Order sun50i-h5-orangepi-pc2.dts nodes in alphabetic
Signed-off-by: Jagan Teki <ja...@amarulasolutions.com>
Acked-by: Jun Nie <jun@linaro.org>
---
arch/arm/dts/sun50i-h5-orangepi-pc2.dts | 56 -
1 file changed, 28 insertions(+), 28 deletions(-)
orangepi-pc2 has usb otg routed host with either EHCI0/OHCI0
sync the same from Linux.
Signed-off-by: Jagan Teki <ja...@amarulasolutions.com>
Acked-by: Jun Nie <jun@linaro.org>
---
arch/arm/dts/sun50i-h5-orangepi-pc2.dts | 13 +
1 file changed, 13 insertions(+)
diff
Allwinner PHY USB code is now part of generic-phy framework,
so drop existing legacy handling like arch/arm/mach-sunxi.c
and related code areas.
Signed-off-by: Jagan Teki <ja...@amarulasolutions.com>
Acked-by: Jun Nie <jun@linaro.org>
---
arch/arm/include/asm/arch-sunxi/usb
Allwinner USB PHY handling can be done through driver-model
generic-phy so add the generic-phy ops to relevant places
on host and musb sunxi driver and enable them in respective
SOC's.
Signed-off-by: Jagan Teki <ja...@amarulasolutions.com>
Acked-by: Jun Nie <jun@linaro.org>
---
a
Sync bananapi-m64 usb_otg node from Linux.
Signed-off-by: Jagan Teki <ja...@amarulasolutions.com>
Acked-by: Jun Nie <jun@linaro.org>
---
arch/arm/dts/sun50i-a64-bananapi-m64.dts | 10 ++
1 file changed, 10 insertions(+)
diff --git a/arch/arm/dts/sun50i-a64-bananapi-m64
Enable USB_MUSB_GADGET which operate OTG in peripheral mode
Signed-off-by: Jagan Teki <ja...@amarulasolutions.com>
Acked-by: Jun Nie <jun@linaro.org>
---
configs/bananapi_m64_defconfig | 1 +
1 file changed, 1 insertion(+)
diff --git a/configs/bananapi_m64_defconf
phy function to allow the sunxi-musb glue to do this.
Signed-off-by: Jagan Teki <ja...@amarulasolutions.com>
Acked-by: Jun Nie <jun@linaro.org>
---
drivers/phy/allwinner/phy-sun4i-usb.c | 6 ++
drivers/usb/musb-new/musb_core.h | 4
drivers/usb/musb-new/musb_uboo
Allwinner PHY USB code is now part of generic-phy framework,
so use it in board_usb_cable_connected.
Signed-off-by: Jagan Teki <ja...@amarulasolutions.com>
Acked-by: Jun Nie <jun@linaro.org>
---
board/sunxi/board.c | 33 -
1 file changed, 32 inse
Sync sun8i-a83t usbphy node details from Linux.
Signed-off-by: Jagan Teki <ja...@amarulasolutions.com>
Acked-by: Jun Nie <jun@linaro.org>
---
arch/arm/dts/sun8i-a83t.dtsi | 20
1 file changed, 20 insertions(+)
diff --git a/arch/arm/dts/sun8i-a83t.dtsi b/
clock gating bits on a64 are different than H3_H5, so fixed
only required bits on clock_sun6i.h.
Signed-off-by: Jagan Teki <ja...@amarulasolutions.com>
Acked-by: Jun Nie <jun@linaro.org>
---
arch/arm/include/asm/arch-sunxi/clock_sun6i.h | 12 +---
1 file changed, 9 inse
Allwinner A31 has 3 USB PHY's and rest similar to A10.
Signed-off-by: Jagan Teki <ja...@amarulasolutions.com>
Acked-by: Jun Nie <jun@linaro.org>
---
drivers/phy/allwinner/phy-sun4i-usb.c | 10 ++
1 file changed, 10 insertions(+)
diff --git a/drivers/phy/allwinner/phy-su
Filling musb_hdrc pdata using structure will unnecessary
add extra ifdefs, so fill them inside probe call for
better code understanding and get rid ifdefs using
devicetree compatible.
Signed-off-by: Jagan Teki <ja...@amarulasolutions.com>
Acked-by: Jun Nie <jun@linaro.org>
---
H3/H5 has 4 USB PHY, rest are similar to A64.
Signed-off-by: Jagan Teki <ja...@amarulasolutions.com>
Acked-by: Jun Nie <jun@linaro.org>
---
drivers/phy/allwinner/phy-sun4i-usb.c | 11 +++
1 file changed, 11 insertions(+)
diff --git a/drivers/phy/allwinner/phy-sun4i-usb.
ID and VBUS detection code require when musb changing
between Host and/or Peripheral modes.
Signed-off-by: Jagan Teki <ja...@amarulasolutions.com>
Acked-by: Jun Nie <jun@linaro.org>
---
drivers/phy/allwinner/phy-sun4i-usb.c | 39 +++
include/phy
Unlike, other Allwinner SUN4I Phy supporting SOC, A83T has
2 USB PHY's and second one is HSIC. So phy control need to
configure to handle these HSIC and SIDDQ requirement.
Signed-off-by: Jagan Teki <ja...@amarulasolutions.com>
Acked-by: Jun Nie <jun@linaro.org>
---
drivers/phy/a
Like other Allwinner SoC, the H3/H5/A64 is missing the config register
from the musb hardware block. Use a known working value for it
like other SoC.
Signed-off-by: Jagan Teki <ja...@amarulasolutions.com>
Acked-by: Jun Nie <jun@linaro.org>
---
drivers/usb/musb-new/musb_regs.h | 3
Unlike other Allwinner SOC's H3/H5/V3s OTG support 4 endpoints
with relevant fifo configs, rest all have 5 endpoints.
So add the fifo configs and defer them based on driver_data.
Signed-off-by: Jagan Teki <ja...@amarulasolutions.com>
Acked-by: Jun Nie <jun@linaro.org>
---
driv
pinctrl, clock and reset
details from DT since the dm code on these will add it future.
Driver named as phy-sun4i-usb.c since the same PHY logic
work for all Allwinner SOC's start from 4I to A64 except 9I
with different phy configurations.
Signed-off-by: Jagan Teki <ja...@amarulasolutions.
Add PHY configs for Allwinner A10/A13/A20 which are SUN4I.
Signed-off-by: Jagan Teki <ja...@amarulasolutions.com>
Acked-by: Jun Nie <jun@linaro.org>
---
drivers/phy/allwinner/phy-sun4i-usb.c | 28
1 file changed, 28 insertions(+)
diff --git a
- add proper macros for musb_config members
- use bool 'true' for multipoint and dyn_fifo instead of numerical 1
Signed-off-by: Jagan Teki <ja...@amarulasolutions.com>
Acked-by: Jun Nie <jun@linaro.org>
---
drivers/usb/musb-new/sunxi.c | 12
1 file changed, 8 inse
Use BIT is possible areas instead of numerical shift.
Signed-off-by: Jagan Teki <ja...@amarulasolutions.com>
Acked-by: Jun Nie <jun@linaro.org>
---
drivers/usb/musb-new/sunxi.c | 28 ++--
1 file changed, 14 insertions(+), 14 deletions(-)
diff --git a/driv
Add OTG device clkgate and reset for H3/H5 through driver_data.
Signed-off-by: Jagan Teki <ja...@amarulasolutions.com>
Acked-by: Jun Nie <jun@linaro.org>
---
drivers/usb/musb-new/sunxi.c | 17 +
1 file changed, 17 insertions(+)
diff --git a/drivers/usb/musb-n
From: Chen-Yu Tsai <w...@csie.org>
Clock gating bits on H43/H5 were wrong, fix them.
Signed-off-by: Chen-Yu Tsai <w...@csie.org>
Reviewed-by: Jagan Teki <ja...@amarulasolutions.com>
Acked-by: Jun Nie <jun@linaro.org>
---
arch/arm/include/asm/arch-sunxi/clock_sun6i.h
Move struct sunxi_ccm_reg pointer to private structure
so-that accessing ccm reg base become more proper way
and avoid local initialization in each function.
Signed-off-by: Jagan Teki <ja...@amarulasolutions.com>
Acked-by: Jun Nie <jun@linaro.org>
---
drivers/usb/host/ehci-
- Drop legacy arch/arm/mach-sunxi/usb_phy.c and related code
Chen-Yu Tsai (1):
sunxi: clock: Fix OHCI clock gating for H3/H5
Jagan Teki (33):
usb: sunxi: Simplify ccm reg base code
musb: sunxi: Add proper macros instead of numericals
musb: sunxi: Use simple way to fill musb_hdrc pdata
musb
Amarula A64-Relic is A64 based IoT device, which support
- Allwinner A64 Cortex-A53
- Mali-400MP2 GPU
- AXP803 PMIC
- 1GB DDR3 RAM
- 8GB eMMC
- AP6330 Wifi/BLE
- MIPI-DSI
- CSI: OV5640 sensor
- USB OTG
- 12V DC power supply
Signed-off-by: Jagan Teki <ja...@amarulasolutions.com>
---
Changes
clock is not enabling.
This patch fixed by passing bit index and the original change
introduced from below commit.
"rtc: sun6i: Add support for the external oscillator gate"
(sha1: 17ecd246414b3a0fe0cb248c86977a8bda465b7b)
Signed-off-by: Michael Trimarchi <mich...@amarulasolutions.com>
Sig
Amarula A64-Relic is Allwinner A64 based IoT device, which support
- Allwinner A64 Cortex-A53
- Mali-400MP2 GPU
- AXP803 PMIC
- 1GB DDR3 RAM
- 8GB eMMC
- AP6330 Wifi/BLE
- MIPI-DSI
- CSI: OV5640 sensor
- USB OTG
- 12V DC power supply
Signed-off-by: Jagan Teki <ja...@amarulasolutions.
On Wed, May 23, 2018 at 1:48 PM, Maxime Ripard
<maxime.rip...@bootlin.com> wrote:
> On Wed, May 23, 2018 at 11:44:56AM +0530, Jagan Teki wrote:
>> On Tue, May 22, 2018 at 8:00 PM, Maxime Ripard
>> <maxime.rip...@bootlin.com> wrote:
>> > On Tue, May 22, 2018 a
On Tue, May 22, 2018 at 8:00 PM, Maxime Ripard
<maxime.rip...@bootlin.com> wrote:
> On Tue, May 22, 2018 at 06:52:28PM +0530, Jagan Teki wrote:
>> Amarula A64-Relic is Allwinner A64 based IoT device, which support
>> - Allwinner A64 Cortex-A53
>> - Mali-400MP2 GPU
>
Amarula A64-Relic is Allwinner A64 based IoT device, which support
- Allwinner A64 Cortex-A53
- Mali-400MP2 GPU
- AXP803 PMIC
- 1GB DDR3 RAM
- 8GB eMMC
- AP6330 Wifi/BLE
- MIPI-DSI
- CSI: OV5640 sensor
- USB OTG
- 12V DC power supply
Signed-off-by: Jagan Teki <ja...@amarulasolutions.
On Tue, May 15, 2018 at 6:19 PM, Jagan Teki <jagannadh.t...@gmail.com> wrote:
> Hi Marek,
>
> On Tue, May 15, 2018 at 2:16 PM, Jun Nie <jun@linaro.org> wrote:
>> 2018-05-07 15:33 GMT+08:00 Jagan Teki <ja...@amarulasolutions.com>:
>>> This series r
Enable HDMI output on sopine board.
Signed-off-by: Jagan Teki <ja...@amarulasolutions.com>
---
Changes for v2:
- none
.../dts/allwinner/sun50i-a64-sopine-baseboard.dts | 26 ++
1 file changed, 26 insertions(+)
diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-
Enable HDMI output on a64-olinuxino board.
Signed-off-by: Jagan Teki <ja...@amarulasolutions.com>
---
Changes for v2:
- none
.../boot/dts/allwinner/sun50i-a64-olinuxino.dts| 26 ++
1 file changed, 26 insertions(+)
diff --git a/arch/arm64/boot/dts/allwinner/sun5
Enable HDMI output on Bananpi-m64 board.
Signed-off-by: Jagan Teki <ja...@amarulasolutions.com>
---
Changes for v2:
- none
.../boot/dts/allwinner/sun50i-a64-bananapi-m64.dts | 26 ++
1 file changed, 26 insertions(+)
diff --git a/arch/arm64/boot/dts/allwinner/sun5
Allwinner SoC like SUN8I and SUN50I are now using DesignWare HDMI
so enable them as default.
Signed-off-by: Jagan Teki <ja...@amarulasolutions.com>
---
Changes for v2:
- Enable for SUN8I
drivers/gpu/drm/sun4i/Kconfig | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm
From: Jernej Skrabec <jernej.skra...@siol.net>
PHY is the same as in H3, except it can select between two clock parent.
Signed-off-by: Jernej Skrabec <jernej.skra...@siol.net>
Signed-off-by: Jagan Teki <ja...@amarulasolutions.com>
---
Changes for v2:
- new patch
dri
From: Jernej Skrabec <jernej.skra...@siol.net>
Some SoCs with DW HDMI have multiple possible clock parents, like A64
and R40.
Expand HDMI PHY clock driver to support second clock parent.
Signed-off-by: Jernej Skrabec <jernej.skra...@siol.net>
Signed-off-by: Ja
HDMI PHY on Allwinner A64 has similar like H3/H5 but with
two clock parents, so add separate compatible for A64.
Signed-off-by: Jagan Teki <ja...@amarulasolutions.com>
---
Changes for v2:
- Add separate compatible for A64
Documentation/devicetree/bindings/display/sunxi/sun4i-drm.txt |
HDMI on Allwinner A64 has similar like H3/H5/A83T.
Add compatible a64 and update A83T compatible as fallback.
Signed-off-by: Jagan Teki <ja...@amarulasolutions.com>
---
Changes for v2:
- Add fallback compatible
Documentation/devicetree/bindings/display/sunxi/sun4i-drm.txt | 1 +
1 file c
Enable DRM Support for Allwinner Display Engine, built as a module.
Signed-off-by: Jagan Teki <ja...@amarulasolutions.com>
---
Changes for v2:
- none
arch/arm64/configs/defconfig | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/def
From: Jernej Skrabec <jernej.skra...@siol.net>
When TCON set up TCON TOP, it needs to know mixer index. Here we do that
by setting engine ID to number provided in mixer index quirk.
Signed-off-by: Jernej Skrabec <jernej.skra...@siol.net>
Signed-off-by: Jagan Teki <ja...@amaru
The DE2 on the A64 is mainly composed of the mixers and tcons,
plus various encoders.
This patch add second mixer and tcon which eventually useful
for testing HDMI. the other part of DE2 will add in future.
Signed-off-by: Jagan Teki <ja...@amarulasolutions.com>
---
Changes for v2:
-
Display Engine(DE2) in Allwinner A64 has two mixers and tcons.
The routing for mixer0 is through tcon0 and connected to
LVDS/RGB/MIPI-DSI controller.
The routing for mixer1 is through tcon1 and connected to HDMI.
Signed-off-by: Jagan Teki <ja...@amarulasolutions.com>
---
Changes for v2:
Allwinner SoC like SUN8I and SUN50I are now using DE2 Mixer
so enable them as default.
Signed-off-by: Jagan Teki <ja...@amarulasolutions.com>
---
Changes for v2:
- Enable for SUN8I
drivers/gpu/drm/sun4i/Kconfig | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/g
According to documentation and experience with other similar SoCs, video
PLLs don't work stable if their output frequency is set below 192 MHz.
Because of that, set minimal rate to both A64 video PLLs to 192 MHz.
Signed-off-by: Jagan Teki <ja...@amarulasolutions.com>
---
Changes for v2:
.
Signed-off-by: Jagan Teki <ja...@amarulasolutions.com>
---
Changes for v2:
- Add fallback compatible for tcon1
- Add separate compatible for mixer1
Documentation/devicetree/bindings/display/sunxi/sun4i-drm.txt | 3 +++
1 file changed, 3 insertions(+)
diff --git a/Documentation/devi
Mixers in Allwinner have similar capabilities as others SoCs with DE2.
Mixer1 has 1 VI and 1 UI planes and supports HW scaling on all
planes.
Signed-off-by: Jagan Teki <ja...@amarulasolutions.com>
---
Changes for v2:
- New patch
drivers/gpu/drm/sun4i/sun8i_mixer.c | 13 +
Allwinner SoC like SUN8I and SUN50I has DE2 CCU so enable them
as default.
Signed-off-by: Jagan Teki <ja...@amarulasolutions.com>
---
Changes for v2:
- Enable for MACH_SUN8I
drivers/clk/sunxi-ng/Kconfig | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/clk/sunxi-ng/Kconfig b/d
DE2 CCU in Allwinner A64 has same like H5, so use the
similar dts details for A64 with fallback compatible.
Signed-off-by: Jagan Teki <ja...@amarulasolutions.com>
---
Changes for v2:
- Add h5 compatible first since A64 came first.
arch/arm64/boot/dts/allwinner/sun50i-a64.dts
Allwinner A64 has DE2 CCU is similar to H3/H5 SoC.
So add compatible for A64 which is fallback compatible
for H5, so update fallback binding.
Signed-off-by: Jagan Teki <ja...@amarulasolutions.com>
Reviewed-by: Rob Herring <r...@kernel.org>
---
Changes for v2:
- Add fallbac
/lkml/2018/4/30/288
[1] https://lkml.org/lkml/2018/4/24/547
Icenowy Zheng (1):
drm: sun4i: add support for HVCC regulator for DWC HDMI glue
Jagan Teki (22):
dt-bindings: clock: Add compatible for A64 DE2 CCU
arm64: dts: allwinner: a64: Add DE2 CCU
clk: sunxi-ng: Enable DE2_CCU for SUN8
Hi Marek,
On Tue, May 15, 2018 at 2:16 PM, Jun Nie <jun@linaro.org> wrote:
> 2018-05-07 15:33 GMT+08:00 Jagan Teki <ja...@amarulasolutions.com>:
>> This series rework of previous version where it removes legacy
>> usb phy handling and added phy driver on generic-p
On Mon, May 14, 2018 at 2:10 PM, Maxime Ripard
<maxime.rip...@bootlin.com> wrote:
> On Mon, May 14, 2018 at 02:03:36PM +0530, Jagan Teki wrote:
>> On Wed, May 2, 2018 at 5:04 PM, Maxime Ripard <maxime.rip...@bootlin.com>
>> wrote:
>> > Hi,
>> >
>>
On Mon, May 14, 2018 at 2:36 PM, Maxime Ripard
<maxime.rip...@bootlin.com> wrote:
> On Mon, May 14, 2018 at 02:34:22PM +0530, Jagan Teki wrote:
>> On Mon, May 14, 2018 at 1:57 PM, Maxime Ripard
>> <maxime.rip...@bootlin.com> wrote:
>> > On Mon, May 14, 2018 a
On Mon, May 14, 2018 at 1:57 PM, Maxime Ripard
<maxime.rip...@bootlin.com> wrote:
> On Mon, May 14, 2018 at 01:34:56PM +0530, Jagan Teki wrote:
>> On Mon, May 14, 2018 at 1:27 PM, Maxime Ripard
>> <maxime.rip...@bootlin.com> wrote:
>> > Hi,
>> >
>>
On Wed, May 2, 2018 at 5:04 PM, Maxime Ripard <maxime.rip...@bootlin.com> wrote:
> Hi,
>
> On Mon, Apr 30, 2018 at 05:10:46PM +0530, Jagan Teki wrote:
>> + hdmi_phy: hdmi-phy@1ef {
>> + compatible = &qu
On Tue, May 1, 2018 at 9:53 PM, Chen-Yu Tsai <w...@csie.org> wrote:
> On Mon, Apr 30, 2018 at 7:40 PM, Jagan Teki <ja...@amarulasolutions.com>
> wrote:
>> Allwinner 64-bit SoC like H5/A64 has DE2 CCU so enable them
>> as default.
>>
>> Signed-off-
On Mon, May 14, 2018 at 1:27 PM, Maxime Ripard
<maxime.rip...@bootlin.com> wrote:
> Hi,
>
> On Mon, May 14, 2018 at 12:37:49PM +0530, Jagan Teki wrote:
>> Hi Maxime and All,
>>
>> We are trying to bring-up AP6330 Wifi chip for A64 board. We noticed
>> to hav
L_LOW>; /* WL-WAKE-AP: PL3 */
interrupt-names = "host-wake";
};
};
And observed rtc-osc32k-out clock is never enabled[1] and the value of
LOSC_OUT_GATING is 0x0 which eventually not enabling
LOSC_OUT_GATING_EN
Pls. let us know if we miss anything here?
[1] https:
On Fri, May 11, 2018 at 11:20 AM, Chen-Yu Tsai <w...@csie.org> wrote:
> On Thu, May 10, 2018 at 10:43 PM, Jagan Teki <ja...@amarulasolutions.com>
> wrote:
>> Amarula A64 Relic is Allwinner A64 based IoT device, which support
>> - Allwinner A64 Cortex-A53
>>
Amarula A64 Relic is A64 based IoT device, which support
- Allwinner A64 Cortex-A53
- Mali-400MP2 GPU
- AXP803 PMIC
- 1GB DDR3 RAM
- 8GB eMMC
- AP6330 Wifi/BLE
- MIPI-DSI
- CSI: OV5640 sensor
- USB OTG
- 12V DC power supply
Signed-off-by: Jagan Teki <ja...@amarulasolutions.com>
---
Changes
Amarula A64 Relic is Allwinner A64 based IoT device, which support
- Allwinner A64 Cortex-A53
- Mali-400MP2 GPU
- AXP803 PMIC
- 1GB DDR3 RAM
- 8GB eMMC
- AP6330 Wifi/BLE
- MIPI-DSI
- CSI: OV5640 sensor
- USB OTG
- 12V DC power supply
Signed-off-by: Jagan Teki <ja...@amarulasolutions.
On 04/04/2018 06:31 PM, Jagan Teki wrote:
On 04/04/2018 05:24 PM, Chen-Yu Tsai wrote:
On Wed, Apr 4, 2018 at 7:09 PM, Jagan Teki <ja...@openedev.com> wrote:
On 04/04/2018 04:31 PM, Jagan Teki wrote:
On 04/03/2018 04:09 PM, Chen-Yu Tsai wrote:
On Tue, Apr 3, 2018 at 6:31 PM, Jagan Te
Sync sun4i-usb-phy bindings from Linux, since the
drivers/phy/allwinner/phy-sun4i-usb.c follow similar.
Sync changes from Linux with below commit:
"phy: sun4i-usb: add support for R40 USB PHY"
(sha1: f3d96f8d23d8e6d0b7642ee946b9b2ac3418fb4d)
Signed-off-by: Jagan Teki <ja...@amarula
Amarula A64-Relic is A64 based IoT device, which support
- Allwinner A64 Cortex-A53
- Mali-400MP2 GPU
- AXP803 PMIC
- 1GB DDR3 RAM
- 8GB eMMC
- AP6330 Wifi/BLE
- MIPI-DSI
- CSI: OV5640 sensor
- USB OTG
- 12V DC power supply
Signed-off-by: Jagan Teki <ja...@amarulasolutions.com>
---
Note:
Amarula A64-Relic is Allwinner A64 based IoT device, which support
- Allwinner A64 Cortex-A53
- Mali-400MP2 GPU
- AXP803 PMIC
- 1GB DDR3 RAM
- 8GB eMMC
- AP6330 Wifi/BLE
- MIPI-DSI
- CSI: OV5640 sensor
- USB OTG
- 12V DC power supply
Signed-off-by: Jagan Teki <ja...@amarulasolutions.
On Sun, Apr 1, 2018 at 8:11 AM, Chen-Yu Tsai wrote:
> On Sun, Apr 1, 2018 at 9:28 AM, André Przywara wrote:
>> On 30/03/18 05:25, Chen-Yu Tsai wrote:
>>
>>
OK. So meanwhile I have something almost(TM) working:
- drivers/clk/sunxi/clk-a64.c,
On Sat, Dec 30, 2017 at 9:10 PM, Icenowy Zheng wrote:
> Allwinner H6 is a new SoC, which have peripherals with highest speed
> among current Allwinner products (USB3.0 and PCI Express); it's memory
> map has also totally changed.
>
> This patchset try to add initial support for
Hi Jun,
On Mon, May 7, 2018 at 1:03 PM, Jagan Teki <ja...@amarulasolutions.com> wrote:
> This series rework of previous version where it removes legacy
> usb phy handling and added phy driver on generic-phy framework.
>
> Current implementation phy driver is unable to
Hi Marek,
On Mon, May 7, 2018 at 5:17 PM, Marek Vasut <ma...@denx.de> wrote:
> On 05/07/2018 09:33 AM, Jagan Teki wrote:
>> Add OTG device clkgate and reset for H3/H5 through driver_data.
>>
>> Signed-off-by: Jagan Teki <ja...@amarulasolutions.com>
>
>
branch 'akpm/master'
Signed-off-by: Jagan Teki <ja...@amarulasolutions.com>
---
Changes for v8:
- %s/follw/follow
- Added merge commit from Linux
doc/device-tree-bindings/phy/sun4i-usb-phy.txt | 65 ++
1 file changed, 65 insertions(+)
create mode 100644 doc/device-tree-
orangepi-pc2 has usb otg routed host with either EHCI0/OHCI0
sync the same from Linux.
Signed-off-by: Jagan Teki <ja...@amarulasolutions.com>
---
arch/arm/dts/sun50i-h5-orangepi-pc2.dts | 13 +
1 file changed, 13 insertions(+)
diff --git a/arch/arm/dts/sun50i-h5-orangepi-pc2.
Enable USB_MUSB_GADGET which operate OTG in peripheral mode
Signed-off-by: Jagan Teki <ja...@amarulasolutions.com>
---
configs/orangepi_prime_defconfig | 1 +
1 file changed, 1 insertion(+)
diff --git a/configs/orangepi_prime_defconfig b/configs/orangepi_prime_defconfig
index df39
orangepi-prime has usb otg routed host with either EHCI0/OHCI0
sync the same from Linux.
Signed-off-by: Jagan Teki <ja...@amarulasolutions.com>
---
arch/arm/dts/sun50i-h5-orangepi-prime.dts | 13 +
1 file changed, 13 insertions(+)
diff --git a/arch/arm/dts/sun50i-h5-or
Enable USB_MUSB_GADGET which operate OTG in peripheral mode
Signed-off-by: Jagan Teki <ja...@amarulasolutions.com>
---
configs/Sinovoip_BPI_M2_Plus_defconfig | 1 +
1 file changed, 1 insertion(+)
diff --git a/configs/Sinovoip_BPI_M2_Plus_defconfig
b/configs/Sinovoip_BPI_M2_Plus_defconfig
Order sun50i-h5-orangepi-pc2.dts nodes in alphabetic
Signed-off-by: Jagan Teki <ja...@amarulasolutions.com>
---
arch/arm/dts/sun50i-h5-orangepi-pc2.dts | 56 -
1 file changed, 28 insertions(+), 28 deletions(-)
diff --git a/arch/arm/dts/sun50i-h5-orangepi-p
Enable USB_MUSB_GADGET which operate OTG in peripheral mode
Signed-off-by: Jagan Teki <ja...@amarulasolutions.com>
---
configs/orangepi_pc2_defconfig | 1 +
1 file changed, 1 insertion(+)
diff --git a/configs/orangepi_pc2_defconfig b/configs/orangepi_pc2_defconfig
index dd5f2c78ab..ca1e
Add PHY configs for Allwinner A10/A13/A20 which are SUN4I.
Signed-off-by: Jagan Teki <ja...@amarulasolutions.com>
---
drivers/phy/allwinner/phy-sun4i-usb.c | 28
1 file changed, 28 insertions(+)
diff --git a/drivers/phy/allwinner/phy-sun4i-usb.c
b/drive
Sync sun4i-usb-phy bindings from Linux, since the
drivers/phy/allwinner/phy-sun4i-usb.c follw similar.
Signed-off-by: Jagan Teki <ja...@amarulasolutions.com>
---
doc/device-tree-bindings/phy/sun4i-usb-phy.txt | 65 ++
1 file changed, 65 insertions(+)
create mode
Bananapi-m2-plus has usb otg routed host with either EHCI0/OHCI0
sync the same from Linux.
Signed-off-by: Jagan Teki <ja...@amarulasolutions.com>
---
arch/arm/dts/sun8i-h3-bananapi-m2-plus.dts | 13 +
1 file changed, 13 insertions(+)
diff --git a/arch/arm/dts/sun8i-h3-banan
From: Jun Nie <jun@linaro.org>
Allwinner H3 have a dual-routed USB PHY0 -- routed to either OHCI/EHCI
or MUSB controller.
Signed-off-by: Jun Nie <jun@linaro.org>
Reviewed-by: Jagan Teki <ja...@openedev.com>
---
arch/arm/dts/sun8i-h3.dtsi | 32 ++
Allwinner A33 has 2 USB PHY's and 0x10 has phy ctrl offset.
Signed-off-by: Jagan Teki <ja...@amarulasolutions.com>
---
drivers/phy/allwinner/phy-sun4i-usb.c | 10 ++
1 file changed, 10 insertions(+)
diff --git a/drivers/phy/allwinner/phy-sun4i-usb.c
b/drivers/phy/allwinner/phy
Allwinner USB PHY handling can be done through driver-model
generic-phy so add the generic-phy ops to relevant places
on host and musb sunxi driver and enable them in respective
SOC's.
Signed-off-by: Jagan Teki <ja...@amarulasolutions.com>
---
arch/arm/mach-sunxi/Kconfig
Allwinner A23 has 2 USB PHY's and 0x04 has phy ctrl offset.
Signed-off-by: Jagan Teki <ja...@amarulasolutions.com>
---
drivers/phy/allwinner/phy-sun4i-usb.c | 9 +
1 file changed, 9 insertions(+)
diff --git a/drivers/phy/allwinner/phy-sun4i-usb.c
b/drivers/phy/allwinner/phy-sun4i
V3S has 1 USB PHY, rest are similar to A64.
Signed-off-by: Jagan Teki <ja...@amarulasolutions.com>
---
drivers/phy/allwinner/phy-sun4i-usb.c | 11 +++
1 file changed, 11 insertions(+)
diff --git a/drivers/phy/allwinner/phy-sun4i-usb.c
b/drivers/phy/allwinner/phy-sun4i-usb.c
phy function to allow the sunxi-musb glue to do this.
Signed-off-by: Jagan Teki <ja...@amarulasolutions.com>
---
drivers/phy/allwinner/phy-sun4i-usb.c | 6 ++
drivers/usb/musb-new/musb_core.h | 4
drivers/usb/musb-new/musb_uboot.c | 19 ---
drivers/usb/mu
Sync bananapi-m64 usb_otg node from Linux.
Signed-off-by: Jagan Teki <ja...@amarulasolutions.com>
---
arch/arm/dts/sun50i-a64-bananapi-m64.dts | 10 ++
1 file changed, 10 insertions(+)
diff --git a/arch/arm/dts/sun50i-a64-bananapi-m64.dts
b/arch/arm/dts/sun50i-a64-bananapi-m
Allwinner A31 has 3 USB PHY's and rest similar to A10.
Signed-off-by: Jagan Teki <ja...@amarulasolutions.com>
---
drivers/phy/allwinner/phy-sun4i-usb.c | 10 ++
1 file changed, 10 insertions(+)
diff --git a/drivers/phy/allwinner/phy-sun4i-usb.c
b/drivers/phy/allwinner/phy-sun4i
Unlike, other Allwinner SUN4I Phy supporting SOC, A83T has
2 USB PHY's and second one is HSIC. So phy control need to
configure to handle these HSIC and SIDDQ requirement.
Signed-off-by: Jagan Teki <ja...@amarulasolutions.com>
---
drivers/phy/allwinner/phy-sun4i-usb.
Sync sun8i-a83t usbphy node details from Linux.
Signed-off-by: Jagan Teki <ja...@amarulasolutions.com>
---
arch/arm/dts/sun8i-a83t.dtsi | 20
1 file changed, 20 insertions(+)
diff --git a/arch/arm/dts/sun8i-a83t.dtsi b/arch/arm/dts/sun8i-a83t.dtsi
index bab6
H3/H5 has 4 USB PHY, rest are similar to A64.
Signed-off-by: Jagan Teki <ja...@amarulasolutions.com>
---
drivers/phy/allwinner/phy-sun4i-usb.c | 11 +++
1 file changed, 11 insertions(+)
diff --git a/drivers/phy/allwinner/phy-sun4i-usb.c
b/drivers/phy/allwinner/phy-sun4i-usb.c
Enable USB_MUSB_GADGET which operate OTG in peripheral mode
Signed-off-by: Jagan Teki <ja...@amarulasolutions.com>
---
configs/bananapi_m64_defconfig | 1 +
1 file changed, 1 insertion(+)
diff --git a/configs/bananapi_m64_defconfig b/configs/bananapi_m64_defconfig
index 47f31c6d9d..40c1
ID and VBUS detection code require when musb changing
between Host and/or Peripheral modes.
Signed-off-by: Jagan Teki <ja...@amarulasolutions.com>
---
drivers/phy/allwinner/phy-sun4i-usb.c | 39 +++
include/phy-sun4i-usb.h
Move struct sunxi_ccm_reg pointer to private structure
so-that accessing ccm reg base become more proper way
and avoid local initialization in each function.
Signed-off-by: Jagan Teki <ja...@amarulasolutions.com>
---
drivers/usb/host/ehci-sunxi.c | 15 +--
drivers/usb/hos
supported
- tested on bpi-m2-plus, orangepi_pc2/prime, bananapi-m64
Changes for v4:
- Rework of previous series
- Add Allwinner sun4i USB PHY driver
- Drop legacy arch/arm/mach-sunxi/usb_phy.c and related code
Chen-Yu Tsai (1):
sunxi: clock: Fix OHCI clock gating for H3/H5
Jagan Teki (33):
usb
Like other Allwinner SoC, the H3/H5/A64 is missing the config register
from the musb hardware block. Use a known working value for it
like other SoC.
Signed-off-by: Jagan Teki <ja...@amarulasolutions.com>
---
Note:
- About previous version comment, at this point the core can't
Unlike other Allwinner SOC's H3/H5/V3s OTG support 4 endpoints
with relevant fifo configs, rest all have 5 endpoints.
So add the fifo configs and defer them based on driver_data.
Signed-off-by: Jagan Teki <ja...@amarulasolutions.com>
---
drivers/usb/musb-new/sunxi.
pinctrl, clock and reset
details from DT since the dm code on these will add it future.
Driver named as phy-sun4i-usb.c since the same PHY logic
work for all Allwinner SOC's start from 4I to A64 except 9I
with different phy configurations.
Signed-off-by: Jagan Teki <ja...@amarulasolutions.
Add OTG device clkgate and reset for H3/H5 through driver_data.
Signed-off-by: Jagan Teki <ja...@amarulasolutions.com>
---
drivers/usb/musb-new/sunxi.c | 17 +
1 file changed, 17 insertions(+)
diff --git a/drivers/usb/musb-new/sunxi.c b/drivers/usb/musb-new/sunxi.c
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