Hi,
Dne sreda, 22. februar 2017 ob 21:17:29 CET je Icenowy Zheng napisal(a):
> 2017年2月23日 03:09于 Maxime Ripard 写道:
>
> > Hi,
> >
> > On Wed, Feb 22, 2017 at 11:18:48PM +0800, Icenowy Zheng wrote:
> > > +config SUNXI_DE2_CCU
> > > + bool "Support for the
Hi,
Dne sreda, 22. februar 2017 ob 16:18:50 CET je Icenowy Zheng napisal(a):
> Allwinner have a new "Display Engine 2.0" in there new SoCs, which comes
> in a new "Display Engine" (mixers instead of old backends and
> frontends).
>
> Add support for the mixer on Allwinner V3s SoC; it's the
Hi,
Dne petek, 24. februar 2017 ob 14:30:36 CET je Rob Herring napisal(a):
> On Wed, Feb 22, 2017 at 2:09 PM, Maxime Ripard
>
> wrote:
> > Hi,
> >
> > On Wed, Feb 22, 2017 at 11:23:06PM +0800, Icenowy Zheng wrote:
> >> Allwinner have a new "Display Engine 2.0"
left from you is for DE2. HDMI stuff is basically copied from Rockhip
> > driver (including EDID reading), TCON code is now reverted to the same as
> > it is in sunxi_display.c. I think it is worth to take a look at EDID code
> > and compare it.
>
> So is the
Dne sreda, 30. november 2016 ob 20:37:24 CET je Jean-Francois Moine
napisal(a):
> On Wed, 30 Nov 2016 20:14:11 +0100
>
> Jernej Škrabec <jernej.skra...@gmail.com> wrote:
> > Dne četrtek, 01. december 2016 ob 03:03:14 CET je Icenowy Zheng
napisal(a):
> > > 20
Hi,
Dne sreda, 22. marec 2017 ob 08:45:48 CET je Maxime Ripard napisal(a):
> On Tue, Mar 21, 2017 at 11:26:46PM +0100, Jernej Škrabec wrote:
> > Hi,
> >
> > Dne torek, 21. marec 2017 ob 20:34:33 CET je Maxime Ripard napisal(a):
> > > Hi,
> > >
> &g
Hi,
Dne sreda, 29. marec 2017 ob 21:46:08 CEST je Icenowy Zheng napisal(a):
> Allwinner have a new "Display Engine 2.0" in their new SoCs, which comes
> with mixers to do graphic processing and feed data to TCON, like the old
> backends and frontends.
>
> Add support for the mixer on Allwinner
Dne petek, 24. marec 2017 ob 16:53:07 CET je Maxime Ripard napisal(a):
> On Wed, Mar 22, 2017 at 06:19:12PM +0100, Jernej Škrabec wrote:
> > Hi,
> >
> > Dne sreda, 22. marec 2017 ob 08:45:48 CET je Maxime Ripard napisal(a):
> > > On Tue, Mar 21, 2017 at 11:26:46
Hi,
Dne torek, 21. marec 2017 ob 20:34:33 CET je Maxime Ripard napisal(a):
> Hi,
>
> On Mon, Mar 20, 2017 at 11:01:25PM +0100, Jernej Skrabec wrote:
> > diff --git a/include/configs/sun50i.h b/include/configs/sun50i.h
> > index 1b7bfb6c22..146f7f4e1b 100644
> > --- a/include/configs/sun50i.h
> >
Dne petek, 21. april 2017 ob 09:04:13 CEST je Maxime Ripard napisal(a):
> Hi Jernej,
>
> On Mon, Mar 27, 2017 at 07:22:28PM +0200, Jernej Skrabec wrote:
> > This series implements support for HDMI output. This is done using
> > DM video framework and sharing the HDMI controller code with RK3288.
lcdc_enable((struct sunxi_lcdc_reg *)SUNXI_LCD0_BASE, 0);
>
> That one is suspicious. Shouldn't sunxi_composer_enable be left, and
> lcdc_enable called only once?
Uh, missed that. Probably fixup error. It will be fixed in next version.
Best regards,
Jernej Škrabec
>
Hi Nickey,
Dne petek, 10. marec 2017 ob 03:19:44 CET je Nickey.Yang napisal(a):
> Hi Jernej,
>
> 在 2017年03月09日 07:34, Jernej Skrabec 写道:
> > Designware HDMI controller and phy are used in other SoCs as well. Split
> > out platform independent code.
> >
> > DW HDMI has 8 bit registers but they
Hi,
Dne ponedeljek, 13. marec 2017 ob 13:33:43 CET je Simon Glass napisal(a):
> Hi,
>
> On 8 March 2017 at 16:34, Jernej Skrabec wrote:
> > This is needed for HDMI, which will be added later.
> >
> > Signed-off-by: Jernej Skrabec
> > ---
> >
Hi!
Dne sreda, 01. marec 2017 ob 08:04:40 CET je Chen-Yu Tsai napisal(a):
> According to the BSP released by Banana Pi, the R40 (sun8iw11p1) has
> an extra "PLL lock control" register in the CCU, which controls whether
> the individual PLL lock status bits in each PLL's control register work
> or
Dne sobota, 01. april 2017 ob 06:20:52 CEST je Simon Glass napisal(a):
> Hi Jernej,
>
> On 20 March 2017 at 16:01, Jernej Skrabec wrote:
> > This series implements support for HDMI output. This is done using
> > DM video framework and sharing the HDMI controller code
Hi Chen-Yu,
Dne ponedeljek, 31. julij 2017 ob 07:13:34 CEST je Chen-Yu Tsai napisal(a):
> Hi Jernej,
>
> On Mon, Jul 31, 2017 at 12:41 AM, Jernej Skrabec
>
> wrote:
> > During development of H3 HDMI driver, I found some issues with
> > setting video clock rate. It
Hi Chen-Yu,
Dne ponedeljek, 31. julij 2017 ob 07:02:18 CEST je Chen-Yu Tsai napisal(a):
> On Mon, Jul 31, 2017 at 12:41 AM, Jernej Skrabec
>
> wrote:
> > Currently ccu_frac_helper_set_rate() doesn't wait for a lock bit to be
> > set before returning. Because of that,
Hi,
Dne sreda, 02. avgust 2017 ob 07:02:39 CEST je icen...@aosc.io napisal(a):
> 在 2017-08-02 12:53,Jernej Škrabec 写道:
>
> > Hi Icenowy,
> >
> > Dne torek, 01. avgust 2017 ob 15:12:52 CEST je Icenowy Zheng
> >
> > napisal(a):
> >> Allwinner H3 fe
Hi Icenowy,
Dne torek, 01. avgust 2017 ob 15:12:58 CEST je Icenowy Zheng napisal(a):
> As we have already the support for the DE2 on Allwinner H3, add the
> display engine pipeline device tree nodes to its DTSI file.
>
> The H5 pipeline has some differences and will be enabled later.
>
>
Hi Icenowy,
Dne torek, 01. avgust 2017 ob 15:12:52 CEST je Icenowy Zheng napisal(a):
> Allwinner H3 features a "Display Engine 2.0".
>
> Add device tree bindings for the following parts:
> - H3 TCONs
> - H3 Mixers
> - H3 Display engine
>
> Signed-off-by: Icenowy Zheng
> ---
>
Hi Chen-Yu,
Dne petek, 04. avgust 2017 ob 06:29:50 CEST je Chen-Yu Tsai napisal(a):
> On Fri, Aug 4, 2017 at 12:16 PM, Icenowy Zheng wrote:
> > 于 2017年8月4日 GMT+08:00 下午12:15:27, Chen-Yu Tsai 写到:
> >>Hi,
> >>
> >>On Tue, Aug 1, 2017 at 9:13 PM, Icenowy Zheng
Hi Maxime,
Dne ponedeljek, 24. april 2017 ob 09:19:40 CEST je Maxime Ripard napisal(a):
> Hi Jernej,
>
> On Fri, Apr 21, 2017 at 07:24:12PM +0200, Jernej Škrabec wrote:
> > Dne petek, 21. april 2017 ob 09:04:13 CEST je Maxime Ripard napisal(a):
> > > Hi Jernej,
> >
Hi Maxime,
Dne ponedeljek, 24. april 2017 ob 09:19:40 CEST je Maxime Ripard napisal(a):
> Hi Jernej,
>
> On Fri, Apr 21, 2017 at 07:24:12PM +0200, Jernej Škrabec wrote:
> > Dne petek, 21. april 2017 ob 09:04:13 CEST je Maxime Ripard napisal(a):
> > > Hi Jernej,
> >
Hi Maxime,
Dne torek, 25. april 2017 ob 10:57:05 CEST je Maxime Ripard napisal(a):
> On Mon, Apr 24, 2017 at 11:54:22PM +0200, Jernej Škrabec wrote:
> > Hi Maxime,
> >
> > Dne ponedeljek, 24. april 2017 ob 09:19:40 CEST je Maxime Ripard
napisal(a):
> > > Hi Jerne
Hi Chen-Yu,
Dne petek, 04. avgust 2017 ob 11:27:33 CEST je Chen-Yu Tsai napisal(a):
> On Fri, Aug 4, 2017 at 4:59 PM, Jernej Škrabec <jernej.skra...@siol.net>
wrote:
> > Hi Chen-Yu,
> >
> > Dne petek, 04. avgust 2017 ob 06:29:50 CEST je Chen-Yu Tsai napisal(a):
> &
Hi,
Dne četrtek, 10. avgust 2017 ob 02:21:21 CEST je Rob Herring napisal(a):
> On Wed, Aug 02, 2017 at 09:06:26PM +0200, Jernej Škrabec wrote:
> > Hi,
> >
> > Dne sreda, 02. avgust 2017 ob 07:02:39 CEST je icen...@aosc.io napisal(a):
> > > 在 2017-08-02 12:53,Jernej
Hi,
Dne sreda, 17. maj 2017 ob 18:43:49 CEST je Icenowy Zheng napisal(a):
> The DE2 mixer can do color space correction needed by TV Encoder with
> its DCSC sub-engine.
>
> Add support for it.
>
> Signed-off-by: Icenowy Zheng
> ---
> drivers/gpu/drm/sun4i/sun8i_mixer.c | 35
>
Hi,
Dne sreda, 17. maj 2017 ob 18:43:53 CEST je Icenowy Zheng napisal(a):
> As we have already the support for the TV encoder on Allwinner H3, add
> the display engine pipeline device tree nodes to its DTSI file.
>
> The H5 pipeline has some differences and will be enabled later.
>
> The
Hi,
Dne ponedeljek, 15. maj 2017 ob 08:11:55 CEST je Maxime Ripard napisal(a):
> On Sun, May 14, 2017 at 09:03:19PM -0600, Simon Glass wrote:
> > Hi,
> >
> > On 12 May 2017 at 10:06, Maxime Ripard
wrote:
> > > Hi Jernej,
> > >
> > > The patch content looks
Hi,
Dne ponedeljek, 15. maj 2017 ob 08:31:22 CEST je Maxime Ripard napisal(a):
> On Sat, May 13, 2017 at 11:14:00PM +0800, Chen-Yu Tsai wrote:
> > >>> +static int sunxi_tve_get_plug_in_status(void)
> > >>> +{
> > >>> + struct sunxi_tve_reg * const tve =
> > >>> + (struct
Hi Maxime,
Dne petek, 12. maj 2017 ob 17:47:17 CEST je Maxime Ripard napisal(a):
> Hi Jernej,
>
> On Wed, May 10, 2017 at 06:46:29PM +0200, Jernej Skrabec wrote:
> > This patch adds support for TV encoder clocks which will be used later.
> >
> > Signed-off-by: Jernej Skrabec
Hi!
Dne petek, 09. junij 2017 ob 18:51:02 CEST je Icenowy Zheng napisal(a):
> 于 2017年6月10日 GMT+08:00 上午12:49:15, Maxime Ripard 写到:
> >On Wed, Jun 07, 2017 at 04:48:50PM +0800, Icenowy Zheng wrote:
> >> >> @@ -189,6 +211,8 @@ supported.
> >> >>
> >> >>
Hi,
Dne sobota, 20. maj 2017 ob 03:37:53 CEST je Chen-Yu Tsai napisal(a):
> On Sat, May 20, 2017 at 2:23 AM, Jernej Škrabec <jernej.skra...@siol.net>
wrote:
> > Hi,
> >
> > Dne petek, 19. maj 2017 ob 20:08:18 CEST je Icenowy Zheng napisal(a):
> >> 于 2017年5月20
Hi Maxime,
Dne ponedeljek, 22. maj 2017 ob 09:35:56 CEST je Maxime Ripard napisal(a):
> On Fri, May 19, 2017 at 05:41:17PM +0200, Jernej Skrabec wrote:
> > This commit adds support for TV (composite) output.
> >
> > Because there is no mechanism to select TV standard, PAL is
> > hardcoded.
>
>
写道:
> >>
> >> > On Mon, May 22, 2017 at 07:55:56PM +0200, Jernej Škrabec wrote:
> >> > > Hi,
> >> > >
> >> > > Dne sobota, 20. maj 2017 ob 03:37:53 CEST je Chen-Yu Tsai
> >
> >napisal(a):
> >> > > &
Hi,
Dne torek, 23. maj 2017 ob 22:22:14 CEST je Maxime Ripard napisal(a):
> Hi Jernej,
>
> On Mon, May 22, 2017 at 08:49:57PM +0200, Jernej Škrabec wrote:
> > Dne ponedeljek, 22. maj 2017 ob 09:35:56 CEST je Maxime Ripard napisal(a):
> > > On Fri, May 19, 2017 at 05:41:17
Hi!
Dne petek, 19. maj 2017 ob 19:49:58 CEST je Icenowy Zheng napisal(a):
> 于 2017年5月20日 GMT+08:00 上午1:47:29, Maxime Ripard 写到:
> >On Thu, May 18, 2017 at 12:43:45AM +0800, Icenowy Zheng wrote:
> >> From: Icenowy Zheng
> >>
> >> Allwinner H3
Hi,
Dne petek, 19. maj 2017 ob 20:08:18 CEST je Icenowy Zheng napisal(a):
> 于 2017年5月20日 GMT+08:00 上午2:03:30, Maxime Ripard 写到:
> >On Thu, May 18, 2017 at 12:43:50AM +0800, Icenowy Zheng wrote:
> >> Allwinner H3 features a TV encoder similar to the one in
Hi!
Dne sreda, 07. junij 2017 ob 16:38:27 CEST je Maxime Ripard napisal(a):
> On Wed, Jun 07, 2017 at 06:01:02PM +0800, Icenowy Zheng wrote:
> > >I have no idea what this is supposed to be doing either.
> > >
> > >I might be wrong, but I really feel like there's a big mismatch
> > >between your
Hi!
Dne sreda, 31. maj 2017 ob 09:58:19 CEST je Chen-Yu Tsai napisal(a):
> The AR100 clock in the PRCM has parents, one of which is pll-periph from
> the main CCU.
>
> Add it to the list of required clocks for the PRCM CCU.
>
> Signed-off-by: Chen-Yu Tsai
> ---
>
Hi,
Dne nedelja, 04. junij 2017 ob 18:01:42 CEST je Icenowy Zheng napisal(a):
> From: Icenowy Zheng
>
> Allwinner H3 has two special TCONs, both come without channel0. And the
> TCON1 of H3 has no special clocks even for the channel1.
>
> Add support for these kinds of TCON.
Hi,
Dne petek, 05. maj 2017 ob 12:07:09 CEST je Andre Przywara napisal(a):
> Hi,
>
> (re-adding the list)
>
> On 05/05/17 05:49, Pajeet Gurav wrote:
> > thank you so much andre! I guess I'll just mooch the code off the
> > u-boot sources and write simple pixel writing routines using that.
>
>
Hi,
Dne sobota, 30. september 2017 ob 13:58:03 CEST je Alexey Kardashevskiy
napisal(a):
> On 21/09/17 06:01, Jernej Skrabec wrote:
> > [added media mailing list due to CEC question]
> >
> > This patch series adds a HDMI glue driver for Allwinner H3 SoC. For now,
> > only video and CEC
Hi Marcus!
Dne nedelja, 03. september 2017 ob 17:08:06 CEST je codekip...@gmail.com
napisal(a):
> From: Marcus Cooper
>
> Add the new DAI blocks to the device tree. I2S0 and I2S1 are for
> connecting to an external codec whereas I2S2 is used for HDMI
> audio.
>
>
Hi!
Dne torek, 28. november 2017 ob 16:54:42 CET je Maxime Ripard napisal(a):
> Hi,
>
> On Mon, Nov 27, 2017 at 09:57:34PM +0100, Jernej Skrabec wrote:
> > Since the time initial DE2 driver was written, some knowledge was gained
> > what setting are really necessary and what most of the magic
Hi!
Dne torek, 28. november 2017 ob 21:55:50 CET je Maxime Ripard napisal(a):
> On Mon, Nov 27, 2017 at 09:57:46PM +0100, Jernej Skrabec wrote:
> > DE2 have many CSC units - channel input CSC, channel output CSC and
> > mixer output CSC and maybe more.
> >
> > Fortunately, they have all same
Hi!
Dne torek, 28. november 2017 ob 22:00:01 CET je Maxime Ripard napisal(a):
> Hi,
>
> On Mon, Nov 27, 2017 at 09:57:41PM +0100, Jernej Skrabec wrote:
> > This commit adds basic support for VI planes. They are meant for video
> > overlay and because of that they support YUV formats too.
Hi,
Dne torek, 28. november 2017 ob 22:00:01 CET je Maxime Ripard napisal(a):
> Hi,
>
> On Mon, Nov 27, 2017 at 09:57:41PM +0100, Jernej Skrabec wrote:
> > This commit adds basic support for VI planes. They are meant for video
> > overlay and because of that they support YUV formats too.
Hi Julian,
Dne sreda, 29. november 2017 ob 22:48:34 CET je Julian Calaby napisal(a):
> Hi Jernej,
>
> On Tue, Nov 28, 2017 at 7:57 AM, Jernej Skrabec
wrote:
> > Calculate scaling parameters and call appropriate scaler set up
> > function.
> >
> > Signed-off-by: Jernej
Hi Maxime,
Dne torek, 05. december 2017 ob 11:36:18 CET je Maxime Ripard napisal(a):
> Hi,
>
> On Fri, Dec 01, 2017 at 07:05:23AM +0100, Jernej Skrabec wrote:
> > Current DE2 driver is very basic and uses a lot of magic constants since
> > there is no documentation and knowledge about it was
Hi,
Dne petek, 18. maj 2018 ob 17:26:51 CEST je Maxime Ripard napisal(a):
> On Fri, May 18, 2018 at 04:46:41PM +0200, Jernej Škrabec wrote:
> > > And this is a bit sloppy, since if phy_clk_num == 3, you won't try to
> > > lookup pll-2 either.
> >
> > It is hi
Hi,
Dne nedelja, 20. maj 2018 ob 04:09:52 CEST je Julian Calaby napisal(a):
> Hi Jernej,
>
> On Sun, May 20, 2018 at 11:57 AM, Julian Calaby
wrote:
> > Hi Jernej,
> >
> > On Sun, May 20, 2018 at 4:31 AM, Jernej Skrabec
wrote:
> >> R40
Hi,
Dne ponedeljek, 21. maj 2018 ob 10:05:17 CEST je Maxime Ripard napisal(a):
> On Sat, May 19, 2018 at 08:31:17PM +0200, Jernej Skrabec wrote:
> > As already described in DT binding, TCON TOP is responsible for
> > configuring display pipeline. In this initial driver focus is on HDMI
> >
Hi,
Dne ponedeljek, 21. maj 2018 ob 10:01:47 CEST je Maxime Ripard napisal(a):
> Hi,
>
> On Sat, May 19, 2018 at 08:31:16PM +0200, Jernej Skrabec wrote:
> > TCON TOP main purpose is to configure whole display pipeline. It
> > determines relationships between mixers and TCONs, selects source TCON
Hi,
Dne ponedeljek, 21. maj 2018 ob 10:12:53 CEST je Maxime Ripard napisal(a):
> On Sat, May 19, 2018 at 08:31:24PM +0200, Jernej Skrabec wrote:
> > Expand HDMI PHY clock driver to support second clock parent.
> >
> > Signed-off-by: Jernej Skrabec
> > ---
> >
> >
Hi,
Dne ponedeljek, 21. maj 2018 ob 10:07:59 CEST je Maxime Ripard napisal(a):
> On Sat, May 19, 2018 at 08:31:18PM +0200, Jernej Skrabec wrote:
> > If SoC has TCON TOP unit, it has to be configured from TCON, since it
> > has all information needed. Additionally, if it is TCON TV, it must also
>
Hi,
Dne četrtek, 24. maj 2018 ob 10:43:51 CEST je Maxime Ripard napisal(a):
> Hi,
>
> On Mon, May 21, 2018 at 05:15:15PM +0200, Jernej Škrabec wrote:
> > > > + /*
> > > > +* Default register values might have some reserved bits set,
which
> >
Hi,
Dne petek, 18. maj 2018 ob 17:26:51 CEST je Maxime Ripard napisal(a):
> On Fri, May 18, 2018 at 04:46:41PM +0200, Jernej Škrabec wrote:
> > > And this is a bit sloppy, since if phy_clk_num == 3, you won't try to
> > > lookup pll-2 either.
> >
> > It is hi
Hi,
Dne petek, 18. maj 2018 ob 17:09:40 CEST je Sergey Suloev napisal(a):
> Hi, guys,
>
> On 05/18/2018 05:46 PM, Jernej Škrabec wrote:
> > Hi,
> >
> > Dne petek, 18. maj 2018 ob 12:01:16 CEST je Maxime Ripard napisal(a):
> >> On Fri, May 18, 2018 a
Hi,
Dne petek, 18. maj 2018 ob 12:01:16 CEST je Maxime Ripard napisal(a):
> On Fri, May 18, 2018 at 03:15:22PM +0530, Jagan Teki wrote:
> > From: Jernej Skrabec
> >
> > Some SoCs with DW HDMI have multiple possible clock parents, like A64
> > and R40.
> >
> > Expand
Hi,
Dne četrtek, 26. april 2018 ob 15:26:49 CEST je Jagan Teki napisal(a):
> On Wed, Apr 25, 2018 at 11:29 PM, Jernej Škrabec
>
> <jernej.skra...@siol.net> wrote:
> > Hi,
> >
> > Dne sreda, 25. april 2018 ob 12:34:09 CEST je Jagan Teki napisal(a):
> >&g
Hi,
Dne četrtek, 04. januar 2018 ob 15:45:18 CET je Chen-Yu Tsai napisal(a):
> On Sun, Dec 31, 2017 at 5:01 AM, Jernej Skrabec
wrote:
> > For example, A83T have nmp plls which are modelled as nkmp plls. Since k
> > is not specified, it has offset 0, shift 0 and lowest
Hi Laurent,
Dne torek, 09. januar 2018 ob 17:08:55 CET je Laurent Pinchart napisal(a):
> Hello,
>
> On Tuesday, 9 January 2018 17:58:46 EET Jernej Škrabec wrote:
> > Dne torek, 09. januar 2018 ob 11:43:08 CET je Archit Taneja napisal(a):
> > > On 12/31/2017 02:31
Hi Chen-Yu,
Dne ponedeljek, 08. januar 2018 ob 10:19:47 CET je Chen-Yu Tsai napisal(a):
> On Fri, Jan 5, 2018 at 3:28 AM, Jernej Škrabec <jernej.skra...@siol.net>
wrote:
> > Hi,
> >
> > Dne četrtek, 04. januar 2018 ob 15:45:18 CET je Chen-Yu Tsai napisal(a):
> >
Hi Archit,
Dne torek, 09. januar 2018 ob 11:43:08 CET je Archit Taneja napisal(a):
> On 12/31/2017 02:31 AM, Jernej Skrabec wrote:
> > Parts of PHY code could be useful also for custom PHYs. For example,
> > Allwinner A83T has custom PHY which is probably Synopsys gen2 PHY
> > with few additional
Hi Laurent,
Dne torek, 09. januar 2018 ob 14:30:22 CET je Laurent Pinchart napisal(a):
> Hi Jernej,
>
> Thank you for the patch.
>
> On Saturday, 30 December 2017 23:01:56 EET Jernej Skrabec wrote:
> > Parts of PHY code could be useful also for custom PHYs. For example,
> > Allwinner A83T has
Hi,
Dne torek, 09. januar 2018 ob 17:08:55 CET je Laurent Pinchart napisal(a):
> Hello,
>
> On Tuesday, 9 January 2018 17:58:46 EET Jernej Škrabec wrote:
> > Dne torek, 09. januar 2018 ob 11:43:08 CET je Archit Taneja napisal(a):
> > > On 12/31/2017 02:31 AM, Jernej Skr
Hi,
Dne četrtek, 18. januar 2018 ob 11:58:41 CET je Maxime Ripard napisal(a):
> Hi,
>
> On Wed, Jan 17, 2018 at 09:14:11PM +0100, Jernej Skrabec wrote:
> > This commit changes formula from this:
> >
> > Freq = (parent_freq * N * K) / (M * P)
> >
> > to this:
> >
> > Freq = (parent_freq / M) *
Hi all,
Dne sreda, 10. januar 2018 ob 20:25:04 CET je Jernej Skrabec napisal(a):
> Parts of PHY code could be useful also for custom PHYs. For example,
> Allwinner A83T has custom PHY which is probably Synopsys gen2 PHY
> with few additional memory mapped registers, so most of the Synopsys PHY
>
Hi,
Dne ponedeljek, 29. januar 2018 ob 19:05:26 CET je Rob Herring napisal(a):
> On Wed, Jan 17, 2018 at 09:14:15PM +0100, Jernej Skrabec wrote:
> > This commit adds all necessary compatibles and descriptions needed to
> > implement A83T HDMI pipeline.
> >
> > Mixer is already properly
Hi Maxime,
(previously I respond only to linux-sunxi mailing list)
>On Mon, Jan 29, 2018 at 10:22:23AM +0100, codekip...@gmail.com wrote:
>> From: Marcus Cooper
>>
>> Add the new DAI block for I2S2 which is used for HDMI audio.
>>
>> Signed-off-by: Marcus Cooper
Dne četrtek, 08. februar 2018 ob 10:15:35 CET je Icenowy Zheng napisal(a):
> 在 2018-02-08 17:00,Maxime Ripard 写道:
>
> > On Tue, Feb 06, 2018 at 09:16:47PM +0800, Icenowy Zheng wrote:
> >> Banana Pi M2 Zero board is a H2+-based board by Sinovoip, with a form
> >> factor and GPIO holes similar to
Hi,
Dne torek, 02. januar 2018 ob 09:14:37 CET je Icenowy Zheng napisal(a):
> 在 2018年1月2日星期二 CST 下午4:11:04,Chen-Yu Tsai 写道:
>
> > On Sat, Dec 30, 2017 at 7:30 PM, Icenowy Zheng wrote:
> > > The H3/H5 SoCs have a HDMI output and a TV Composite output.
> > >
> > > Add simplefb
Hi Rob,
Dne sreda, 03. januar 2018 ob 21:21:54 CET je Rob Herring napisal(a):
> On Sat, Dec 30, 2017 at 10:01:58PM +0100, Jernej Skrabec wrote:
> > This commit adds all necessary compatibles and descriptions needed to
> > implement A83T HDMI pipeline.
> >
> > Mixer is already properly described,
Hi!
Dne sreda, 15. avgust 2018 ob 14:07:45 CEST je Icenowy Zheng napisal(a):
> The glue in sun4i-drm of dw-hdmi currently doesn't set the clocks of
> dw-hdmi exclusively, which will lead the display fails to initialize in
> some situations.
>
> Add the exclusivity to sun8i-dw-hdmi and
Hi!
Dne sreda, 15. avgust 2018 ob 15:43:19 CEST je Icenowy Zheng napisal(a):
> 于 2018年8月15日 GMT+08:00 下午9:39:44, "Jernej Škrabec"
写到:
> >Hi!
> >
> >Dne sreda, 15. avgust 2018 ob 14:07:45 CEST je Icenowy Zheng
> >
> >napisal(a):
> >> Th
Dne torek, 07. avgust 2018 ob 14:31:03 CEST je Paul Kocialkowski napisal(a):
> Hi,
>
> On Fri, 2018-07-27 at 16:58 +0200, Jernej Škrabec wrote:
> > Dne petek, 27. julij 2018 ob 16:03:41 CEST je Jernej Škrabec napisal(a):
> > > Hi!
> > >
> > > Dne sred
Dne torek, 04. september 2018 ob 11:18:47 CEST je Chen-Yu Tsai napisal(a):
> On Sun, Sep 2, 2018 at 3:27 PM Jernej Skrabec
wrote:
> > Allwinner H6 SoC has multiplier N range between 1 and 254. Since parent
> > rate is 24MHz, intermediate result when calculating final rate easily
> > overflows 32
Dne torek, 04. september 2018 ob 11:04:21 CEST je Chen-Yu Tsai napisal(a):
> On Sun, Sep 2, 2018 at 3:27 PM Jernej Skrabec
wrote:
> > Support for mixer0, mixer1, writeback and rotation units is added.
> >
> > Signed-off-by: Jernej Skrabec
> > Signed-off-by: Icenowy Zheng
> > ---
> >
> >
Dne sreda, 05. september 2018 ob 09:03:35 CEST je Maxime Ripard napisal(a):
> On Tue, Sep 04, 2018 at 10:06:06PM +0530, Jagan Teki wrote:
> > Allwinner SoC like SUN8I and SUN50I has DE2 CCU so enable them
> > as default.
> >
> > Signed-off-by: Jagan Teki
> > ---
> > Changes for v4, v3:
> > -
Hi Jagan,
Dne sreda, 05. september 2018 ob 09:57:54 CEST je Jagan Teki napisal(a):
> On Wed, Sep 5, 2018 at 1:21 PM, Maxime Ripard
wrote:
> > On Wed, Sep 05, 2018 at 12:56:03PM +0530, Jagan Teki wrote:
> >> On Tue, Sep 4, 2018 at 10:10 AM, Icenowy Zheng wrote:
> >> > From: Jagan Teki
> >> >
Dne ponedeljek, 10. september 2018 ob 16:23:54 CEST je Maxime Ripard
napisal(a):
> On Fri, Sep 07, 2018 at 03:22:34PM +0800, Icenowy Zheng wrote:
> > The R40 HDMI PHY seems to be different to the A64 one, the A64 one
> > has no input mux, but the R40 one has.
> >
> > Drop the A64 fallback
Hi,
Dne sreda, 07. marec 2018 ob 21:30:42 CET je @lex napisal(a):
> ops, i mean turning ON.
>
> On Wednesday, March 7, 2018 at 5:26:59 PM UTC-3, @lex wrote:
> > Hi,
> >
> > Turning HDMI monitor during boot or after complete boot kernel shows the
> > following error:
> >
> > [ 14.842605] []
lank=0* just in case but did not help.
> >
> > Kernel is based on megous's work a few days ago, maybe i missed some other
> > patch?
>
> My 4.15 branch has the old HDMI patches. Try with 4.16 branch, wich has a
> fairly recent version of the patches including this fix
Hi Maxime,
Dne sreda, 28. februar 2018 ob 08:36:08 CET je Maxime Ripard napisal(a):
> On Tue, Feb 27, 2018 at 11:26:51PM +0100, Jernej Skrabec wrote:
> > TCON checks for LVDS properties even if it doesn't support it. Add a
> > check to skip that part of the code if TCON doesn't support channel 0.
Hi Maxime,
Dne torek, 27. februar 2018 ob 23:26:45 CET je Jernej Skrabec napisal(a):
> This series implements H3/H5 HDMI driver. It was tested on OrangePi 2 (H3),
> OrangePi Plus2e (H3) and OrangePi PC2 (H5) with many resolutions and it
> works well. Bug, which prevented correct operation for
Hi,
Dne sreda, 28. februar 2018 ob 08:34:40 CET je Maxime Ripard napisal(a):
> Hi,
>
> On Tue, Feb 27, 2018 at 11:26:46PM +0100, Jernej Skrabec wrote:
> > Some NM PLLs doesn't work well when their output clock rate is set below
> > certain rate.
> >
> > Add support for that constrain.
> >
> >
Hi,
Dne četrtek, 08. marec 2018 ob 23:47:17 CET je Ondřej Jirman napisal(a):
> Hi,
>
> On Thu, Mar 01, 2018 at 10:34:32PM +0100, Jernej Skrabec wrote:
> > Currently exclusive TCON clock lock is never released, which, for
> > example, prevents changing resolution on HDMI.
> >
> > In order to fix
which is set when clock rate is protected and unset
when it is unprotected. That way we could track if clk_rate_exclusive_put()
needs to be called or not.
Best regards,
Jernej
>
> regards,
> o.
>
> On Fri, Mar 09, 2018 at 01:13:14AM +0100, 'Ondřej Jirman' via linux-sunxi
wro
> >>
> >>> [] (commit_tail+0x80/0x84)
> >>
> >> [ 58.905950] [] (commit_tail) from []
> >>
> >>> (drm_atomic_helper_commit+0x120/0x124)
> >>
> >> [ 58.906034] [] (drm_atomic_helper_commit) from []
> >>
> &g
Hi,
Dne torek, 24. april 2018 ob 15:34:21 CEST je Jagan Teki napisal(a):
> HDMI on Allwinner A64 has similar behavior like H3/H5, so
> reuse the same dts node details for A64.
>
> Signed-off-by: Jagan Teki
> ---
> arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi | 28
>
Hi,
Dne torek, 24. april 2018 ob 15:34:12 CEST je Jagan Teki napisal(a):
> Allwinner A64 has display engine pipeline like other Allwinner SOC's
> A83T/H3/H5.
>
> A64 DE2 behaviour similar to Allwinner A83T where mixer0, connected to tcon0
> with RGB, LVDS MIPI-DSI and mixer1, connected to tcon1
Hi,
Dne sobota, 31. marec 2018 ob 21:40:17 CEST je ML napisal(a):
> Hi,
>
> Currently developing a custom kernel for a A64, I need to display images &
> videos on HDMI screen. How can I code the Display Engine? It is only two
> pages in the SOC datasheet. Any real manual out there (couldn't
Hi all,
Dne sreda, 21. marec 2018 ob 03:18:13 CET je Icenowy Zheng napisal(a):
> 于 2018年3月21日 GMT+08:00 上午2:46:46, Maxime Ripard
写到:
> >On Sat, Mar 17, 2018 at 01:53:49AM +0800, Icenowy Zheng wrote:
> >> All the sub-blocks of Allwinner A64 DE2 needs the SRAM C on A64
Hi,
Dne petek, 16. marec 2018 ob 15:02:13 CET je Icenowy Zheng napisal(a):
> The Allwinner H6 SoC has a CCU which has been largely rearranged.
>
> Add support for it in the sunxi-ng CCU framework.
>
> Signed-off-by: Icenowy Zheng
> Acked-by: Maxime Ripard
Hi!
Dne ponedeljek, 05. marec 2018 ob 16:27:00 CET je Joonas Kylmälä napisal(a):
> Jernej Skrabec:
> > +_out {
> > + hdmi_out_con: endpoint {
> > + remote-endpoint = <_con_in>;
> > + };
> > +};
>
> This node is added to all the DTS files you enabled HDMI on. Is it
> something that
Hi Julian,
Dne nedelja, 25. februar 2018 ob 09:11:34 CET je Julian Calaby napisal(a):
> Hi Jernej,
>
> On Sun, Feb 25, 2018 at 8:45 AM, Jernej Skrabec
wrote:
> > Enable HDMI output on all boards which have HDMI connector.
> >
> > Signed-off-by: Jernej Skrabec
Hi,
Dne ponedeljek, 26. februar 2018 ob 10:38:00 CET je Maxime Ripard napisal(a):
> Hi,
>
> On Sat, Feb 24, 2018 at 10:45:31PM +0100, Jernej Skrabec wrote:
> > Some NM PLLs doesn't work well when their output clock rate is set below
> > certain rate.
> >
> > Add support for that constrain.
>
>
Hi,
Dne ponedeljek, 26. februar 2018 ob 10:39:30 CET je Maxime Ripard napisal(a):
> Hi,
>
> On Sat, Feb 24, 2018 at 10:45:38PM +0100, Jernej Skrabec wrote:
> > Current polarity configuration code is cleary wrong since it compares
> > same flag two times. However, even if flag name is fixed, it
Hi all,
Dne sobota, 24. februar 2018 ob 22:45:41 CET je Jernej Skrabec napisal(a):
> While A83T HDMI PHY seems to be just customized Synopsys HDMI PHY, H3
> HDMI PHY is completely custom PHY.
>
> However, they still have many things in common like clock and reset
> setup, setting sync polarity
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