On Sat, May 10, 2014 at 01:46:38PM -0300, Emilio López wrote:
There was probably something interesting here, but both the messages
you sent are full of empty :)
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patches.
Thanks!
Maxime
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, and the sun?i*.dts changes to enable this
have already been upstreamed.
For both patches,
Acked-by: Maxime Ripard maxime.rip...@free-electrons.com
Thanks!
Maxime
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;
+ };
+
You should set the vmmc-supply property here, like in
http://lists.infradead.org/pipermail/linux-arm-kernel/2014-May/255064.html
Thanks,
Maxime
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On Mon, May 12, 2014 at 05:14:26PM +0800, Chen-Yu Tsai wrote:
Hi,
On Sat, May 10, 2014 at 8:56 PM, Maxime Ripard
maxime.rip...@free-electrons.com wrote:
The USB phy controller in the A31 differs mostly from the older controllers
because it has a clock dedicated for each phy, while
and USB OTG.
Signed-off-by: Hans de Goede hdego...@redhat.com
Applied, thanks.
Maxime
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The A31 USB clock slightly differ from its older counterparts, mostly because
it has a different gate for each PHY, while the older one had a single gate for
all the phy.
Signed-off-by: Maxime Ripard maxime.rip...@free-electrons.com
Reviewed-by: Hans de Goede hdego...@redhat.com
---
drivers/clk
The USB clocks of the A31 seems to be parented to the 24MHz oscillator, and
handle the clocks for the USB phys and OHCI devices.
Signed-off-by: Maxime Ripard maxime.rip...@free-electrons.com
Reviewed-by: Hans de Goede hdego...@redhat.com
---
arch/arm/boot/dts/sun6i-a31.dtsi | 11 +++
1
-electrons.com
Signed-off-by: Maxime Ripard maxime.rip...@free-electrons.com
Reviewed-by: Hans de Goede hdego...@redhat.com
---
arch/arm/boot/dts/Makefile| 1 +
arch/arm/boot/dts/sun6i-a31-app4-evb1.dts | 57 +++
2 files changed, 58 insertions(+)
create mode
The A31 has two ECHI/OHCI controllers, and one OHCI-only phy-less controller.
Signed-off-by: Maxime Ripard maxime.rip...@free-electrons.com
Reviewed-by: Hans de Goede hdego...@redhat.com
---
arch/arm/boot/dts/sun6i-a31.dtsi | 77
1 file changed, 77
The USB phy controller in the A31 differs mostly from the older controllers
because it has a clock dedicated for each phy, while the older ones were having
a single clock for all the phys.
Signed-off-by: Maxime Ripard maxime.rip...@free-electrons.com
Reviewed-by: Hans de Goede hdego...@redhat.com
retrieval
ARM: sunxi: dt: add APP4-EVB1 board support
Maxime Ripard (6):
clk: sunxi: Implement A31 USB clock
ARM: sun6i: Add the USB clocks to the DTSI.
phy: sunxi: Rework phy initialization
phy: usb: sunxi: Introduce Allwinner A31 USB PHY support
usb: ohci-platform: Enable optional use
-off-by: Boris BREZILLON boris.brezil...@free-electrons.com
Signed-off-by: Maxime Ripard maxime.rip...@free-electrons.com
Reviewed-by: Hans de Goede hdego...@redhat.com
---
Documentation/devicetree/bindings/usb/usb-ehci.txt | 1 +
drivers/usb/host/ehci-platform.c | 17
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The A31 has two ECHI/OHCI controllers, and one OHCI-only phy-less controller.
Signed-off-by: Maxime Ripard maxime.rip...@free-electrons.com
Reviewed-by: Hans de Goede hdego...@redhat.com
---
arch/arm/boot/dts/sun6i-a31.dtsi | 77
1 file changed, 77
The USB clocks of the A31 seems to be parented to the 24MHz oscillator, and
handle the clocks for the USB phys and OHCI devices.
Signed-off-by: Maxime Ripard maxime.rip...@free-electrons.com
Reviewed-by: Hans de Goede hdego...@redhat.com
---
arch/arm/boot/dts/sun6i-a31.dtsi | 11 +++
1
The A31 USB clock slightly differ from its older counterparts, mostly because
it has a different gate for each PHY, while the older one had a single gate for
all the phy.
Signed-off-by: Maxime Ripard maxime.rip...@free-electrons.com
Reviewed-by: Hans de Goede hdego...@redhat.com
Acked-by: Mike
function instead of the
private structure since it was the only user
Boris BREZILLON (2):
usb: ehci-platform: add optional reset controller retrieval
ARM: sunxi: dt: add APP4-EVB1 board support
Maxime Ripard (6):
clk: sunxi: Implement A31 USB clock
ARM: sun6i: Add the USB clocks to the DTSI
Move the phy initialization and variables declaration to the loop itself, since
it is where it really belongs. Also remove all the temporary variables, we can
use the structure members directly.
Signed-off-by: Maxime Ripard maxime.rip...@free-electrons.com
Reviewed-by: Hans de Goede hdego
-off-by: Boris BREZILLON boris.brezil...@free-electrons.com
Signed-off-by: Maxime Ripard maxime.rip...@free-electrons.com
Reviewed-by: Hans de Goede hdego...@redhat.com
---
Documentation/devicetree/bindings/usb/usb-ehci.txt | 1 +
drivers/usb/host/ehci-platform.c | 26
The USB phy controller in the A31 differs mostly from the older controllers
because it has a clock dedicated for each phy, while the older ones were having
a single clock for all the phys.
Signed-off-by: Maxime Ripard maxime.rip...@free-electrons.com
Reviewed-by: Hans de Goede hdego...@redhat.com
-electrons.com
Signed-off-by: Maxime Ripard maxime.rip...@free-electrons.com
Reviewed-by: Hans de Goede hdego...@redhat.com
---
arch/arm/boot/dts/Makefile| 1 +
arch/arm/boot/dts/sun6i-a31-app4-evb1.dts | 57 +++
2 files changed, 58 insertions(+)
create mode
);
+
+ vchan_dma_desc_free_list(vchan-vc, head);
shouldn't you kill the tasklet as well here?
Just to be clear, which tasklet? vchan's or the driver's?
Thanks,
Maxime
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-off-by: Boris BREZILLON boris.brezil...@free-electrons.com
Signed-off-by: Maxime Ripard maxime.rip...@free-electrons.com
Reviewed-by: Hans de Goede hdego...@redhat.com
Acked-by: Alan Stern st...@rowland.harvard.edu
---
Documentation/devicetree/bindings/usb/usb-ehci.txt | 1 +
drivers/usb/host/ehci
The OHCI controllers used in the Allwinner A31 are asserted in reset using a
global reset controller.
Add optional support for such a controller in the OHCI platform driver.
Signed-off-by: Maxime Ripard maxime.rip...@free-electrons.com
Reviewed-by: Hans de Goede hdego...@redhat.com
Acked
Move the phy initialization and variables declaration to the loop itself, since
it is where it really belongs. Also remove all the temporary variables, we can
use the structure members directly.
Signed-off-by: Maxime Ripard maxime.rip...@free-electrons.com
Reviewed-by: Hans de Goede hdego
The A31 has two ECHI/OHCI controllers, and one OHCI-only phy-less controller.
Signed-off-by: Maxime Ripard maxime.rip...@free-electrons.com
Reviewed-by: Hans de Goede hdego...@redhat.com
---
arch/arm/boot/dts/sun6i-a31.dtsi | 77
1 file changed, 77
assertion/deassertion to probe/remove
- Moved the dedicated_clocks to the probe function instead of the
private structure since it was the only user
Boris BREZILLON (2):
usb: ehci-platform: add optional reset controller retrieval
ARM: sunxi: dt: add APP4-EVB1 board support
Maxime Ripard
-electrons.com
Signed-off-by: Maxime Ripard maxime.rip...@free-electrons.com
Reviewed-by: Hans de Goede hdego...@redhat.com
---
arch/arm/boot/dts/Makefile| 1 +
arch/arm/boot/dts/sun6i-a31-app4-evb1.dts | 57 +++
2 files changed, 58 insertions(+)
create mode
The USB clocks of the A31 seems to be parented to the 24MHz oscillator, and
handle the clocks for the USB phys and OHCI devices.
Signed-off-by: Maxime Ripard maxime.rip...@free-electrons.com
Reviewed-by: Hans de Goede hdego...@redhat.com
---
arch/arm/boot/dts/sun6i-a31.dtsi | 11 +++
1
The A31 USB clock slightly differ from its older counterparts, mostly because
it has a different gate for each PHY, while the older one had a single gate for
all the phy.
Signed-off-by: Maxime Ripard maxime.rip...@free-electrons.com
Reviewed-by: Hans de Goede hdego...@redhat.com
Acked-by: Mike
On Wed, May 14, 2014 at 11:18:51AM +0530, Kishon Vijay Abraham I wrote:
Hi,
On Tuesday 13 May 2014 09:14 PM, Maxime Ripard wrote:
Move the phy initialization and variables declaration to the loop itself,
since
it is where it really belongs. Also remove all the temporary variables, we
, ir;
+ interrupts = 0 6 4;
+ reg = 0x01C21c00 0x40;
You're mixing upper and lower case letters here, please make it lower
case.
Thanks!
Maxime
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We actually never used clkdev at all in the Allwinner support. Hence, this
registration has always been dead code that can be removed.
Signed-off-by: Maxime Ripard maxime.rip...@free-electrons.com
---
drivers/clk/sunxi/clk-a10-hosc.c | 3 +--
drivers/clk/sunxi/clk-a20-gmac.c | 2 --
drivers
},
{ .compatible = allwinner,sun5i-a13-usb-phy },
+ { .compatible = allwinner,sun6i-a31-usb-phy },
Do you have Documentation for this comptible binding? Would be good to mention
that in the commit log.
Ah right. I forgot.
I'm sending you a followup patch.
Thanks!
Maxime
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On Tue, May 13, 2014 at 05:44:14PM +0200, Maxime Ripard wrote:
Hi everyone,
This patchset adds support for the USB controllers found in the
Allwinner A31.
While the design is similar to the earlier Allwinner SoCs that are
already supported, a few details here and there change, like
The A31 USB clock slightly differ from its older counterparts, mostly because
it has a different gate for each PHY, while the older one had a single gate for
all the phy.
Signed-off-by: Maxime Ripard maxime.rip...@free-electrons.com
Reviewed-by: Hans de Goede hdego...@redhat.com
Acked-by: Mike
Document the freshly introduced compatible for the USB phy in use in the
Allwinner A31 SoC.
Signed-off-by: Maxime Ripard maxime.rip...@free-electrons.com
---
.../devicetree/bindings/phy/sun4i-usb-phy.txt | 23 --
1 file changed, 17 insertions(+), 6 deletions(-)
diff
= rc_allocate_device();
+
You can drop the extra line here
Maxime
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On Wed, May 14, 2014 at 02:56:00PM +0200, Maxime Ripard wrote:
The A31 USB clock slightly differ from its older counterparts, mostly because
it has a different gate for each PHY, while the older one had a single gate
for
all the phy.
Signed-off-by: Maxime Ripard maxime.rip...@free
-by in
sunxi/drivers-for-3.16, and patch 7 in sunxi/dt-for-3.16.
Thanks!
Maxime
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On Wed, May 07, 2014 at 02:33:18PM -0700, Guenter Roeck wrote:
On Tue, May 06, 2014 at 09:44:19PM -0500, Maxime Ripard wrote:
Most of the watchdog code is duplicated between the machine restart code and
the watchdog driver. Add the restart hook to the watchdog driver, to be
able
.
After reverting this patch everything works again.
Right, it seems like we're still using clkdev for the clock protection
bits.
Let's drop this patch.
Thanks,
Maxime
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.
Other subdevices might be added later (if needed).
Signed-off-by: Boris BREZILLON boris.brezil...@free-electrons.com
Acked-by: Maxime Ripard maxime.rip...@free-electrons.com
---
drivers/mfd/Kconfig | 8 +++
drivers/mfd/Makefile | 1 +
drivers/mfd/sun6i-prcm.c
!
Maxime
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we selected in
kernel config. This matches the build behavior of the kernel itself
after splitting up sunxi support to various SoCs in Kconfig.
Maxime, could you take this?
Applied, thanks.
Maxime
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subdevices.
Other subdevices might be added later (if needed).
Signed-off-by: Boris BREZILLON boris.brezil...@free-electrons.com
Acked-by: Maxime Ripard maxime.rip...@free-electrons.com
---
drivers/mfd/Kconfig | 8 +++
drivers/mfd/Makefile | 1
)
and reset controller subdevices.
Other subdevices might be added later (if needed).
Signed-off-by: Boris BREZILLON boris.brezil...@free-electrons.com
Acked-by: Maxime Ripard maxime.rip...@free-electrons.com
---
drivers/mfd/Kconfig | 8
On Wed, May 21, 2014 at 11:01:05AM +0530, Vinod Koul wrote:
On Tue, May 13, 2014 at 03:42:58PM +0200, Maxime Ripard wrote:
Hi Vinod,
On Wed, Apr 30, 2014 at 12:34:08PM +0530, Vinod Koul wrote:
+
+static int sun6i_dma_terminate_all(struct sun6i_vchan *vchan
On Wed, May 21, 2014 at 07:43:30PM +0200, Hans de Goede wrote:
bus-width defaults to 1, and all 4 lines are hooked up at the cubietruck,
properly set bus-width to 4.
Signed-off-by: Hans de Goede hdego...@redhat.com
Merged the two patches, thanks!
Maxime
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protecting patches
- Minor fixes here and there as suggested by Andy Shevchenko: switch
to dmam_pool_create, switch to dev_dbg instead of pr_debug, etc.
Maxime Ripard (2):
Documentation: dt: Add Allwinner A31 DMA controller bindings
dmaengine: sun6i: Add driver for the Allwinner A31 DMA controller
On Mon, May 19, 2014 at 05:04:22PM +0200, Maxime Ripard wrote:
On Thu, May 15, 2014 at 11:11:23AM +0200, Maxime Ripard wrote:
On Wed, May 07, 2014 at 02:33:18PM -0700, Guenter Roeck wrote:
On Tue, May 06, 2014 at 09:44:19PM -0500, Maxime Ripard wrote:
Most of the watchdog code
On Thu, May 22, 2014 at 09:39:43PM +0100, One Thousand Gnomes wrote:
On Thu, 22 May 2014 22:34:44 +0200
Maxime Ripard maxime.rip...@free-electrons.com wrote:
On Mon, May 19, 2014 at 05:04:22PM +0200, Maxime Ripard wrote:
On Thu, May 15, 2014 at 11:11:23AM +0200, Maxime Ripard wrote
,
Maxime
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On Thu, May 22, 2014 at 02:12:07PM -0700, Guenter Roeck wrote:
On Thu, May 22, 2014 at 10:34:44PM +0200, Maxime Ripard wrote:
On Mon, May 19, 2014 at 05:04:22PM +0200, Maxime Ripard wrote:
On Thu, May 15, 2014 at 11:11:23AM +0200, Maxime Ripard wrote:
On Wed, May 07, 2014 at 02:33:18PM
Hi Greg,
On Wed, May 14, 2014 at 06:05:20PM +0200, Greg Kroah-Hartman wrote:
On Wed, May 14, 2014 at 02:34:19PM +0200, Maxime Ripard wrote:
On Tue, May 13, 2014 at 05:44:14PM +0200, Maxime Ripard wrote:
Hi everyone,
This patchset adds support for the USB controllers found
On Sat, May 24, 2014 at 07:19:40AM +0900, Greg Kroah-Hartman wrote:
On Fri, May 23, 2014 at 08:33:39PM +0200, Maxime Ripard wrote:
Hi Greg,
On Wed, May 14, 2014 at 06:05:20PM +0200, Greg Kroah-Hartman wrote:
On Wed, May 14, 2014 at 02:34:19PM +0200, Maxime Ripard wrote:
On Tue, May
/jwrdegoede/u-boot-sunxi/commits/sunxi-test
Maxime
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some patches for the A31. Unfortunately, we haven't
figured out the DRAM initialization, so it's second-stage-only at the
moment.
Maxime
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the
interrupts directly from the device tree.
Can you be a bit more precise on this?
What is the issue that this patch fix?
Maxime
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+
I told you numerous times already that I wanted this patch to be split
into at least three of them:
- One to add the device to the DTSI.
- One to add the pins
- and one to enable the devices in the DTS.
Please address this comment.
Maxime
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On Tue, May 27, 2014 at 03:53:18PM -0700, Greg Kroah-Hartman wrote:
On Thu, May 15, 2014 at 11:14:38AM +0200, Maxime Ripard wrote:
Hi Greg,
On Wed, May 14, 2014 at 06:05:20PM +0200, Greg Kroah-Hartman wrote:
On Wed, May 14, 2014 at 02:34:19PM +0200, Maxime Ripard wrote:
On Tue, May
On Tue, May 27, 2014 at 11:01:03AM +0200, Hans de Goede wrote:
Hi,
On 05/27/2014 10:09 AM, Maxime Ripard wrote:
On Mon, May 26, 2014 at 09:47:58AM +0200, Hans de Goede wrote:
With level triggered interrupt mask / unmask will get called for each
interrupt, doing the somewhat expensive mux
On Tue, May 27, 2014 at 06:14:31PM +0200, Tomasz Figa wrote:
On 27.05.2014 10:07, Maxime Ripard wrote:
On Mon, May 26, 2014 at 09:47:57AM +0200, Hans de Goede wrote:
From: Chen-Yu Tsai w...@csie.org
The sunxi pinctrl irq chip driver does not support wakeup at the
moment. Adding
On Wed, May 28, 2014 at 11:51:52AM +0200, Hans de Goede wrote:
Hi,
On 05/28/2014 11:36 AM, Maxime Ripard wrote:
On Tue, May 27, 2014 at 04:18:29PM +0200, Linus Walleij wrote:
On Mon, May 26, 2014 at 9:47 AM, Hans de Goede hdego...@redhat.com wrote:
With level triggered interrupt mask
On Tue, May 27, 2014 at 08:17:43PM -0400, jonsm...@gmail.com wrote:
On Sun, May 25, 2014 at 2:34 PM, Maxime Ripard
maxime.rip...@free-electrons.com wrote:
On Sat, May 24, 2014 at 11:50:20AM -0400, jonsm...@gmail.com wrote:
I seem to have fried TX on my TTL serial converter. I can't get a new
serie with minor modifications
(remove the cfg_reg_from_bank that doesn't make any sense).
Thanks,
Maxime
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Signed-off-by: Hans de Goede hdego...@redhat.com
Acked-by: Maxime Ripard maxime.rip...@free-electrons.com
Thanks!
Maxime
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On Sat, May 31, 2014 at 11:13:05AM +0200, Hans de Goede wrote:
Hi,
On 05/28/2014 12:33 PM, Maxime Ripard wrote:
On Wed, May 28, 2014 at 11:51:52AM +0200, Hans de Goede wrote:
Hi,
On 05/28/2014 11:36 AM, Maxime Ripard wrote:
On Tue, May 27, 2014 at 04:18:29PM +0200, Linus Walleij wrote
, but we should add a check for
func being !NULL here, otherwise, the kernel is going to blow up at
the next line.
And since gpio_to_irq might not be called before the request_irq, you
might be in such a case.
Maxime
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, thanks.
Maxime
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);
+
+ spin_unlock_irqrestore(pctl-lock, flags);
+}
Please at least call sunxi_pinctrl_irq_ack and
sunxi_pinctrl_irq_unmask if you're doing this.
Maxime
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: No PMIC hook to init smartreflex
[0.782419] sr_init: platform driver register failed for SR
Could you remove the loglevel parameter, and repost what you have?
Maxime
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to it eventually, but I don't get
what it would bring here.
Have different compatible strings for the various revisions of the IP
is much simpler and adds no code at all.
Maxime
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On Fri, Jun 13, 2014 at 08:09:36AM -0400, jonsm...@gmail.com wrote:
On Fri, Jun 13, 2014 at 6:15 AM, Maxime Ripard
maxime.rip...@free-electrons.com wrote:
On Fri, Jun 13, 2014 at 11:54:06AM +0200, Hans de Goede wrote:
Hi,
On 06/13/2014 10:40 AM, Maxime Ripard wrote:
On Fri, Jun 13
, but it doesn't apply, since the above node
doesn't exist. Please rebase on top of v3.16-rc1 and resend the patch.
Maxime
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Hi,
On Mon, Jun 09, 2014 at 12:08:11AM +0600, Alexander Bersenev wrote:
This patch adds pins for two IR controllers on A20
Signed-off-by: Alexander Bersenev b...@hackerdom.ru
Signed-off-by: Alexsey Shestacov wingr...@linux-sunxi.org
Applied, thanks.
Maxime
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wingr...@linux-sunxi.org
Applied, thanks.
Maxime
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On Tue, Jun 03, 2014 at 05:13:17PM +0200, Hans de Goede wrote:
Hi,
On 06/03/2014 03:30 PM, Maxime Ripard wrote:
On Sat, May 31, 2014 at 04:01:38PM +0200, Hans de Goede wrote:
For level triggered gpio interrupts we need to use handle_fasteoi_irq,
like we do with the irq-sunxi-nmi driver
].init_data = NULL;
+ matches[i].of_node = NULL;
+ }
+
That looks rather hackish, especially since we've never been in such a
case yet, since we have a single PMIC in our system.
Can't you just use memzero here?
Maxime
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.
Signed-off-by: Chen-Yu Tsai w...@csie.org
Acked-by: Maxime Ripard maxime.rip...@free-electrons.com
Maxime
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sun4i_mod0_config = {
.pwidth = 2,
};
+static struct clk_factors_config sun6i_a31_mbus_config = {
+ .mshift = 0,
+ .mwidth = 3,
Actually, the A31 has an extra N factor.
So this mbus clock looks like it's only about the A23, and not the A31
at all.
Maxime
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will know about the odd values.
Signed-off-by: Chen-Yu Tsai w...@csie.org
Acked-by: Maxime Ripard maxime.rip...@free-electrons.com
Maxime
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is
the same as the A31. To make it clear, we add a new compatible for
the A23, allwinner,sun8i-a23-apb0-gates-clk.
Signed-off-by: Chen-Yu Tsai w...@csie.org
Acked-by: Maxime Ripard maxime.rip...@free-electrons.com
Maxime
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that on older Allwinner SoCs, such
as the A10 or A20, but the N factor starts from 1 instead of 0.
This patch adds support for PLL1 and all the basic clock gates.
Signed-off-by: Chen-Yu Tsai w...@csie.org
Except for the minor comment below, you have my
Acked-by: Maxime Ripard maxime.rip
that it will actually work for the A31, since it does
define some dividers anyway, and the divider table is !NULL, even
though there's actually no dividers defined.
Maxime
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on the
previous patches, so I'm not even sure this patch can go as is.
It would be much easier if you (ChenYu) could introduce first a very
basic with just the UART support, and then, as separate series,
clocks, PRCM, MMC, and so on.
Maxime
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Acked-by: Maxime Ripard maxime.rip...@free-electrons.com
Maxime
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On Thu, Jun 19, 2014 at 12:33:41PM +0800, Chen-Yu Tsai wrote:
On Wed, Jun 18, 2014 at 6:26 PM, Maxime Ripard
maxime.rip...@free-electrons.com wrote:
On Tue, Jun 17, 2014 at 10:52:49PM +0800, Chen-Yu Tsai wrote:
The A23 has an almost identical PRCM clock tree. The difference in
the APB0
On Thu, May 22, 2014 at 02:12:07PM -0700, Guenter Roeck wrote:
On Thu, May 22, 2014 at 10:34:44PM +0200, Maxime Ripard wrote:
On Mon, May 19, 2014 at 05:04:22PM +0200, Maxime Ripard wrote:
On Thu, May 15, 2014 at 11:11:23AM +0200, Maxime Ripard wrote:
On Wed, May 07, 2014 at 02:33:18PM
On Sat, Jun 21, 2014 at 05:04:05PM +0600, Alexander Bersenev wrote:
This patch adds records for two IR controllers on A20
Signed-off-by: Alexander Bersenev b...@hackerdom.ru
Signed-off-by: Alexsey Shestacov wingr...@linux-sunxi.org
Applied, thanks.
Maxime
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tree some patches that were depending on this one based on that
assumption.
And now, we have a regression.
Anyway... I guess I should just revert some commits now.
Maxime
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Applied, thanks
Maxime
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On Fri, Jun 20, 2014 at 10:52:50PM +0800, Chen-Yu Tsai wrote:
The Allwinner A23 is a dual-core Cortex-A7-based SoC. It re-uses most of
the IPs found in previous SoCs, notably the A31.
Signed-off-by: Chen-Yu Tsai w...@csie.org
Applied, thanks
Maxime
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Maxime Ripard, Free Electrons
On Fri, Jun 20, 2014 at 10:52:52PM +0800, Chen-Yu Tsai wrote:
The Allwinner A23 is a tablet oriented SoC with 2 Cortex-A7 cores
and a Mali-400MP2 GPU.
Signed-off-by: Chen-Yu Tsai w...@csie.org
Applied, thanks
Maxime
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Fixed the whitespace warning and applied.
Thanks!
Maxime
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On Mon, Jun 23, 2014 at 01:08:24PM -0700, Александр Берсенев wrote:
Thanks,
Should I send applied patches in the further versions of this patch set?
No, you don't have to.
Maxime
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for the basic clocks in the A23, just
PLL1 for cpus, and the system bus clocks and gates.
The last patch adds the DT nodes for the newly added clocks.
Patch 1 should be merged for 3.16, while the rest should go in 3.17.
Why should it go in for 3.16? Is there any user for it yet?
Maxime
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Maxime
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Signed-off-by: Chen-Yu Tsai w...@csie.org
Acked-by: Maxime Ripard maxime.rip...@free-electrons.com
Maxime
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