, thanks!
Maxime
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sequencing bindings.
The WiFi module supports out-of-band interrupt signaling via GPIO,
but this is buggy and not enabled yet.
Signed-off-by: Chen-Yu Tsai w...@csie.org
There's two almost identical patches 12/12. Which one am I suppose to
apply?
Thanks!
Maxime
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On Tue, Mar 10, 2015 at 04:27:10PM +0100, Hans de Goede wrote:
Signed-off-by: Hans de Goede hdego...@redhat.com
Some commit log would have been nice, but I just applied the patch.
Thanks!
Maxime
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don't use
the pinctrl header.
Applied the two patches, thanks!
Maxime
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Signed-off-by: Hans de Goede hdego...@redhat.com
Applied, thanks!
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On Wed, Mar 11, 2015 at 05:08:08PM +0800, Chen-Yu Tsai wrote:
On Wed, Mar 11, 2015 at 4:52 PM, Maxime Ripard
maxime.rip...@free-electrons.com wrote:
On Wed, Mar 11, 2015 at 11:11:49AM +0800, Chen-Yu Tsai wrote:
On Wed, Mar 11, 2015 at 5:32 AM, Maxime Ripard
maxime.rip...@free-electrons.com
board config to devicetree, so that we only need to maintain dts files
and not both dts files and u-boot board configs.
I had the plan to remove all earlyprintk in the bootargs of the DTS, I
can do it to convert all DTS to use stdout-path as well.
Maxime
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.
Applied both, thanks!
Maxime
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On Mon, Mar 23, 2015 at 04:43:09PM -0700, Chen-Yu Tsai wrote:
On Sat, Mar 21, 2015 at 11:20 AM, Maxime Ripard
maxime.rip...@free-electrons.com wrote:
On Fri, Mar 20, 2015 at 02:49:18PM +0800, Chen-Yu Tsai wrote:
Hi Maxime,
Here's v2 of the sunxi cpufreq dts fixes, aimed at 4.0
On Fri, Mar 20, 2015 at 07:52:49PM +0100, Hans de Goede wrote:
From: Maxime Ripard maxime.rip...@free-electrons.com
The SRAM the EMAC is using might not have been mapped accordingly by the
bootloader, preventing the EMAC to work properly.
Ask for that SRAM to be mapped at probe time
;
+ reg = 0x01c0 0x30;
+ };
+
dma: dma-controller@01c02000 {
compatible = allwinner,sun4i-a10-dma;
reg = 0x01c02000 0x1000;
--
2.3.3
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people would like to see arch-timer and SMP
supported with PSCI, but work on this has been slow. So
in the mean time, I thought I'd just post what SMP code
I have.
Feel free to just merge the first patch if you think SMP
can wait.
Merged 2 and 3, thanks!
Maxime
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,
Maxime
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in the pinctrl node too?
If this patch is resent soon enough, I'll merge it and send it through
a late pull request together with the A23 SMP and A31 cpufreq patches.
Thanks!
Maxime
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On Sat, Mar 21, 2015 at 02:23:01PM +0100, Hans de Goede wrote:
Remove the unused usb1_vbus_pin_csq908 node (vbus is always on on the cs908),
and sort the remaining nodes alphabetically.
Signed-off-by: Hans de Goede hdego...@redhat.com
Applied, thanks!
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used to set them in SoCs that are not supported by U-boot yet, and
where the bootloader won't come and patch the DT (A31, A23, A80).
Maxime
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!
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care to not have multiple slave devices use
the same address. It is recommended to follow whatever conventions
the hardware vendor uses.
While very complete, the three last paragraphs should rather be, or at
least duplicated, in the file itself.
Maxime
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-supply = reg_usb2_vbus;
+ status = okay;
+};
--
2.0.5
It looks fine otherwise. Thanks!
Maxime
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it as
unknown on the wiki page,
would 'odm' be considered valid?
Not really. Another mk808c device might very well be made by some
other odm.
Don't your device has any brand on the case or the PCB?
Maxime
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http
On Wed, Mar 04, 2015 at 11:26:15PM +0300, Aleksei Mamlin wrote:
On Wed, 4 Mar 2015 21:18:19 +0100
Maxime Ripard maxime.rip...@free-electrons.com wrote:
On Wed, Mar 04, 2015 at 11:15:47AM +0300, Aleksei Mamlin wrote:
This patch add support for Wexler TAB7200 tablet.
The Wexler
is that this
protocol is quite far away from I2C. P2WI was already at the edge.
Maybe there is a better place for such custom stuff? I dunno yet.
That's unfortunate, especially since it looks closer to SPI than what
P2WI even was.
What would be your suggestion?
Thanks,
Maxime
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On Tue, Mar 03, 2015 at 02:20:31PM +0100, Hans de Goede wrote:
Hi,
On 03-03-15 09:22, Maxime Ripard wrote:
On Tue, Mar 03, 2015 at 08:55:36AM +0100, Hans de Goede wrote:
+/ {
+ model = Mele I7 Quad top set box;
+ compatible = mele,i7, allwinner,sun6i-a31;
+
+ chosen {
+ bootargs
more people on board.
If you have a good strategy for that, I'm all ears.
Maxime
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the SRAM controller patches are in next we can also merge
the musb: Add support for the Allwinner sunxi musb commit and the dts
changes.
All the DT bits look fine to me. I'll wait for Felipe and Kishon
comments before merging those.
Thanks!
Maxime
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the fractional mode
or the integer mode?
Maxime
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Everything is in the A20 datasheet on github.
Maxime
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some consistency to the downstream users.
Maxime
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;
+ interrupts = 0 86 4;
Please use the GIC's define here.
Thanks,
Maxime
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usually have an example after too.
Thanks!
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with an AXP209 PMU.
For more details see: http://linux-sunxi.org/Jesurun_Q5
Signed-off-by: Hans de Goede hdego...@redhat.com
Queued for 4.2, thanks!
Maxime
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.
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;
+ return -EMSGSIZE;
Eventually, we should move to using DMA for these messages longer than
the FIFO.
I should post these patches.
Maxime
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: emac: Claim our SRAM
This reverts commit 418c7a0486eb530033c8b436d729015a1193a84b.
And this is another commit I have no idea where it comes from.
What is the actual issue that revert this commit fixed?
Thanks,
Maxime
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On Sun, Apr 26, 2015 at 05:33:36PM +0200, Michal Suchanek wrote:
On 26 April 2015 at 16:33, Maxime Ripard
maxime.rip...@free-electrons.com wrote:
On Sun, Apr 26, 2015 at 04:14:33PM +0200, Michal Suchanek wrote:
On 26 April 2015 at 14:51, Maxime Ripard
maxime.rip...@free-electrons.com wrote
On Sun, Apr 26, 2015 at 04:14:33PM +0200, Michal Suchanek wrote:
On 26 April 2015 at 14:51, Maxime Ripard
maxime.rip...@free-electrons.com wrote:
On Sun, Apr 26, 2015 at 02:38:18PM +0200, Michal Suchanek wrote:
On 26 April 2015 at 13:56, Martin Sperl ker...@martin.sperl.org wrote
-tree kernels this just
works, we should be able to match that ease of use
with devicetree.
We do agree on that. We repeatedly told that the DT was not a good
solution, overlays or not, and this is exactly one of the reasons.
Maxime
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On Sun, Apr 26, 2015 at 01:42:51PM +0200, Michal Suchanek wrote:
On 26 April 2015 at 10:42, Maxime Ripard
maxime.rip...@free-electrons.com wrote:
On Sat, Apr 25, 2015 at 09:21:07PM +0200, Michal Suchanek wrote:
Signed-off-by: Michal Suchanek hramr...@gmail.com
No commit log
On Sun, Apr 26, 2015 at 11:21:34AM +0200, Michal Suchanek wrote:
Hello,
On 26 April 2015 at 10:39, Maxime Ripard
maxime.rip...@free-electrons.com wrote:
Hi,
On Mon, Mar 23, 2015 at 03:00:31PM +0100, Michal Suchanek wrote:
Signed-off-by: Michal Suchanek hramr...@gmail.com
ohci0
/spidev32766.1
crw--- 1 root root 153, 2 Apr 28 15:52 /dev/spidev32766.2
crw--- 1 root root 153, 3 Apr 28 15:52 /dev/spidev32766.3
Shouldn't they be numbered from like spidev0.[0-3].
Is this an udev problem ? any clues ?
You're missing an SPI alias in the DT.
Maxime
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On Sun, Apr 26, 2015 at 05:12:24PM +0200, Michal Suchanek wrote:
What is the actual issue that revert this commit fixed?
Ethernet not working.
That's a symptom, not a disease.
If you want a cure for something, usually, a symptom doesn't give you
anything.
Maxime
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On Wed, Apr 29, 2015 at 10:59:29AM +0200, Michal Suchanek wrote:
On 26 April 2015 at 17:12, Michal Suchanek hramr...@gmail.com wrote:
On 26 April 2015 at 16:41, Maxime Ripard
maxime.rip...@free-electrons.com wrote:
On Sun, Apr 26, 2015 at 04:17:35PM +0200, Michal Suchanek wrote:
On 25
about.
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-val needs
to be shifted by sram-offset.
Maxime
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On Mon, Apr 27, 2015 at 08:51:12AM +0200, Michal Suchanek wrote:
On 26 April 2015 at 17:47, Maxime Ripard
maxime.rip...@free-electrons.com wrote:
On Sun, Apr 26, 2015 at 04:40:50PM +0200, Hans de Goede wrote:
Hi,
I've a feeling everyone in this thread is ignoring the
raspberry pi use
the compatible from spidev, and have that matching
compatible in that new driver.
Maxime
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in the wild.
Usually, you want to use --annotate for this, and having PATCH vX in
the subject, which can easily be done using -vX.
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is
configured to be used.
Signed-off-by: Marcus Cooper codekip...@gmail.com
Applied, thanks!
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spi2_pins_a. It feels a bit weird
to have a spi2_pins_b group without its a counterpart.
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;
serial1 = uart2;
serial2 = uart3;
+ spi0 = spi0;
+ spi1 = spi1;
+ spi2 = spi2;
That patch should be merged with the patch 3, and since there's only
spi2 in use on that board, it should be aliased to spi0.
Maxime
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On Mon, Apr 27, 2015 at 11:16:01AM +0100, Mark Brown wrote:
On Sun, Apr 26, 2015 at 02:51:13PM +0200, Maxime Ripard wrote:
On Sun, Apr 26, 2015 at 02:38:18PM +0200, Michal Suchanek wrote:
I don't know if it's been suggested before, certainly nobody did the
work to make it happen. I
is:
+ * Copyright (C) 2014 Chen-Yu Tsai w...@csie.org
+ * Copyright (C) 2014 Maxime Ripard maxime.rip...@free-electrons.com
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed as is without any
+ * warranty of any kind, whether express
-by: Maxime Ripard maxime.rip...@free-electrons.com
Thanks!
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/sunxi/README with these infos
(and ideally, updating it with the new SoCs we've heard about) ?
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On Wed, May 06, 2015 at 12:23:49PM +0200, Jens Kuske wrote:
On 06/05/15 12:04, Maxime Ripard wrote:
Hi,
On Wed, May 06, 2015 at 11:31:28AM +0200, Jens Kuske wrote:
The Allwinner H3 is a quad-core Cortex-A7-based SoC. It is very similar
to other sun8i family SoCs like the A23
again, to
stay compatible with how it was called in Manual and earlier sunxi SoCs.
It seems reasonable :)
Thanks,
Maxime
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you tested the architected timers?
Thanks,
Maxime
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more or less similar..
interrupt-extended is a way to group interrupt-parent and interrupts
together. These two syntaxes are strictly equivalent.
Maxime
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that we know that we always have the needed regulators enabled,
disregarding which USB port is used?
Thanks,
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Hi Vinod,
On Fri, May 08, 2015 at 09:14:26AM +0530, Vinod Koul wrote:
On Wed, May 06, 2015 at 12:13:42PM +0200, Maxime Ripard wrote:
On Wed, May 06, 2015 at 11:31:31AM +0200, Jens Kuske wrote:
The H3 SoC has the same dma engine as the A31 (sun6i), with a
reduced amount of endpoints
Signed-off-by: Hans de Goede hdego...@redhat.com
Signed-off-by: Maxime Ripard maxime.rip...@free-electrons.com
---
Changes from v5:
* Rebased on 4.1-rc1
Changes from v4:
* Fix for interrupt triggering after freeing a dma-channel, this fixed
the problems with jack
* Adjust to recent kernel dma
);
+ dev_dbg(dev, Releasing sram %s.\n, sram-name );
SRAM is an acronym, it should be written uppercase.
Maxime
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,
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in separate DTSI, and then, once we have a
clear view of what needs what, we will create a common DTSI.
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= GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH;
+ clocks = ahb1_gates 6;
+ resets = ahb1_rst 6;
+ #dma-cells = 1;
+ };
With what device did you test DMA?
Maxime
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On Sun, May 10, 2015 at 12:16:19PM +0530, Vishnu Patekar wrote:
A33 PIO has 7 ports which starts from PB and has two interrupt ports.
Signed-off-by: Vishnu Patekar vishnupatekar0...@gmail.com
Acked-by: Maxime Ripard maxime.rip...@free-electrons.com
Thanks!
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-ups and devices require PMIC regulator */
+ status = failed;
+};
Is this still true, or is it just a copy/paste mistake?
Thanks,
Maxime
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or not that will be compiled,
but whether you're registering the clocks and which clocks you
protect.
Signed-off-by: VishnuPatekar vishnupatekar0...@gmail.com
Isn't it supposed to have a space in the middle of your name, just
like you have in your mail address?
Thanks,
Maxime
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. We're discussing with Chen-Yu about refactoring this anyway, so
it will probably go away in a near future.
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of devices to declare as childs of
ahb2.
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/linux-arm-kernel/2014-June/265064.html
H, I think I somehow overlooked the fact that the timer was there,
even though Chen-Yu said it. My bad :/
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as modules.
Maxime
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?
Or maybe just the one that's used by both USB hosts?
I was more thinking of giving to the phy an additional regulator, so
that it would enable both the regulators needed to power up all ports.
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.
It looks good otherwise.
Thanks!
Maxime
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On Mon, May 18, 2015 at 11:32:31AM +0200, Jens Kuske wrote:
Hi,
On 05/17/15 16:19, Maxime Ripard wrote:
On Fri, May 15, 2015 at 06:38:54PM +0200, Jens Kuske wrote:
Add a remove function and export the init and remove function
to allow us to build the SoC specific drivers as modules
On Mon, May 18, 2015 at 11:11:34AM +0200, Jens Kuske wrote:
Hi,
On 05/17/15 14:50, Maxime Ripard wrote:
Hi Jens,
On Fri, May 15, 2015 at 06:38:52PM +0200, Jens Kuske wrote:
Some newer sunxi SoCs (A83T, H3) don't have individual registers for
AHB1, APB1 and APB2 gates anymore
On Mon, Apr 27, 2015 at 07:07:28PM +0100, Mark Brown wrote:
On Mon, Apr 27, 2015 at 07:30:36PM +0200, Maxime Ripard wrote:
On Mon, Apr 27, 2015 at 11:16:01AM +0100, Mark Brown wrote:
lkml.org is being terrible as usual so I can't see half the thread (or
at least got fed up trying to get
Hi,
On Sun, May 10, 2015 at 12:54:50PM +0200, Jens Kuske wrote:
On 09/05/15 13:27, Maxime Ripard wrote:
On Wed, May 06, 2015 at 11:31:29AM +0200, Jens Kuske wrote:
The H3 clock control unit is similar to the those of other sun8i family
members like the A23.
The AHB1 gates got split up
to just work.
Maxime
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Hi Nicolas,
On Mon, May 18, 2015 at 01:19:18AM -0400, Nicolas Pitre wrote:
On Sun, 17 May 2015, Maxime Ripard wrote:
Hi Ian,
On Sat, May 16, 2015 at 11:08:46AM +0100, Ian Campbell wrote:
On Thu, 2015-05-14 at 14:10 +0800, Chen-Yu Tsai wrote:
This is my attempt to support SMP
On Thu, May 14, 2015 at 01:14:25PM +0800, Chen-Yu Tsai wrote:
On Tue, May 12, 2015 at 10:44 PM, Maxime Ripard
maxime.rip...@free-electrons.com wrote:
Hi,
On Sun, May 10, 2015 at 12:54:50PM +0200, Jens Kuske wrote:
On 09/05/15 13:27, Maxime Ripard wrote:
On Wed, May 06, 2015 at 11:31
and the interrupt mapping here.
Maxime
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factor clock, pll6 x2 */
+ { .fixed = 4 }, /* divided output, pll6 /2 */
+ }
+};
This is exactly the same clock as A31's PLL6, it shouldn't be declared
as a different one.
Maxime
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to do so. But if no one's
doing it, then we still have to have a way to bringup the secondary
CPUs.
Maxime
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On Fri, May 15, 2015 at 06:38:55PM +0200, Jens Kuske wrote:
The Allwinner H3 is a quad-core Cortex-A7-based SoC. It is very similar
to other sun8i family SoCs like the A23.
Signed-off-by: Jens Kuske jensku...@gmail.com
Applied, thanks!
Maxime
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Maxime Ripard, Free Electrons
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select PINCTRL_SUNXI_COMMON
+config PINCTRL_SUN8I_H3
+ tristate Allwinner H3 pinctrl driver
+ default MACH_SUN8I
+ select PINCTRL_SUNXI_COMMON
PINCTRL_SUNXI_COMMON should probably be turned into a tristate as well
Maxime
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Maxime Ripard, Free Electrons
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= 0x08001400 0x200;
+ };
+
The unit address doesn't match the content of the reg property.
Maxime
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have been sent to the reset framework maintainer.
Looks good otherwise.
Maxime
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are clocked at a lower frequency than the
A7...
Maxime
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To unsubscribe from this group and stop
about the device-tree side then.
If you have some suggestions for future DT names, I'm definitely open
to it though.
Maxime
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On Tue, Apr 14, 2015 at 04:29:08PM +0200, Paul Kocialkowski wrote:
Le mardi 14 avril 2015 à 16:22 +0200, Maxime Ripard a écrit :
On Tue, Apr 14, 2015 at 04:14:24PM +0200, Paul Kocialkowski wrote:
I understand the point though, that it can be
seen as an ABI (don't break the ABI
by default in other places (such as wiki page names),
unless there is ambiguity (in which case it's included).
I really don't know about that one, but I'd feel like having a DT
called sun4i-a10-olimex-a10-olinuxino.dtb would be kind of bad as
well.
Maxime
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On Wed, Apr 15, 2015 at 09:17:13PM +0200, Paul Kocialkowski wrote:
Le mercredi 15 avril 2015 à 10:29 +0200, Maxime Ripard a écrit :
On Tue, Apr 14, 2015 at 07:15:24PM +0200, Paul Kocialkowski wrote:
Le mardi 14 avril 2015 à 16:47 +0200, Maxime Ripard a écrit :
On Tue, Apr 14, 2015 at 04
clock that register a factors clock and set that
integer bit to one.
If they are the only users, there's no need to make it generic.
Maxime
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, so I suggest to
adapt to it.
Good thing the clk-factors stuff can handle such case then.
Maxime
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currently offline, so no, I won't go and search around on the
internet what the hell you're talking about.
Maxime
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