[linux-sunxi] Re: [PATCH 33/54] dt-bindings: thermal: Make trips node optional

[Daniel Lezcano]

On 21/07/2021 16:04, Maxime Ripard wrote:
> Even though the previous binding made it a required child node, the
> implementation in Linux never made it mandatory and just ignored thermal
> zones without trip points.
> 
> This was even effectively encouraged, since the thermal core wouldn't
> allow a thermal sensor to probe without a thermal zone.
> 
> In the case where you had a thermal device that had multiple sensors but
> with enough knowledge to provide trip points for only a few of them,
> this meant that the only way to make that driver probe was to provide a
> thermal zone without the trips node required by the binding.
> 
> This obviously led to a fair number of device trees doing exactly that,
> making the initial binding requirement ineffective.
> 
> Let's make it clear by dropping that requirement.
> 
> Cc: Amit Kucheria 
> Cc: Daniel Lezcano 
> Cc: linux...@vger.kernel.org
> Cc: Zhang Rui 
> Signed-off-by: Maxime Ripard 

Applied, thanks!

  -- D.


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[linux-sunxi] Re: [PATCH v2] ARM: dts: sun8i-a83t: Add thermal trip points/cooling maps

[Daniel Lezcano]

On 24/02/2020 18:39, Ondřej Jirman wrote:
> On Mon, Feb 24, 2020 at 06:23:28PM +0100, megous hlavni wrote:
>> Hi, 
>>
>> On Mon, Feb 24, 2020 at 06:06:20PM +0100, Daniel Lezcano wrote:
>>> On 24/02/2020 17:54, Ondrej Jirman wrote:
>>>> This enables passive cooling by down-regulating CPU voltage
>>>>clocks = < CLK_C1CPUX>;
>>>> @@ -1188,12 +1188,60 @@ cpu0_thermal: cpu0-thermal {
>>>>polling-delay-passive = <0>;
>>>>polling-delay = <0>;
>>>>thermal-sensors = < 0>;
>>>> +
>>>> +  trips {
>>>> +  ': cpu-hot {
>>>> +  temperature = <8>;
>>>> +  hysteresis = <2000>;
>>>> +  type = "passive";
>>>> +  };
>>>> +
>>>> +  cpu0_very_hot: cpu-very-hot {
>>>> +  temperature = <10>;
>>>> +  hysteresis = <0>;
>>>> +  type = "critical";
>>>> +  };
>>>> +  };
>>>> +
>>>> +  cooling-maps {
>>>> +  cpu-hot-limit {
>>>> +  trip = <_hot>;
>>>> +  cooling-device = < 
>>>> THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
>>>> +   < 
>>>> THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
>>>> +   < 
>>>> THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
>>>> +   < 
>>>> THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
>>>> +  };
>>>> +  };
>>>>};
>>>>  
>>>>cpu1_thermal: cpu1-thermal {
>>>>polling-delay-passive = <0>;
>>>
>>> No polling to mitigate?
>>
>> Polling to mitigate what?
>>
>> The driver is using interrupts whenever new reading is available, and
>> notifies tz of the change. I don't have a reason to believe any new
>> values are available from thermal sensor outside of the interrupt
>> period.
> 
> To be more clear, new temperatures are available from the thermal sensor 
> driver
> at the rate of 4 per second, which should be enough to do quick adjustments to
> the thermal zone/cooling device even for quick temperature rises.
> 
> https://elixir.bootlin.com/linux/v5.6-rc3/source/drivers/thermal/sun8i_thermal.c#L442
> 
> There's no slow/fast period depending on whether the cooling is active.
> It's always fast and no polling of the thermal sensor is needed.

Thanks for the clarification. All sensors have their specificity.

Does the sensor allow to create a threshold temperature where an
interrupt fires when crossing the boundary? That would be interesting
for performance and energy saving to disable the interrupts until
'cpu0_hot' is reached, no?

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[linux-sunxi] Re: [PATCH v2] ARM: dts: sun8i-a83t: Add thermal trip points/cooling maps

[Daniel Lezcano]

On 24/02/2020 17:54, Ondrej Jirman wrote:
> This enables passive cooling by down-regulating CPU voltage
> and frequency.
> 
> For the trip points, I used values from the BSP code directly.
> 
> The critical trip point value is 30°C above the maximum recommended
> ambient temperature (70°C) for the SoC from the datasheet, so there's
> some headroom even at such a high ambient temperature.
> 
> Signed-off-by: Ondrej Jirman 
> ---
>  arch/arm/boot/dts/sun8i-a83t.dtsi | 60 +++
>  1 file changed, 54 insertions(+), 6 deletions(-)
> 
> v2:
> - added more detail to the commit description
> 
> diff --git a/arch/arm/boot/dts/sun8i-a83t.dtsi 
> b/arch/arm/boot/dts/sun8i-a83t.dtsi
> index 74ac7ee9383cf..53c2b6a836f27 100644
> --- a/arch/arm/boot/dts/sun8i-a83t.dtsi
> +++ b/arch/arm/boot/dts/sun8i-a83t.dtsi
> @@ -72,7 +72,7 @@ cpu0: cpu@0 {
>   #cooling-cells = <2>;
>   };
>  
> - cpu@1 {
> + cpu1: cpu@1 {
>   compatible = "arm,cortex-a7";
>   device_type = "cpu";
>   clocks = < CLK_C0CPUX>;
> @@ -83,7 +83,7 @@ cpu@1 {
>   #cooling-cells = <2>;
>   };
>  
> - cpu@2 {
> + cpu2: cpu@2 {
>   compatible = "arm,cortex-a7";
>   device_type = "cpu";
>   clocks = < CLK_C0CPUX>;
> @@ -94,7 +94,7 @@ cpu@2 {
>   #cooling-cells = <2>;
>   };
>  
> - cpu@3 {
> + cpu3: cpu@3 {
>   compatible = "arm,cortex-a7";
>   device_type = "cpu";
>   clocks = < CLK_C0CPUX>;
> @@ -116,7 +116,7 @@ cpu100: cpu@100 {
>   #cooling-cells = <2>;
>   };
>  
> - cpu@101 {
> + cpu101: cpu@101 {
>   compatible = "arm,cortex-a7";
>   device_type = "cpu";
>   clocks = < CLK_C1CPUX>;
> @@ -127,7 +127,7 @@ cpu@101 {
>   #cooling-cells = <2>;
>   };
>  
> - cpu@102 {
> + cpu102: cpu@102 {
>   compatible = "arm,cortex-a7";
>   device_type = "cpu";
>   clocks = < CLK_C1CPUX>;
> @@ -138,7 +138,7 @@ cpu@102 {
>   #cooling-cells = <2>;
>   };
>  
> - cpu@103 {
> + cpu103: cpu@103 {
>   compatible = "arm,cortex-a7";
>   device_type = "cpu";
>   clocks = < CLK_C1CPUX>;
> @@ -1188,12 +1188,60 @@ cpu0_thermal: cpu0-thermal {
>   polling-delay-passive = <0>;
>   polling-delay = <0>;
>   thermal-sensors = < 0>;
> +
> + trips {
> + cpu0_hot: cpu-hot {
> + temperature = <8>;
> + hysteresis = <2000>;
> + type = "passive";
> + };
> +
> + cpu0_very_hot: cpu-very-hot {
> + temperature = <10>;
> + hysteresis = <0>;
> + type = "critical";
> + };
> + };
> +
> + cooling-maps {
> + cpu-hot-limit {
> + trip = <_hot>;
> + cooling-device = < 
> THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
> +  < 
> THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
> +  < 
> THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
> +  < 
> THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
> + };
> + };
>   };
>  
>   cpu1_thermal: cpu1-thermal {
>   polling-delay-passive = <0>;

No polling to mitigate?

>   polling-delay = <0>;
>   thermal-sensors = < 1>;
> +
> + trips {
> + cpu1_hot: cpu-hot {
> + temperature = <8>;
> + hysteresis = <2000>;
> + type = "passive";

I'm curious, can you really reach this temperature with a cortex-a7
running at 1.2GHz max?

> + };
> +
> + cpu1_very_hot: cpu-very-hot {
> + temperature = <10>;
> + hysteresis = <0>;
> + type = "critical";
> + 

[linux-sunxi] Re: [PATCH 0/7] Timer & SPI support for Allwinner suniv F1C100s

[Daniel Lezcano]

On 18/03/2019 08:18, Icenowy Zheng wrote:
> 在 2019-03-17日的 21:52 +0100，Daniel Lezcano写道：
>> On 17/03/2019 18:39, Icenowy Zheng wrote:
>>> 在 2019-02-11一的 12:21 +0300，Mesih Kilinc写道：
>>>> This is followup series for F1C100s initial support patchset. 
>>>> All patches merged except patch 1 ~ 2 which is related to timer.
>>>> I am resending those since they are already have Acked tags.
>>>
>>> Ping.
>>>
>>> Could you please merge these timer-related patches?
>>
>> Hi,
>>
>> I acked the timer-related patches. If you resend the patches with my
>> acked-by I will consider them to go through the allwinner tree.
>>
>> Do you want me to take 1 and 2 through my tree?
> 
> Please. They also have the ACK from Allwinner/sunXi maintainer.

Applied for 5.2. Thanks

By the way, I did not find any trace of the email in my mailer, was I
To'ed or CC'ed for those patches ?


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[linux-sunxi] Re: [PATCH 0/7] Timer & SPI support for Allwinner suniv F1C100s

[Daniel Lezcano]

On 17/03/2019 18:39, Icenowy Zheng wrote:
> 在 2019-02-11一的 12:21 +0300，Mesih Kilinc写道：
>> This is followup series for F1C100s initial support patchset. 
>> All patches merged except patch 1 ~ 2 which is related to timer.
>> I am resending those since they are already have Acked tags.
> 
> Ping.
> 
> Could you please merge these timer-related patches?

Hi,

I acked the timer-related patches. If you resend the patches with my
acked-by I will consider them to go through the allwinner tree.

Do you want me to take 1 and 2 through my tree?



>> Our dt-bindings for F1C100s are merged, we can now use them at our 
>> device tree source - patch 3.
>>
>> Also this series add spi support and enables spi flash at Lichee-pi
>> Nano
>> in patch 4 ~ 7. This patches are based on Icenowy's work.
>>
>> Thanks!
>>
>> Mesih Kilinc (7):
>>   dt-bindings: timer: Add Allwinner suniv timer
>>   clocksource: sun4i: add a compatible for suniv
>>   ARM: dts: suniv: Add dt-binding headers for F1C100s
>>   dt-bindings: spi: Add Support for Allwinner F1C100s
>>   ARM: dts: suniv: Add SPI device-tree nodes
>>   ARM: dts: suniv: Add pinmux for SPI0 and SPI1 of F1C100s
>>   ARM: dts: f1c100s: Activate SPI flash on Lichee Pi Nano
>>
>>  .../devicetree/bindings/spi/spi-sun6i.txt  |  5 +-
>>  .../bindings/timer/allwinner,sun4i-timer.txt   |  4 +-
>>  arch/arm/boot/dts/suniv-f1c100s-licheepi-nano.dts  | 13 ++
>>  arch/arm/boot/dts/suniv-f1c100s.dtsi   | 53
>> +++---
>>  drivers/clocksource/timer-sun4i.c  |  5 +-
>>  5 files changed, 70 insertions(+), 10 deletions(-)
>>
> 


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[linux-sunxi] Re: [PATCH v3 0/2] Allwinner A64 timer workaround

[Daniel Lezcano]

On 13/01/2019 03:17, Samuel Holland wrote:
> This is the third version of a patch series to fix system clock jumps
> and other timer instability on the Allwinner A64 SoC. It has now been
> tested for a week, and I've received no reports of date jumps with this
> version. So this is, as far as I can tell, a complete workaround.
> 
> See the commit messages for a detailed description of the issue, but the
> summary is that, when a high counter bit rolls over, indeterminance in
> the low bits causes CNTPCT/CNTVCT and their respective TVAL registers to
> jump forward or backward. Backward jumps (or the next read after forward
> jumps) are sometimes seen by the kernel and interpreted as the timer
> wrapping around after 2^56 cycles. This causes the system clock to jump
> forward approximately 91 years.
> 
> changes since v2;
> - Reduced workaround threshold from 11 to 10 bits based on reports from
>   other hardare and the U-Boot version of this workaround
> - Added TVAL handling based on Marc's suggestion
> - Added erratum documentation and renamed symbols to match
> - Added Maxime's Acked-by
> 
> changes since v1:
> - Add an iteration limit like most other arch timer workarounds
> - Added Andre's Tested-by
> 
> Samuel Holland (2):
>   arm64: arch_timer: Workaround for Allwinner A64 timer instability
>   arm64: dts: allwinner: a64: Enable A64 timer workaround
> 
>  Documentation/arm64/silicon-errata.txt|  2 +
>  arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi |  1 +
>  drivers/clocksource/Kconfig   | 10 
>  drivers/clocksource/arm_arch_timer.c  | 55 +++
>  4 files changed, 68 insertions(+)
> 

Applied. Took the opportunity to add the stable@ tag.

Thanks

  -- Daniel


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[linux-sunxi] Re: [RFC PATCH v3 07/17] clocksource: sun4i: add a compatible for suniv

[Daniel Lezcano]

On 21/11/2018 19:30, Mesih Kilinc wrote:
> The suniv (new F-series) chip has a timer with less functionality than
> the A10 timer, e.g. it has only 3 channels.
> 
> Add a new compatible for it. As we didn't use the extra channels on A10
> either now, the code needn't to be changed.
> 
> The suniv chip is based on ARM926EJ-S CPU, thus it has no architecture timer.
> 
> Register sun4i_timer as sched_clock on it.
> 
> Signed-off-by: Mesih Kilinc 

Acked-by: Daniel Lezcano 

> ---
>  drivers/clocksource/sun4i_timer.c | 5 -
>  1 file changed, 4 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/clocksource/sun4i_timer.c 
> b/drivers/clocksource/sun4i_timer.c
> index 6e0180a..65f38f6 100644
> --- a/drivers/clocksource/sun4i_timer.c
> +++ b/drivers/clocksource/sun4i_timer.c
> @@ -186,7 +186,8 @@ static int __init sun4i_timer_init(struct device_node 
> *node)
>*/
>   if (of_machine_is_compatible("allwinner,sun4i-a10") ||
>   of_machine_is_compatible("allwinner,sun5i-a13") ||
> - of_machine_is_compatible("allwinner,sun5i-a10s"))
> + of_machine_is_compatible("allwinner,sun5i-a10s") ||
> + of_machine_is_compatible("allwinner,suniv-f1c100s"))
>   sched_clock_register(sun4i_timer_sched_read, 32,
>timer_of_rate());
>  
> @@ -218,3 +219,5 @@ static int __init sun4i_timer_init(struct device_node 
> *node)
>  }
>  TIMER_OF_DECLARE(sun4i, "allwinner,sun4i-a10-timer",
>  sun4i_timer_init);
> +TIMER_OF_DECLARE(suniv, "allwinner,suniv-f1c100s-timer",
> +sun4i_timer_init);
> 


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