[linux-sunxi] [PATCH 2/3] net: sun8i-emac: Always clear syscon EPHY register

[Andre Przywara]

At the moment we only consider the EPHY register for those SoCs were
we actually have an internal PHY to configure. However even other SoCs
have this register, an expect a bit to be cleared for proper operation
with an external PHY.

Rework sun8i_emac_set_syscon_ephy() to be called regardless of the EMAC
model, and clear the H3_EPHY_SELECT bit if no internal PHY is used.

This helps with the upcoming H616 support, were we need to consider two
EMACs.

Signed-off-by: Andre Przywara <andre.przyw...@arm.com>
---
 drivers/net/sun8i_emac.c | 31 +++++++++++++------------------
 1 file changed, 13 insertions(+), 18 deletions(-)

diff --git a/drivers/net/sun8i_emac.c b/drivers/net/sun8i_emac.c
index 5db33f5c135..a1a30b34579 100644
--- a/drivers/net/sun8i_emac.c
+++ b/drivers/net/sun8i_emac.c
@@ -297,30 +297,29 @@ static void sun8i_adjust_link(struct emac_eth_dev *priv,
        writel(v, priv->mac_reg + EMAC_CTL0);
 }
 
-static int sun8i_emac_set_syscon_ephy(struct emac_eth_dev *priv, u32 *reg)
+static u32 sun8i_emac_set_syscon_ephy(struct emac_eth_dev *priv, u32 reg)
 {
        if (priv->use_internal_phy) {
                /* H3 based SoC's that has an Internal 100MBit PHY
                 * needs to be configured and powered up before use
                */
-               *reg &= ~H3_EPHY_DEFAULT_MASK;
-               *reg |=  H3_EPHY_DEFAULT_VALUE;
-               *reg |= priv->phyaddr << H3_EPHY_ADDR_SHIFT;
-               *reg &= ~H3_EPHY_SHUTDOWN;
-               *reg |= H3_EPHY_SELECT;
-       } else
-               /* This is to select External Gigabit PHY on
-                * the boards with H3 SoC.
-               */
-               *reg &= ~H3_EPHY_SELECT;
+               reg &= ~H3_EPHY_DEFAULT_MASK;
+               reg |=  H3_EPHY_DEFAULT_VALUE;
+               reg |= priv->phyaddr << H3_EPHY_ADDR_SHIFT;
+               reg &= ~H3_EPHY_SHUTDOWN;
+               return reg | H3_EPHY_SELECT;
+       }
 
-       return 0;
+       /* This is to select External Gigabit PHY on those boards with
+        * an internal PHY. Does not hurt on other SoCs. Linux does
+        * it as well.
+        */
+       return reg & ~H3_EPHY_SELECT;
 }
 
 static int sun8i_emac_set_syscon(struct sun8i_eth_pdata *pdata,
                                 struct emac_eth_dev *priv)
 {
-       int ret;
        u32 reg;
 
        if (priv->variant == R40_GMAC) {
@@ -336,11 +335,7 @@ static int sun8i_emac_set_syscon(struct sun8i_eth_pdata 
*pdata,
 
        reg = readl(priv->sysctl_reg + 0x30);
 
-       if (priv->variant == H3_EMAC || priv->variant == H6_EMAC) {
-               ret = sun8i_emac_set_syscon_ephy(priv, &reg);
-               if (ret)
-                       return ret;
-       }
+       reg = sun8i_emac_set_syscon_ephy(priv, reg);
 
        reg &= ~(SC_ETCS_MASK | SC_EPIT);
        if (priv->variant == H3_EMAC ||
-- 
2.17.5

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