Re: [linux-sunxi] [PATCH v4 3/8] phy: sun4i-usb: add PHYCTL offset for H3 SoC

2017-03-24 Thread Icenowy Zheng
24.03.2017, 14:56, "Chen-Yu Tsai" : > On Fri, Mar 24, 2017 at 2:27 PM, Icenowy Zheng wrote: >>  24.03.2017, 11:05, "Chen-Yu Tsai" : >>>  On Mon, Mar 20, 2017 at 12:19 AM, Icenowy Zheng wrote:   The config structure of H3 in

Re: [linux-sunxi] [PATCH v4 3/8] phy: sun4i-usb: add PHYCTL offset for H3 SoC

2017-03-24 Thread Chen-Yu Tsai
On Fri, Mar 24, 2017 at 2:27 PM, Icenowy Zheng wrote: > > > 24.03.2017, 11:05, "Chen-Yu Tsai" : >> On Mon, Mar 20, 2017 at 12:19 AM, Icenowy Zheng wrote: >>> The config structure of H3 in phy-sun4i-usb driver have the PHYCTL >>> register

Re: [linux-sunxi] [PATCH v4 3/8] phy: sun4i-usb: add PHYCTL offset for H3 SoC

2017-03-24 Thread Icenowy Zheng
24.03.2017, 11:05, "Chen-Yu Tsai" : > On Mon, Mar 20, 2017 at 12:19 AM, Icenowy Zheng wrote: >>  The config structure of H3 in phy-sun4i-usb driver have the PHYCTL >>  register offset missing. >> >>  Add it. Because it's a SoC after A33, its PHYCTL offset should

Re: [linux-sunxi] [PATCH v4 3/8] phy: sun4i-usb: add PHYCTL offset for H3 SoC

2017-03-23 Thread Chen-Yu Tsai
On Mon, Mar 20, 2017 at 12:19 AM, Icenowy Zheng wrote: > The config structure of H3 in phy-sun4i-usb driver have the PHYCTL > register offset missing. > > Add it. Because it's a SoC after A33, its PHYCTL offset should be 0x10. You are implying that all SoCs after A33 have

[linux-sunxi] [PATCH v4 3/8] phy: sun4i-usb: add PHYCTL offset for H3 SoC

2017-03-19 Thread Icenowy Zheng
The config structure of H3 in phy-sun4i-usb driver have the PHYCTL register offset missing. Add it. Because it's a SoC after A33, its PHYCTL offset should be 0x10. Signed-off-by: Icenowy Zheng --- New patch in v4. drivers/phy/phy-sun4i-usb.c | 1 + 1 file changed, 1