On 10/01/2021 18:43, Jernej Škrabec wrote:
> Dne petek, 08. januar 2021 ob 03:01:42 CET je André Przywara napisal(a):
>> On 03/12/2020 17:46, Jernej Skrabec wrote:
>>> It turns out that in rare cases, current analytical approach to detect
>>> correct DRAM bus width and rank on H6 doesn't work. On
On 03/12/2020 17:46, Jernej Skrabec wrote:
> It turns out that in rare cases, current analytical approach to detect
> correct DRAM bus width and rank on H6 doesn't work. On some TV boxes
> with DDR3, incorrect DRAM configuration triggers write leveling error
> which immediately stops
