On 03/01/2021 09:26, Jernej Skrabec wrote:
> This commit introduces DM H616 clock driver.
>
> Signed-off-by: Jernej Skrabec <jernej.skra...@siol.net>
Compared against the manual.
Reviewed-by: Andre Przywara <andre.przyw...@arm.com>
Cheers,
Andre
> ---
> drivers/clk/sunxi/Kconfig | 7 ++
> drivers/clk/sunxi/Makefile | 1 +
> drivers/clk/sunxi/clk_h616.c | 120 +++++++++++++++++++++++++++++++++++
> 3 files changed, 128 insertions(+)
> create mode 100644 drivers/clk/sunxi/clk_h616.c
>
> diff --git a/drivers/clk/sunxi/Kconfig b/drivers/clk/sunxi/Kconfig
> index 5ff101b99305..bf084fa7a84a 100644
> --- a/drivers/clk/sunxi/Kconfig
> +++ b/drivers/clk/sunxi/Kconfig
> @@ -79,6 +79,13 @@ config CLK_SUN50I_H6
> This enables common clock driver support for platforms based
> on Allwinner H6 SoC.
>
> +config CLK_SUN50I_H616
> + bool "Clock driver for Allwinner H616"
> + default MACH_SUN50I_H616
> + help
> + This enables common clock driver support for platforms based
> + on Allwinner H616 SoC.
> +
> config CLK_SUN50I_A64
> bool "Clock driver for Allwinner A64"
> default MACH_SUN50I
> diff --git a/drivers/clk/sunxi/Makefile b/drivers/clk/sunxi/Makefile
> index 36fb2aeb56c5..0dfc0593fb1c 100644
> --- a/drivers/clk/sunxi/Makefile
> +++ b/drivers/clk/sunxi/Makefile
> @@ -16,4 +16,5 @@ obj-$(CONFIG_CLK_SUN8I_V3S) += clk_v3s.o
> obj-$(CONFIG_CLK_SUN9I_A80) += clk_a80.o
> obj-$(CONFIG_CLK_SUN8I_H3) += clk_h3.o
> obj-$(CONFIG_CLK_SUN50I_H6) += clk_h6.o
> +obj-$(CONFIG_CLK_SUN50I_H616) += clk_h616.o
> obj-$(CONFIG_CLK_SUN50I_A64) += clk_a64.o
> diff --git a/drivers/clk/sunxi/clk_h616.c b/drivers/clk/sunxi/clk_h616.c
> new file mode 100644
> index 000000000000..e2e3a5c78c95
> --- /dev/null
> +++ b/drivers/clk/sunxi/clk_h616.c
> @@ -0,0 +1,120 @@
> +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
> +/*
> + * Copyright (C) 2021 Jernej Skrabec <jernej.skra...@siol.net>
> + */
> +
> +#include <common.h>
> +#include <clk-uclass.h>
> +#include <dm.h>
> +#include <errno.h>
> +#include <asm/arch/ccu.h>
> +#include <dt-bindings/clock/sun50i-h616-ccu.h>
> +#include <dt-bindings/reset/sun50i-h616-ccu.h>
> +#include <linux/bitops.h>
> +
> +static struct ccu_clk_gate h616_gates[] = {
> + [CLK_BUS_MMC0] = GATE(0x84c, BIT(0)),
> + [CLK_BUS_MMC1] = GATE(0x84c, BIT(1)),
> + [CLK_BUS_MMC2] = GATE(0x84c, BIT(2)),
> +
> + [CLK_BUS_UART0] = GATE(0x90c, BIT(0)),
> + [CLK_BUS_UART1] = GATE(0x90c, BIT(1)),
> + [CLK_BUS_UART2] = GATE(0x90c, BIT(2)),
> + [CLK_BUS_UART3] = GATE(0x90c, BIT(3)),
> + [CLK_BUS_UART4] = GATE(0x90c, BIT(4)),
> + [CLK_BUS_UART5] = GATE(0x90c, BIT(5)),
> +
> + [CLK_SPI0] = GATE(0x940, BIT(31)),
> + [CLK_SPI1] = GATE(0x944, BIT(31)),
> +
> + [CLK_BUS_SPI0] = GATE(0x96c, BIT(0)),
> + [CLK_BUS_SPI1] = GATE(0x96c, BIT(1)),
> +
> + [CLK_BUS_EMAC0] = GATE(0x97c, BIT(0)),
> + [CLK_BUS_EMAC1] = GATE(0x97c, BIT(1)),
> +
> + [CLK_USB_PHY0] = GATE(0xa70, BIT(29)),
> + [CLK_USB_OHCI0] = GATE(0xa70, BIT(31)),
> +
> + [CLK_USB_PHY1] = GATE(0xa74, BIT(29)),
> + [CLK_USB_OHCI1] = GATE(0xa74, BIT(31)),
> +
> + [CLK_USB_PHY2] = GATE(0xa78, BIT(29)),
> + [CLK_USB_OHCI2] = GATE(0xa78, BIT(31)),
> +
> + [CLK_USB_PHY3] = GATE(0xa7c, BIT(29)),
> + [CLK_USB_OHCI3] = GATE(0xa7c, BIT(31)),
> +
> + [CLK_BUS_OHCI0] = GATE(0xa8c, BIT(0)),
> + [CLK_BUS_OHCI1] = GATE(0xa8c, BIT(1)),
> + [CLK_BUS_OHCI2] = GATE(0xa8c, BIT(2)),
> + [CLK_BUS_OHCI3] = GATE(0xa8c, BIT(3)),
> + [CLK_BUS_EHCI0] = GATE(0xa8c, BIT(4)),
> + [CLK_BUS_EHCI1] = GATE(0xa8c, BIT(5)),
> + [CLK_BUS_EHCI2] = GATE(0xa8c, BIT(6)),
> + [CLK_BUS_EHCI3] = GATE(0xa8c, BIT(7)),
> + [CLK_BUS_OTG] = GATE(0xa8c, BIT(8)),
> +};
> +
> +static struct ccu_reset h616_resets[] = {
> + [RST_BUS_MMC0] = RESET(0x84c, BIT(16)),
> + [RST_BUS_MMC1] = RESET(0x84c, BIT(17)),
> + [RST_BUS_MMC2] = RESET(0x84c, BIT(18)),
> +
> + [RST_BUS_UART0] = RESET(0x90c, BIT(16)),
> + [RST_BUS_UART1] = RESET(0x90c, BIT(17)),
> + [RST_BUS_UART2] = RESET(0x90c, BIT(18)),
> + [RST_BUS_UART3] = RESET(0x90c, BIT(19)),
> + [RST_BUS_UART4] = RESET(0x90c, BIT(20)),
> + [RST_BUS_UART5] = RESET(0x90c, BIT(21)),
> +
> + [RST_BUS_SPI0] = RESET(0x96c, BIT(16)),
> + [RST_BUS_SPI1] = RESET(0x96c, BIT(17)),
> +
> + [RST_BUS_EMAC0] = RESET(0x97c, BIT(16)),
> + [RST_BUS_EMAC1] = RESET(0x97c, BIT(17)),
> +
> + [RST_USB_PHY0] = RESET(0xa70, BIT(30)),
> +
> + [RST_USB_PHY1] = RESET(0xa74, BIT(30)),
> +
> + [RST_USB_PHY2] = RESET(0xa78, BIT(30)),
> +
> + [RST_USB_PHY3] = RESET(0xa7c, BIT(30)),
> +
> + [RST_BUS_OHCI0] = RESET(0xa8c, BIT(16)),
> + [RST_BUS_OHCI1] = RESET(0xa8c, BIT(17)),
> + [RST_BUS_OHCI2] = RESET(0xa8c, BIT(18)),
> + [RST_BUS_OHCI3] = RESET(0xa8c, BIT(19)),
> + [RST_BUS_EHCI0] = RESET(0xa8c, BIT(20)),
> + [RST_BUS_EHCI1] = RESET(0xa8c, BIT(21)),
> + [RST_BUS_EHCI2] = RESET(0xa8c, BIT(22)),
> + [RST_BUS_EHCI3] = RESET(0xa8c, BIT(23)),
> + [RST_BUS_OTG] = RESET(0xa8c, BIT(24)),
> +};
> +
> +static const struct ccu_desc h616_ccu_desc = {
> + .gates = h616_gates,
> + .resets = h616_resets,
> +};
> +
> +static int h616_clk_bind(struct udevice *dev)
> +{
> + return sunxi_reset_bind(dev, ARRAY_SIZE(h616_resets));
> +}
> +
> +static const struct udevice_id h616_ccu_ids[] = {
> + { .compatible = "allwinner,sun50i-h616-ccu",
> + .data = (ulong)&h616_ccu_desc },
> + { }
> +};
> +
> +U_BOOT_DRIVER(clk_sun50i_h616) = {
> + .name = "sun50i_h616_ccu",
> + .id = UCLASS_CLK,
> + .of_match = h616_ccu_ids,
> + .priv_auto_alloc_size = sizeof(struct ccu_priv),
> + .ops = &sunxi_clk_ops,
> + .probe = sunxi_clk_probe,
> + .bind = h616_clk_bind,
> +};
>
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