On Sun, Mar 7, 2021 at 1:25 AM Jernej Skrabec <jernej.skra...@siol.net> wrote: > > Video driver currently manages clocks and resets by directly writing to > registers. This is already a bit messy because each SoC has some > specifics. It's much better to implement proper clock and reset driver > which takes information from device tree file. > > Note that this driver is not perfect yet. It still sets PLL and parent > by hand. Sunxi clock framework still doesn't know how to set parents or > rates. However, this is already big step in right direction. > > Cc: Lukasz Majewski <lu...@denx.de> > Signed-off-by: Jernej Skrabec <jernej.skra...@siol.net> > ---
Reviewed-by: Jagan Teki <ja...@amarulasolutions.com> -- You received this message because you are subscribed to the Google Groups "linux-sunxi" group. To unsubscribe from this group and stop receiving emails from it, send an email to linux-sunxi+unsubscr...@googlegroups.com. To view this discussion on the web, visit https://groups.google.com/d/msgid/linux-sunxi/CAMty3ZB1y_Sa-6hu3m1uvAe6oAXDNmnQ43xg8_DeARLFDderiQ%40mail.gmail.com.
