On 06/01/2021 17:02, Jernej Skrabec wrote:
> Updated H6 DT files are based on Linux 5.11-rc1 release.
>
> Signed-off-by: Jernej Skrabec <jernej.skra...@siol.net>
Reviewed-by: Andre Przywara <andre.przyw...@arm.com>
Two things to note:
- This relies on the U-Boot patch to sun8i-emac to recognise rgmii-id
and friends, otherwise Ethernet won't work. The patch should ideally be
merged before those ones.
- This decreases DT compatibilty with older kernels, which don't know
about the H6 RTC (introduced in Linux v5.4). The IOSC fixed clock got
replaced by <&rtc 2>, so this won't be available everywhere.
Cheers,
Andre
> ---
> arch/arm/dts/sun50i-h6-beelink-gs1.dts | 70 +++-
> arch/arm/dts/sun50i-h6-cpu-opp.dtsi | 117 ++++++
> arch/arm/dts/sun50i-h6-orangepi-lite2.dts | 71 +++-
> arch/arm/dts/sun50i-h6-orangepi-one-plus.dts | 41 +-
> arch/arm/dts/sun50i-h6-orangepi.dtsi | 72 +++-
> arch/arm/dts/sun50i-h6-pine-h64.dts | 102 +++--
> arch/arm/dts/sun50i-h6.dtsi | 394 +++++++++++++++++--
> 7 files changed, 794 insertions(+), 73 deletions(-)
> create mode 100644 arch/arm/dts/sun50i-h6-cpu-opp.dtsi
>
> diff --git a/arch/arm/dts/sun50i-h6-beelink-gs1.dts
> b/arch/arm/dts/sun50i-h6-beelink-gs1.dts
> index 0dc33c90dd60..7c9dbde645b5 100644
> --- a/arch/arm/dts/sun50i-h6-beelink-gs1.dts
> +++ b/arch/arm/dts/sun50i-h6-beelink-gs1.dts
> @@ -1,11 +1,10 @@
> -// SPDX-License-Identifier: (GPL-2.0+ or MIT)
> -/*
> - * Copyright (C) 2019 Clément Péron <peron.c...@gmail.com>
> - */
> +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
> +// Copyright (C) 2019 Clément Péron <peron.c...@gmail.com>
>
> /dts-v1/;
>
> #include "sun50i-h6.dtsi"
> +#include "sun50i-h6-cpu-opp.dtsi"
>
> #include <dt-bindings/gpio/gpio.h>
>
> @@ -25,6 +24,7 @@
> connector {
> compatible = "hdmi-connector";
> type = "a";
> + ddc-en-gpios = <&pio 7 2 GPIO_ACTIVE_HIGH>; /* PH2 */
>
> port {
> hdmi_con_in: endpoint {
> @@ -33,6 +33,13 @@
> };
> };
>
> + ext_osc32k: ext_osc32k_clk {
> + #clock-cells = <0>;
> + compatible = "fixed-clock";
> + clock-frequency = <32768>;
> + clock-output-names = "ext_osc32k";
> + };
> +
> leds {
> compatible = "gpio-leds";
>
> @@ -51,12 +58,38 @@
> regulator-max-microvolt = <5000000>;
> regulator-always-on;
> };
> +
> + sound-spdif {
> + compatible = "simple-audio-card";
> + simple-audio-card,name = "sun50i-h6-spdif";
> +
> + simple-audio-card,cpu {
> + sound-dai = <&spdif>;
> + };
> +
> + simple-audio-card,codec {
> + sound-dai = <&spdif_out>;
> + };
> + };
> +
> + spdif_out: spdif-out {
> + #sound-dai-cells = <0>;
> + compatible = "linux,spdif-dit";
> + };
> +};
> +
> +&cpu0 {
> + cpu-supply = <®_dcdca>;
> };
>
> &de {
> status = "okay";
> };
>
> +&dwc3 {
> + status = "okay";
> +};
> +
> &ehci0 {
> status = "okay";
> };
> @@ -64,12 +97,17 @@
> &emac {
> pinctrl-names = "default";
> pinctrl-0 = <&ext_rgmii_pins>;
> - phy-mode = "rgmii";
> + phy-mode = "rgmii-id";
> phy-handle = <&ext_rgmii_phy>;
> phy-supply = <®_aldo2>;
> status = "okay";
> };
>
> +&gpu {
> + mali-supply = <®_dcdcc>;
> + status = "okay";
> +};
> +
> &hdmi {
> status = "okay";
> };
> @@ -201,13 +239,16 @@
> reg_dcdca: dcdca {
> regulator-always-on;
> regulator-min-microvolt = <810000>;
> - regulator-max-microvolt = <1080000>;
> + regulator-max-microvolt = <1160000>;
> + regulator-ramp-delay = <2500>;
> regulator-name = "vdd-cpu";
> };
>
> reg_dcdcc: dcdcc {
> + regulator-enable-ramp-delay = <32000>;
> regulator-min-microvolt = <810000>;
> regulator-max-microvolt = <1080000>;
> + regulator-ramp-delay = <2500>;
> regulator-name = "vdd-gpu";
> };
>
> @@ -232,6 +273,11 @@
> };
> };
>
> +&r_ir {
> + linux,rc-map-name = "rc-beelink-gs1";
> + status = "okay";
> +};
> +
> &r_pio {
> /*
> * PL0 and PL1 are used for PMIC I2C
> @@ -243,6 +289,14 @@
> vcc-pm-supply = <®_aldo1>;
> };
>
> +&rtc {
> + clocks = <&ext_osc32k>;
> +};
> +
> +&spdif {
> + status = "okay";
> +};
> +
> &uart0 {
> pinctrl-names = "default";
> pinctrl-0 = <&uart0_ph_pins>;
> @@ -258,3 +312,7 @@
> usb0_vbus-supply = <®_vcc5v>;
> status = "okay";
> };
> +
> +&usb3phy {
> + status = "okay";
> +};
> diff --git a/arch/arm/dts/sun50i-h6-cpu-opp.dtsi
> b/arch/arm/dts/sun50i-h6-cpu-opp.dtsi
> new file mode 100644
> index 000000000000..1a5eddc5a40f
> --- /dev/null
> +++ b/arch/arm/dts/sun50i-h6-cpu-opp.dtsi
> @@ -0,0 +1,117 @@
> +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
> +// Copyright (C) 2020 Ondrej Jirman <meg...@megous.com>
> +// Copyright (C) 2020 Clément Péron <peron.c...@gmail.com>
> +
> +/ {
> + cpu_opp_table: cpu-opp-table {
> + compatible = "allwinner,sun50i-h6-operating-points";
> + nvmem-cells = <&cpu_speed_grade>;
> + opp-shared;
> +
> + opp@480000000 {
> + clock-latency-ns = <244144>; /* 8 32k periods */
> + opp-hz = /bits/ 64 <480000000>;
> +
> + opp-microvolt-speed0 = <880000 880000 1200000>;
> + opp-microvolt-speed1 = <820000 820000 1200000>;
> + opp-microvolt-speed2 = <820000 820000 1200000>;
> + };
> +
> + opp@720000000 {
> + clock-latency-ns = <244144>; /* 8 32k periods */
> + opp-hz = /bits/ 64 <720000000>;
> +
> + opp-microvolt-speed0 = <880000 880000 1200000>;
> + opp-microvolt-speed1 = <820000 820000 1200000>;
> + opp-microvolt-speed2 = <820000 820000 1200000>;
> + };
> +
> + opp@816000000 {
> + clock-latency-ns = <244144>; /* 8 32k periods */
> + opp-hz = /bits/ 64 <816000000>;
> +
> + opp-microvolt-speed0 = <880000 880000 1200000>;
> + opp-microvolt-speed1 = <820000 820000 1200000>;
> + opp-microvolt-speed2 = <820000 820000 1200000>;
> + };
> +
> + opp@888000000 {
> + clock-latency-ns = <244144>; /* 8 32k periods */
> + opp-hz = /bits/ 64 <888000000>;
> +
> + opp-microvolt-speed0 = <880000 880000 1200000>;
> + opp-microvolt-speed1 = <820000 820000 1200000>;
> + opp-microvolt-speed2 = <820000 820000 1200000>;
> + };
> +
> + opp@1080000000 {
> + clock-latency-ns = <244144>; /* 8 32k periods */
> + opp-hz = /bits/ 64 <1080000000>;
> +
> + opp-microvolt-speed0 = <940000 940000 1200000>;
> + opp-microvolt-speed1 = <880000 880000 1200000>;
> + opp-microvolt-speed2 = <880000 880000 1200000>;
> + };
> +
> + opp@1320000000 {
> + clock-latency-ns = <244144>; /* 8 32k periods */
> + opp-hz = /bits/ 64 <1320000000>;
> +
> + opp-microvolt-speed0 = <1000000 1000000 1200000>;
> + opp-microvolt-speed1 = <940000 940000 1200000>;
> + opp-microvolt-speed2 = <940000 940000 1200000>;
> + };
> +
> + opp@1488000000 {
> + clock-latency-ns = <244144>; /* 8 32k periods */
> + opp-hz = /bits/ 64 <1488000000>;
> +
> + opp-microvolt-speed0 = <1060000 1060000 1200000>;
> + opp-microvolt-speed1 = <1000000 1000000 1200000>;
> + opp-microvolt-speed2 = <1000000 1000000 1200000>;
> + };
> +
> + opp@1608000000 {
> + clock-latency-ns = <244144>; /* 8 32k periods */
> + opp-hz = /bits/ 64 <1608000000>;
> +
> + opp-microvolt-speed0 = <1090000 1090000 1200000>;
> + opp-microvolt-speed1 = <1030000 1030000 1200000>;
> + opp-microvolt-speed2 = <1030000 1030000 1200000>;
> + };
> +
> + opp@1704000000 {
> + clock-latency-ns = <244144>; /* 8 32k periods */
> + opp-hz = /bits/ 64 <1704000000>;
> +
> + opp-microvolt-speed0 = <1120000 1120000 1200000>;
> + opp-microvolt-speed1 = <1060000 1060000 1200000>;
> + opp-microvolt-speed2 = <1060000 1060000 1200000>;
> + };
> +
> + opp@1800000000 {
> + clock-latency-ns = <244144>; /* 8 32k periods */
> + opp-hz = /bits/ 64 <1800000000>;
> +
> + opp-microvolt-speed0 = <1160000 1160000 1200000>;
> + opp-microvolt-speed1 = <1100000 1100000 1200000>;
> + opp-microvolt-speed2 = <1100000 1100000 1200000>;
> + };
> + };
> +};
> +
> +&cpu0 {
> + operating-points-v2 = <&cpu_opp_table>;
> +};
> +
> +&cpu1 {
> + operating-points-v2 = <&cpu_opp_table>;
> +};
> +
> +&cpu2 {
> + operating-points-v2 = <&cpu_opp_table>;
> +};
> +
> +&cpu3 {
> + operating-points-v2 = <&cpu_opp_table>;
> +};
> diff --git a/arch/arm/dts/sun50i-h6-orangepi-lite2.dts
> b/arch/arm/dts/sun50i-h6-orangepi-lite2.dts
> index e098a2475f2d..e8770858b5d0 100644
> --- a/arch/arm/dts/sun50i-h6-orangepi-lite2.dts
> +++ b/arch/arm/dts/sun50i-h6-orangepi-lite2.dts
> @@ -1,11 +1,74 @@
> -// SPDX-License-Identifier: (GPL-2.0+ or MIT)
> -/*
> - * Copyright (C) 2018 Jagan Teki <ja...@openedev.com>
> - */
> +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
> +// Copyright (C) 2018 Jagan Teki <ja...@openedev.com>
>
> #include "sun50i-h6-orangepi.dtsi"
>
> / {
> model = "OrangePi Lite2";
> compatible = "xunlong,orangepi-lite2", "allwinner,sun50i-h6";
> +
> + aliases {
> + serial1 = &uart1; /* BT-UART */
> + };
> +
> + wifi_pwrseq: wifi_pwrseq {
> + compatible = "mmc-pwrseq-simple";
> + clocks = <&rtc 1>;
> + clock-names = "ext_clock";
> + reset-gpios = <&r_pio 1 3 GPIO_ACTIVE_LOW>; /* PM3 */
> + post-power-on-delay-ms = <200>;
> + };
> +};
> +
> +&mmc1 {
> + vmmc-supply = <®_cldo2>;
> + vqmmc-supply = <®_bldo3>;
> + mmc-pwrseq = <&wifi_pwrseq>;
> + bus-width = <4>;
> + non-removable;
> + status = "okay";
> +
> + brcm: sdio-wifi@1 {
> + reg = <1>;
> + compatible = "brcm,bcm4329-fmac";
> + interrupt-parent = <&r_pio>;
> + interrupts = <1 0 IRQ_TYPE_LEVEL_LOW>; /* PM0 */
> + interrupt-names = "host-wake";
> + };
> +};
> +
> +®_cldo2 {
> + /*
> + * This regulator is connected with CLDO3.
> + * Before the kernel can support synchronized
> + * enable of coupled regulators, keep them
> + * both always on as a ugly hack.
> + */
> + regulator-always-on;
> +};
> +
> +®_cldo3 {
> + /*
> + * This regulator is connected with CLDO2.
> + * See the comments for CLDO2.
> + */
> + regulator-always-on;
> +};
> +
> +/* There's the BT part of the AP6255 connected to that UART */
> +&uart1 {
> + pinctrl-names = "default";
> + pinctrl-0 = <&uart1_pins>, <&uart1_rts_cts_pins>;
> + uart-has-rtscts;
> + status = "okay";
> +
> + bluetooth {
> + compatible = "brcm,bcm4345c5";
> + clocks = <&rtc 1>;
> + clock-names = "lpo";
> + device-wakeup-gpios = <&r_pio 1 2 GPIO_ACTIVE_HIGH>; /* PM2 */
> + host-wakeup-gpios = <&r_pio 1 1 GPIO_ACTIVE_HIGH>; /* PM1 */
> + shutdown-gpios = <&r_pio 1 4 GPIO_ACTIVE_HIGH>; /* PM4 */
> + max-speed = <1500000>;
> + };
> };
> diff --git a/arch/arm/dts/sun50i-h6-orangepi-one-plus.dts
> b/arch/arm/dts/sun50i-h6-orangepi-one-plus.dts
> index 12e17567ab56..29a081e72a9b 100644
> --- a/arch/arm/dts/sun50i-h6-orangepi-one-plus.dts
> +++ b/arch/arm/dts/sun50i-h6-orangepi-one-plus.dts
> @@ -1,12 +1,43 @@
> -// SPDX-License-Identifier: (GPL-2.0+ or MIT)
> -/*
> - * Copyright (C) 2018 Amarula Solutions
> - * Author: Jagan Teki <ja...@amarulasolutions.com>
> - */
> +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
> +// Copyright (C) 2018 Amarula Solutions
> +// Author: Jagan Teki <ja...@amarulasolutions.com>
>
> #include "sun50i-h6-orangepi.dtsi"
>
> / {
> model = "OrangePi One Plus";
> compatible = "xunlong,orangepi-one-plus", "allwinner,sun50i-h6";
> +
> + aliases {
> + ethernet0 = &emac;
> + };
> +
> + reg_gmac_3v3: gmac-3v3 {
> + compatible = "regulator-fixed";
> + regulator-name = "vcc-gmac-3v3";
> + regulator-min-microvolt = <3300000>;
> + regulator-max-microvolt = <3300000>;
> + startup-delay-us = <100000>;
> + enable-active-high;
> + gpio = <&pio 3 6 GPIO_ACTIVE_HIGH>; /* PD6 */
> + vin-supply = <®_aldo2>;
> + };
> +};
> +
> +&emac {
> + pinctrl-names = "default";
> + pinctrl-0 = <&ext_rgmii_pins>;
> + phy-mode = "rgmii-id";
> + phy-handle = <&ext_rgmii_phy>;
> + phy-supply = <®_gmac_3v3>;
> + allwinner,rx-delay-ps = <200>;
> + allwinner,tx-delay-ps = <200>;
> + status = "okay";
> +};
> +
> +&mdio {
> + ext_rgmii_phy: ethernet-phy@1 {
> + compatible = "ethernet-phy-ieee802.3-c22";
> + reg = <1>;
> + };
> };
> diff --git a/arch/arm/dts/sun50i-h6-orangepi.dtsi
> b/arch/arm/dts/sun50i-h6-orangepi.dtsi
> index 62e27948a3fa..ebc120a9232f 100644
> --- a/arch/arm/dts/sun50i-h6-orangepi.dtsi
> +++ b/arch/arm/dts/sun50i-h6-orangepi.dtsi
> @@ -1,8 +1,6 @@
> -// SPDX-License-Identifier: (GPL-2.0+ or MIT)
> -/*
> - * Copyright (C) 2018 Amarula Solutions
> - * Author: Jagan Teki <ja...@amarulasolutions.com>
> - */
> +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
> +// Copyright (C) 2018 Amarula Solutions
> +// Author: Jagan Teki <ja...@amarulasolutions.com>
>
> /dts-v1/;
>
> @@ -22,6 +20,25 @@
> stdout-path = "serial0:115200n8";
> };
>
> + connector {
> + compatible = "hdmi-connector";
> + type = "a";
> + ddc-en-gpios = <&pio 7 2 GPIO_ACTIVE_HIGH>; /* PH2 */
> +
> + port {
> + hdmi_con_in: endpoint {
> + remote-endpoint = <&hdmi_out_con>;
> + };
> + };
> + };
> +
> + ext_osc32k: ext_osc32k_clk {
> + #clock-cells = <0>;
> + compatible = "fixed-clock";
> + clock-frequency = <32768>;
> + clock-output-names = "ext_osc32k";
> + };
> +
> leds {
> compatible = "gpio-leds";
>
> @@ -47,6 +64,10 @@
> };
> };
>
> +&de {
> + status = "okay";
> +};
> +
> &ehci0 {
> status = "okay";
> };
> @@ -55,6 +76,21 @@
> status = "okay";
> };
>
> +&gpu {
> + mali-supply = <®_dcdcc>;
> + status = "okay";
> +};
> +
> +&hdmi {
> + status = "okay";
> +};
> +
> +&hdmi_out {
> + hdmi_out_con: endpoint {
> + remote-endpoint = <&hdmi_con_in>;
> + };
> +};
> +
> &mmc0 {
> vmmc-supply = <®_cldo1>;
> cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>;
> @@ -70,6 +106,12 @@
> status = "okay";
> };
>
> +&pio {
> + vcc-pc-supply = <®_bldo2>;
> + vcc-pd-supply = <®_cldo1>;
> + vcc-pg-supply = <®_aldo1>;
> +};
> +
> &r_i2c {
> status = "okay";
>
> @@ -163,6 +205,7 @@
> };
>
> reg_dcdcc: dcdcc {
> + regulator-enable-ramp-delay = <32000>;
> regulator-min-microvolt = <810000>;
> regulator-max-microvolt = <1080000>;
> regulator-name = "vdd-gpu";
> @@ -189,6 +232,18 @@
> };
> };
>
> +&r_ir {
> + status = "okay";
> +};
> +
> +&r_pio {
> + vcc-pm-supply = <®_bldo3>;
> +};
> +
> +&rtc {
> + clocks = <&ext_osc32k>;
> +};
> +
> &uart0 {
> pinctrl-names = "default";
> pinctrl-0 = <&uart0_ph_pins>;
> @@ -196,7 +251,12 @@
> };
>
> &usb2otg {
> - dr_mode = "otg";
> + /*
> + * OrangePi Lite 2 and One Plus, where this DT is used, don't
> + * have a controllable VBUS even though they do have an ID pin.
> + * Using it as anything but a USB host is unsafe.
> + */
> + dr_mode = "host";
> status = "okay";
> };
>
> diff --git a/arch/arm/dts/sun50i-h6-pine-h64.dts
> b/arch/arm/dts/sun50i-h6-pine-h64.dts
> index 189834518391..961732c52aa0 100644
> --- a/arch/arm/dts/sun50i-h6-pine-h64.dts
> +++ b/arch/arm/dts/sun50i-h6-pine-h64.dts
> @@ -1,30 +1,38 @@
> -// SPDX-License-Identifier: (GPL-2.0+ or MIT)
> -/*
> - * Copyright (c) 2017 Icenowy Zheng <icen...@aosc.io>
> - */
> +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
> +// Copyright (c) 2017 Icenowy Zheng <icen...@aosc.io>
>
> /dts-v1/;
>
> #include "sun50i-h6.dtsi"
> +#include "sun50i-h6-cpu-opp.dtsi"
>
> #include <dt-bindings/gpio/gpio.h>
>
> / {
> - model = "Pine H64";
> + model = "Pine H64 model A";
> compatible = "pine64,pine-h64", "allwinner,sun50i-h6";
>
> aliases {
> ethernet0 = &emac;
> serial0 = &uart0;
> + spi0 = &spi0;
> };
>
> chosen {
> stdout-path = "serial0:115200n8";
> };
>
> - connector {
> + ext_osc32k: ext_osc32k_clk {
> + #clock-cells = <0>;
> + compatible = "fixed-clock";
> + clock-frequency = <32768>;
> + clock-output-names = "ext_osc32k";
> + };
> +
> + hdmi_connector: connector {
> compatible = "hdmi-connector";
> type = "a";
> + ddc-en-gpios = <&pio 7 2 GPIO_ACTIVE_HIGH>; /* PH2 */
>
> port {
> hdmi_con_in: endpoint {
> @@ -52,6 +60,16 @@
> };
> };
>
> + reg_gmac_3v3: gmac-3v3 {
> + compatible = "regulator-fixed";
> + regulator-name = "vcc-gmac-3v3";
> + regulator-min-microvolt = <3300000>;
> + regulator-max-microvolt = <3300000>;
> + startup-delay-us = <100000>;
> + gpio = <&pio 2 16 GPIO_ACTIVE_HIGH>;
> + enable-active-high;
> + };
> +
> reg_usb_vbus: vbus {
> compatible = "regulator-fixed";
> regulator-name = "usb-vbus";
> @@ -63,25 +81,35 @@
> };
> };
>
> +&cpu0 {
> + cpu-supply = <®_dcdca>;
> +};
> +
> +&de {
> + status = "okay";
> +};
> +
> +&ehci0 {
> + status = "okay";
> +};
> +
> +&ehci3 {
> + status = "okay";
> +};
> +
> &emac {
> pinctrl-names = "default";
> pinctrl-0 = <&ext_rgmii_pins>;
> - phy-mode = "rgmii";
> + phy-mode = "rgmii-id";
> phy-handle = <&ext_rgmii_phy>;
> - phy-supply = <®_aldo2>;
> + phy-supply = <®_gmac_3v3>;
> allwinner,rx-delay-ps = <200>;
> allwinner,tx-delay-ps = <200>;
> status = "okay";
> };
>
> -&mdio {
> - ext_rgmii_phy: ethernet-phy@1 {
> - compatible = "ethernet-phy-ieee802.3-c22";
> - reg = <1>;
> - };
> -};
> -
> -&de {
> +&gpu {
> + mali-supply = <®_dcdcc>;
> status = "okay";
> };
>
> @@ -95,12 +123,11 @@
> };
> };
>
> -&ehci0 {
> - status = "okay";
> -};
> -
> -&ehci3 {
> - status = "okay";
> +&mdio {
> + ext_rgmii_phy: ethernet-phy@1 {
> + compatible = "ethernet-phy-ieee802.3-c22";
> + reg = <1>;
> + };
> };
>
> &mmc0 {
> @@ -216,13 +243,16 @@
> reg_dcdca: dcdca {
> regulator-always-on;
> regulator-min-microvolt = <810000>;
> - regulator-max-microvolt = <1080000>;
> + regulator-max-microvolt = <1160000>;
> + regulator-ramp-delay = <2500>;
> regulator-name = "vdd-cpu";
> };
>
> reg_dcdcc: dcdcc {
> + regulator-enable-ramp-delay = <32000>;
> regulator-min-microvolt = <810000>;
> regulator-max-microvolt = <1080000>;
> + regulator-ramp-delay = <2500>;
> regulator-name = "vdd-gpu";
> };
>
> @@ -255,10 +285,36 @@
> };
> };
>
> +&r_ir {
> + status = "okay";
> +};
> +
> &r_pio {
> vcc-pm-supply = <®_aldo1>;
> };
>
> +&rtc {
> + clocks = <&ext_osc32k>;
> +};
> +
> +/*
> + * The CS pin is shared with the MMC2 CMD pin, so we cannot have the SPI
> + * flash and eMMC at the same time, as one of them would fail probing.
> + * Disable SPI0 in here, to prefer the more useful eMMC. U-Boot can
> + * fix this up in no eMMC is connected.
> + */
> +&spi0 {
> + pinctrl-0 = <&spi0_pins>, <&spi0_cs_pin>;
> + pinctrl-names = "default";
> + status = "disabled";
> +
> + flash@0 {
> + compatible = "winbond,w25q128", "jedec,spi-nor";
> + reg = <0>;
> + spi-max-frequency = <4000000>;
> + };
> +};
> +
> &uart0 {
> pinctrl-names = "default";
> pinctrl-0 = <&uart0_ph_pins>;
> diff --git a/arch/arm/dts/sun50i-h6.dtsi b/arch/arm/dts/sun50i-h6.dtsi
> index a117f479ae55..8a62a9fbe347 100644
> --- a/arch/arm/dts/sun50i-h6.dtsi
> +++ b/arch/arm/dts/sun50i-h6.dtsi
> @@ -1,7 +1,5 @@
> -// SPDX-License-Identifier: (GPL-2.0+ or MIT)
> -/*
> - * Copyright (C) 2017 Icenowy Zheng <icen...@aosc.io>
> - */
> +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
> +// Copyright (C) 2017 Icenowy Zheng <icen...@aosc.io>
>
> #include <dt-bindings/interrupt-controller/arm-gic.h>
> #include <dt-bindings/clock/sun50i-h6-ccu.h>
> @@ -11,6 +9,7 @@
> #include <dt-bindings/reset/sun50i-h6-ccu.h>
> #include <dt-bindings/reset/sun50i-h6-r-ccu.h>
> #include <dt-bindings/reset/sun8i-de2.h>
> +#include <dt-bindings/thermal/thermal.h>
>
> / {
> interrupt-parent = <&gic>;
> @@ -26,6 +25,9 @@
> device_type = "cpu";
> reg = <0>;
> enable-method = "psci";
> + clocks = <&ccu CLK_CPUX>;
> + clock-latency-ns = <244144>; /* 8 32k periods */
> + #cooling-cells = <2>;
> };
>
> cpu1: cpu@1 {
> @@ -33,6 +35,9 @@
> device_type = "cpu";
> reg = <1>;
> enable-method = "psci";
> + clocks = <&ccu CLK_CPUX>;
> + clock-latency-ns = <244144>; /* 8 32k periods */
> + #cooling-cells = <2>;
> };
>
> cpu2: cpu@2 {
> @@ -40,6 +45,9 @@
> device_type = "cpu";
> reg = <2>;
> enable-method = "psci";
> + clocks = <&ccu CLK_CPUX>;
> + clock-latency-ns = <244144>; /* 8 32k periods */
> + #cooling-cells = <2>;
> };
>
> cpu3: cpu@3 {
> @@ -47,6 +55,9 @@
> device_type = "cpu";
> reg = <3>;
> enable-method = "psci";
> + clocks = <&ccu CLK_CPUX>;
> + clock-latency-ns = <244144>; /* 8 32k periods */
> + #cooling-cells = <2>;
> };
> };
>
> @@ -56,14 +67,6 @@
> status = "disabled";
> };
>
> - iosc: internal-osc-clk {
> - #clock-cells = <0>;
> - compatible = "fixed-clock";
> - clock-frequency = <16000000>;
> - clock-accuracy = <300000000>;
> - clock-output-names = "iosc";
> - };
> -
> osc24M: osc24M_clk {
> #clock-cells = <0>;
> compatible = "fixed-clock";
> @@ -71,11 +74,13 @@
> clock-output-names = "osc24M";
> };
>
> - osc32k: osc32k_clk {
> - #clock-cells = <0>;
> - compatible = "fixed-clock";
> - clock-frequency = <32768>;
> - clock-output-names = "osc32k";
> + pmu {
> + compatible = "arm,cortex-a53-pmu";
> + interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
> + interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
> };
>
> psci {
> @@ -85,6 +90,7 @@
>
> timer {
> compatible = "arm,armv8-timer";
> + arm,no-tick-in-suspend;
> interrupts = <GIC_PPI 13
> (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
> <GIC_PPI 14
> @@ -130,6 +136,7 @@
> clock-names = "bus",
> "mod";
> resets = <&display_clocks RST_MIXER0>;
> + iommus = <&iommu 0>;
>
> ports {
> #address-cells = <1>;
> @@ -155,6 +162,30 @@
> resets = <&ccu RST_BUS_VE>;
> interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
> allwinner,sram = <&ve_sram 1>;
> + iommus = <&iommu 3>;
> + };
> +
> + gpu: gpu@1800000 {
> + compatible = "allwinner,sun50i-h6-mali",
> + "arm,mali-t720";
> + reg = <0x01800000 0x4000>;
> + interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
> + interrupt-names = "job", "mmu", "gpu";
> + clocks = <&ccu CLK_GPU>, <&ccu CLK_BUS_GPU>;
> + clock-names = "core", "bus";
> + resets = <&ccu RST_BUS_GPU>;
> + status = "disabled";
> + };
> +
> + crypto: crypto@1904000 {
> + compatible = "allwinner,sun50i-h6-crypto";
> + reg = <0x01904000 0x1000>;
> + interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&ccu CLK_BUS_CE>, <&ccu CLK_CE>, <&ccu
> CLK_MBUS_CE>;
> + clock-names = "bus", "mod", "ram";
> + resets = <&ccu RST_BUS_CE>;
> };
>
> syscon: syscon@3000000 {
> @@ -197,7 +228,7 @@
> ccu: clock@3001000 {
> compatible = "allwinner,sun50i-h6-ccu";
> reg = <0x03001000 0x1000>;
> - clocks = <&osc24M>, <&osc32k>, <&iosc>;
> + clocks = <&osc24M>, <&rtc 0>, <&rtc 2>;
> clock-names = "hosc", "losc", "iosc";
> #clock-cells = <1>;
> #reset-cells = <1>;
> @@ -215,9 +246,29 @@
> #dma-cells = <1>;
> };
>
> - sid: sid@3006000 {
> + msgbox: mailbox@3003000 {
> + compatible = "allwinner,sun50i-h6-msgbox",
> + "allwinner,sun6i-a31-msgbox";
> + reg = <0x03003000 0x1000>;
> + clocks = <&ccu CLK_BUS_MSGBOX>;
> + resets = <&ccu RST_BUS_MSGBOX>;
> + interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
> + #mbox-cells = <1>;
> + };
> +
> + sid: efuse@3006000 {
> compatible = "allwinner,sun50i-h6-sid";
> reg = <0x03006000 0x400>;
> + #address-cells = <1>;
> + #size-cells = <1>;
> +
> + ths_calibration: thermal-sensor-calibration@14 {
> + reg = <0x14 0x8>;
> + };
> +
> + cpu_speed_grade: cpu-speed-grade@1c {
> + reg = <0x1c 0x4>;
> + };
> };
>
> watchdog: watchdog@30090a0 {
> @@ -225,10 +276,21 @@
> "allwinner,sun6i-a31-wdt";
> reg = <0x030090a0 0x20>;
> interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&osc24M>;
> /* Broken on some H6 boards */
> status = "disabled";
> };
>
> + pwm: pwm@300a000 {
> + compatible = "allwinner,sun50i-h6-pwm";
> + reg = <0x0300a000 0x400>;
> + clocks = <&osc24M>, <&ccu CLK_BUS_PWM>;
> + clock-names = "mod", "bus";
> + resets = <&ccu RST_BUS_PWM>;
> + #pwm-cells = <3>;
> + status = "disabled";
> + };
> +
> pio: pinctrl@300b000 {
> compatible = "allwinner,sun50i-h6-pinctrl";
> reg = <0x0300b000 0x400>;
> @@ -236,7 +298,7 @@
> <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>,
> <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>,
> <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
> - clocks = <&ccu CLK_APB1>, <&osc24M>, <&osc32k>;
> + clocks = <&ccu CLK_APB1>, <&osc24M>, <&rtc 0>;
> clock-names = "apb", "hosc", "losc";
> gpio-controller;
> #gpio-cells = <3>;
> @@ -256,6 +318,21 @@
> function = "hdmi";
> };
>
> + i2c0_pins: i2c0-pins {
> + pins = "PD25", "PD26";
> + function = "i2c0";
> + };
> +
> + i2c1_pins: i2c1-pins {
> + pins = "PH5", "PH6";
> + function = "i2c1";
> + };
> +
> + i2c2_pins: i2c2-pins {
> + pins = "PD23", "PD24";
> + function = "i2c2";
> + };
> +
> mmc0_pins: mmc0-pins {
> pins = "PF0", "PF1", "PF2", "PF3",
> "PF4", "PF5";
> @@ -264,10 +341,7 @@
> bias-pull-up;
> };
>
> - /*
> - * /omit-if-no-ref/ isn't supported by U-boot
> - * keep this comment to avoid bad sync with Linux
> - */
> + /omit-if-no-ref/
> mmc1_pins: mmc1-pins {
> pins = "PG0", "PG1", "PG2", "PG3",
> "PG4", "PG5";
> @@ -285,10 +359,50 @@
> bias-pull-up;
> };
>
> + /omit-if-no-ref/
> + spi0_pins: spi0-pins {
> + pins = "PC0", "PC2", "PC3";
> + function = "spi0";
> + };
> +
> + /* pin shared with MMC2-CMD (eMMC) */
> + /omit-if-no-ref/
> + spi0_cs_pin: spi0-cs-pin {
> + pins = "PC5";
> + function = "spi0";
> + };
> +
> + /omit-if-no-ref/
> + spi1_pins: spi1-pins {
> + pins = "PH4", "PH5", "PH6";
> + function = "spi1";
> + };
> +
> + /omit-if-no-ref/
> + spi1_cs_pin: spi1-cs-pin {
> + pins = "PH3";
> + function = "spi1";
> + };
> +
> + spdif_tx_pin: spdif-tx-pin {
> + pins = "PH7";
> + function = "spdif";
> + };
> +
> uart0_ph_pins: uart0-ph-pins {
> pins = "PH0", "PH1";
> function = "uart0";
> };
> +
> + uart1_pins: uart1-pins {
> + pins = "PG6", "PG7";
> + function = "uart1";
> + };
> +
> + uart1_rts_cts_pins: uart1-rts-cts-pins {
> + pins = "PG8", "PG9";
> + function = "uart1";
> + };
> };
>
> gic: interrupt-controller@3021000 {
> @@ -302,6 +416,15 @@
> #interrupt-cells = <3>;
> };
>
> + iommu: iommu@30f0000 {
> + compatible = "allwinner,sun50i-h6-iommu";
> + reg = <0x030f0000 0x10000>;
> + interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&ccu CLK_BUS_IOMMU>;
> + resets = <&ccu RST_BUS_IOMMU>;
> + #iommu-cells = <1>;
> + };
> +
> mmc0: mmc@4020000 {
> compatible = "allwinner,sun50i-h6-mmc",
> "allwinner,sun50i-a64-mmc";
> @@ -394,6 +517,78 @@
> status = "disabled";
> };
>
> + i2c0: i2c@5002000 {
> + compatible = "allwinner,sun50i-h6-i2c",
> + "allwinner,sun6i-a31-i2c";
> + reg = <0x05002000 0x400>;
> + interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&ccu CLK_BUS_I2C0>;
> + resets = <&ccu RST_BUS_I2C0>;
> + pinctrl-names = "default";
> + pinctrl-0 = <&i2c0_pins>;
> + status = "disabled";
> + #address-cells = <1>;
> + #size-cells = <0>;
> + };
> +
> + i2c1: i2c@5002400 {
> + compatible = "allwinner,sun50i-h6-i2c",
> + "allwinner,sun6i-a31-i2c";
> + reg = <0x05002400 0x400>;
> + interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&ccu CLK_BUS_I2C1>;
> + resets = <&ccu RST_BUS_I2C1>;
> + pinctrl-names = "default";
> + pinctrl-0 = <&i2c1_pins>;
> + status = "disabled";
> + #address-cells = <1>;
> + #size-cells = <0>;
> + };
> +
> + i2c2: i2c@5002800 {
> + compatible = "allwinner,sun50i-h6-i2c",
> + "allwinner,sun6i-a31-i2c";
> + reg = <0x05002800 0x400>;
> + interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&ccu CLK_BUS_I2C2>;
> + resets = <&ccu RST_BUS_I2C2>;
> + pinctrl-names = "default";
> + pinctrl-0 = <&i2c2_pins>;
> + status = "disabled";
> + #address-cells = <1>;
> + #size-cells = <0>;
> + };
> +
> + spi0: spi@5010000 {
> + compatible = "allwinner,sun50i-h6-spi",
> + "allwinner,sun8i-h3-spi";
> + reg = <0x05010000 0x1000>;
> + interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&ccu CLK_BUS_SPI0>, <&ccu CLK_SPI0>;
> + clock-names = "ahb", "mod";
> + dmas = <&dma 22>, <&dma 22>;
> + dma-names = "rx", "tx";
> + resets = <&ccu RST_BUS_SPI0>;
> + status = "disabled";
> + #address-cells = <1>;
> + #size-cells = <0>;
> + };
> +
> + spi1: spi@5011000 {
> + compatible = "allwinner,sun50i-h6-spi",
> + "allwinner,sun8i-h3-spi";
> + reg = <0x05011000 0x1000>;
> + interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&ccu CLK_BUS_SPI1>, <&ccu CLK_SPI1>;
> + clock-names = "ahb", "mod";
> + dmas = <&dma 23>, <&dma 23>;
> + dma-names = "rx", "tx";
> + resets = <&ccu RST_BUS_SPI1>;
> + status = "disabled";
> + #address-cells = <1>;
> + #size-cells = <0>;
> + };
> +
> emac: ethernet@5020000 {
> compatible = "allwinner,sun50i-h6-emac",
> "allwinner,sun50i-a64-emac";
> @@ -414,6 +609,34 @@
> };
> };
>
> + i2s1: i2s@5091000 {
> + #sound-dai-cells = <0>;
> + compatible = "allwinner,sun50i-h6-i2s";
> + reg = <0x05091000 0x1000>;
> + interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&ccu CLK_BUS_I2S1>, <&ccu CLK_I2S1>;
> + clock-names = "apb", "mod";
> + dmas = <&dma 4>, <&dma 4>;
> + resets = <&ccu RST_BUS_I2S1>;
> + dma-names = "rx", "tx";
> + status = "disabled";
> + };
> +
> + spdif: spdif@5093000 {
> + #sound-dai-cells = <0>;
> + compatible = "allwinner,sun50i-h6-spdif";
> + reg = <0x05093000 0x400>;
> + interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&ccu CLK_BUS_SPDIF>, <&ccu CLK_SPDIF>;
> + clock-names = "apb", "spdif";
> + resets = <&ccu RST_BUS_SPDIF>;
> + dmas = <&dma 2>;
> + dma-names = "tx";
> + pinctrl-names = "default";
> + pinctrl-0 = <&spdif_tx_pin>;
> + status = "disabled";
> + };
> +
> usb2otg: usb@5100000 {
> compatible = "allwinner,sun50i-h6-musb",
> "allwinner,sun8i-a33-musb";
> @@ -470,6 +693,38 @@
> status = "disabled";
> };
>
> + dwc3: usb@5200000 {
> + compatible = "snps,dwc3";
> + reg = <0x05200000 0x10000>;
> + interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&ccu CLK_BUS_XHCI>,
> + <&ccu CLK_BUS_XHCI>,
> + <&rtc 0>;
> + clock-names = "ref", "bus_early", "suspend";
> + resets = <&ccu RST_BUS_XHCI>;
> + /*
> + * The datasheet of the chip doesn't declare the
> + * peripheral function, and there's no boards known
> + * to have a USB Type-B port routed to the port.
> + * In addition, no one has tested the peripheral
> + * function yet.
> + * So set the dr_mode to "host" in the DTSI file.
> + */
> + dr_mode = "host";
> + phys = <&usb3phy>;
> + phy-names = "usb3-phy";
> + status = "disabled";
> + };
> +
> + usb3phy: phy@5210000 {
> + compatible = "allwinner,sun50i-h6-usb3-phy";
> + reg = <0x5210000 0x10000>;
> + clocks = <&ccu CLK_USB_PHY1>;
> + resets = <&ccu RST_USB_PHY1>;
> + #phy-cells = <0>;
> + status = "disabled";
> + };
> +
> ehci3: usb@5311000 {
> compatible = "allwinner,sun50i-h6-ehci", "generic-ehci";
> reg = <0x05311000 0x100>;
> @@ -480,6 +735,7 @@
> resets = <&ccu RST_BUS_OHCI3>,
> <&ccu RST_BUS_EHCI3>;
> phys = <&usb2phy 3>;
> + phy-names = "usb";
> status = "disabled";
> };
>
> @@ -491,6 +747,7 @@
> <&ccu CLK_USB_OHCI3>;
> resets = <&ccu RST_BUS_OHCI3>;
> phys = <&usb2phy 3>;
> + phy-names = "usb";
> status = "disabled";
> };
>
> @@ -507,7 +764,7 @@
> resets = <&ccu RST_BUS_HDMI_SUB>, <&ccu RST_BUS_HDCP>;
> reset-names = "ctrl", "hdcp";
> phys = <&hdmi_phy>;
> - phy-names = "hdmi-phy";
> + phy-names = "phy";
> pinctrl-names = "default";
> pinctrl-0 = <&hdmi_pins>;
> status = "disabled";
> @@ -549,7 +806,6 @@
> "tcon-tv0";
> clock-output-names = "tcon-top-tv0";
> resets = <&ccu RST_BUS_TCON_TOP>;
> - reset-names = "rst";
> #clock-cells = <1>;
>
> ports {
> @@ -636,10 +892,19 @@
> };
> };
>
> + rtc: rtc@7000000 {
> + compatible = "allwinner,sun50i-h6-rtc";
> + reg = <0x07000000 0x400>;
> + interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
> + clock-output-names = "osc32k", "osc32k-out", "iosc";
> + #clock-cells = <1>;
> + };
> +
> r_ccu: clock@7010000 {
> compatible = "allwinner,sun50i-h6-r-ccu";
> reg = <0x07010000 0x400>;
> - clocks = <&osc24M>, <&osc32k>, <&iosc>,
> + clocks = <&osc24M>, <&rtc 0>, <&rtc 2>,
> <&ccu CLK_PLL_PERIPH0>;
> clock-names = "hosc", "losc", "iosc", "pll-periph";
> #clock-cells = <1>;
> @@ -651,6 +916,7 @@
> "allwinner,sun6i-a31-wdt";
> reg = <0x07020400 0x20>;
> interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&osc24M>;
> };
>
> r_intc: interrupt-controller@7021000 {
> @@ -667,7 +933,7 @@
> reg = <0x07022000 0x400>;
> interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
> <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
> - clocks = <&r_ccu CLK_R_APB1>, <&osc24M>, <&osc32k>;
> + clocks = <&r_ccu CLK_R_APB1>, <&osc24M>, <&rtc 0>;
> clock-names = "apb", "hosc", "losc";
> gpio-controller;
> #gpio-cells = <3>;
> @@ -678,10 +944,30 @@
> pins = "PL0", "PL1";
> function = "s_i2c";
> };
> +
> + r_ir_rx_pin: r-ir-rx-pin {
> + pins = "PL9";
> + function = "s_cir_rx";
> + };
> + };
> +
> + r_ir: ir@7040000 {
> + compatible = "allwinner,sun50i-h6-ir",
> + "allwinner,sun6i-a31-ir";
> + reg = <0x07040000 0x400>;
> + interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&r_ccu CLK_R_APB1_IR>,
> + <&r_ccu CLK_IR>;
> + clock-names = "apb", "ir";
> + resets = <&r_ccu RST_R_APB1_IR>;
> + pinctrl-names = "default";
> + pinctrl-0 = <&r_ir_rx_pin>;
> + status = "disabled";
> };
>
> r_i2c: i2c@7081400 {
> - compatible = "allwinner,sun6i-a31-i2c";
> + compatible = "allwinner,sun50i-h6-i2c",
> + "allwinner,sun6i-a31-i2c";
> reg = <0x07081400 0x400>;
> interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
> clocks = <&r_ccu CLK_R_APB2_I2C>;
> @@ -692,5 +978,55 @@
> #address-cells = <1>;
> #size-cells = <0>;
> };
> +
> + ths: thermal-sensor@5070400 {
> + compatible = "allwinner,sun50i-h6-ths";
> + reg = <0x05070400 0x100>;
> + interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&ccu CLK_BUS_THS>;
> + clock-names = "bus";
> + resets = <&ccu RST_BUS_THS>;
> + nvmem-cells = <&ths_calibration>;
> + nvmem-cell-names = "calibration";
> + #thermal-sensor-cells = <1>;
> + };
> + };
> +
> + thermal-zones {
> + cpu-thermal {
> + polling-delay-passive = <0>;
> + polling-delay = <0>;
> + thermal-sensors = <&ths 0>;
> +
> + trips {
> + cpu_alert: cpu-alert {
> + temperature = <85000>;
> + hysteresis = <2000>;
> + type = "passive";
> + };
> +
> + cpu-crit {
> + temperature = <100000>;
> + hysteresis = <0>;
> + type = "critical";
> + };
> + };
> +
> + cooling-maps {
> + map0 {
> + trip = <&cpu_alert>;
> + cooling-device = <&cpu0
> THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
> + <&cpu1
> THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
> + <&cpu2
> THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
> + <&cpu3
> THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
> + };
> + };
> + };
> +
> + gpu-thermal {
> + polling-delay-passive = <0>;
> + polling-delay = <0>;
> + thermal-sensors = <&ths 1>;
> + };
> };
> };
>
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