[linux-sunxi] AXP209 startup issues

I have problems with boards that I prototyped for A20 based design. When I power up the board or apply reset I would get some output for 100ms or so. and then then all the LDO outputs are off. EXTEN and LD02 are low all time. Power OK is also low. IPSOUT is OK as it should be. I am using ACIN

[linux-sunxi] [PATCH v2 09/13] ARM: dts: sun8i-a83t: Add RSB controller device node to dtsi

This patch adds a device node for the Reduced Serial Bus (RSB) controller and the defacto pinmux setting to the A83T dtsi. Since there is only one possible pinmux setting for RSB, just set it in the dtsi. Signed-off-by: Vishnu Patekar ---

[linux-sunxi] [PATCH v2 12/13] ARM: dts: sun8i: Add A83T based Sinovoip Bpi-M3 Board

This patch adds support for Sinovoip BPI-M3 A83T based board. It has 2G LPDDR3, UART, ethernet, USB, HDMI, USB Sata, MIPI DSI, mic, AP6212 Wifi, etc on it. It is paired with AXP813 PMIC which is almost same as AXP818. Signed-off-by: Vishnu Patekar ---

[linux-sunxi] [PATCH v2 00/13] Add A83T clk, r_pio, mmc rsb support

Hello, This is v2 of series which adds further support for A83T, mainly adds clock support. Also adds R_PIO, PRCM related clocks, mmc, rsb support. A83T difference in short: R_PIO is slightly different from A23 r_pio. AHB1 has different parents as compared to a31-ahb1, APB1 has different

[linux-sunxi] [PATCH v2 01/13] pinctrl: sunxi: Add A83T R_PIO controller support

The A83T has R_PIO pin controller, it's same as A23, execpt A83T interrupt bit is 6th and A83T has one extra pin PL12. Signed-off-by: Vishnu Patekar Acked-by: Chen-Yu Tsai Acked-by: Rob Herring ---

[linux-sunxi] [PATCH v2 02/13] clk: sunxi: add ahb1 clock for A83T

AHB1 on A83T is similar to ahb1 on A31, except parents are different. clock index 0b1x is PLL6. Signed-off-by: Vishnu Patekar Acked-by: Chen-Yu Tsai Acked-by: Rob Herring --- Documentation/devicetree/bindings/clock/sunxi.txt | 1 +

[linux-sunxi] [PATCH v2 08/13] ARM: dts: sun8i-a83t: Add R_PIO controller node to the dtsi

Now that we have a driver for the R_PIO controller, add the corresponding device node to the dtsi. Signed-off-by: Vishnu Patekar --- arch/arm/boot/dts/sun8i-a83t.dtsi | 12 1 file changed, 12 insertions(+) diff --git a/arch/arm/boot/dts/sun8i-a83t.dtsi

[linux-sunxi] [PATCH v2 04/13] ARM: dts: sun8i-a83t: Add basic clocks and resets

This adds A83T system bus clocks, bus gates, and clock resets. Three ahb reset registers are combined into one node. Signed-off-by: Vishnu Patekar --- arch/arm/boot/dts/sun8i-a83t.dtsi | 114 +- 1 file changed, 112 insertions(+),

[linux-sunxi] [PATCH v2 03/13] clk: sunxi: Add APB1 clock for A83T

APB1 is similar to sun4i-a10-apb0-clk, except different dividers. This adds support for apb1 on A83T. Signed-off-by: Vishnu Patekar Acked-by: Rob Herring --- Documentation/devicetree/bindings/clock/sunxi.txt | 1 + drivers/clk/sunxi/clk-sunxi.c

[linux-sunxi] [PATCH v2 05/13] ARM: dts: sun8i-a83t: add mmc clock nodes

mmc clocks are compatible with that of earlier sun8i socs. This adds mmc0, mmc1, and mmc2 clock nodes for A83T. Signed-off-by: Vishnu Patekar Acked-by: Chen-Yu Tsai --- arch/arm/boot/dts/sun8i-a83t.dtsi | 30 ++ 1 file

[linux-sunxi] [PATCH v2 06/13] ARM: dts: sun8i-a83t: Add mmc controller nodes

A83T mmc is compatible with earliers sunxi socs. This adds mmc0, mmc1, and mmc2 controller nodes for A83T. Signed-off-by: Vishnu Patekar --- arch/arm/boot/dts/sun8i-a83t.dtsi | 57 +++ 1 file changed, 57 insertions(+) diff --git

[linux-sunxi] Re: [PATCH v2 04/13] ARM: dts: sun8i-a83t: Add basic clocks and resets

On Sun, Feb 28, 2016 at 7:18 AM, Vishnu Patekar wrote: > This adds A83T system bus clocks, bus gates, and clock resets. > > Three ahb reset registers are combined into one node. > > Signed-off-by: Vishnu Patekar > --- >

[linux-sunxi] Re: eGalax Driver for A20 (Banana/Orange Pi)

Dňa nedeľa, 13. decembra 2015 17:07:18 UTC+1 jtow...@gmail.com napísal(-a): > Do you have a working build for this for orange pi plus pre compiled I can > download and flash? i am interested in this image too please if you have the image share it with us -- You received this message because

[linux-sunxi] [PATCH v2 11/13] ARM: dts: sun8i: enable mmc for H8Homlet Board.

This enables mmc0. Signed-off-by: Vishnu Patekar Tested-by: LABBE Corentin --- arch/arm/boot/dts/sun8i-a83t-allwinner-h8homlet-v2.dts | 11 +++ 1 file changed, 11 insertions(+) diff --git

[linux-sunxi] [PATCH v2 13/13] ARM: sunxi: Introduce MACH_SUN8I_A83T option

A83T has CPUS clock similar to A80's. currently, a80 cpus clock only compiled for A80. So, Introduce MACH_SUN8I_A83T to compile it for A83T as well. Signed-off-by: Vishnu Patekar --- arch/arm/mach-sunxi/Kconfig | 5 + drivers/clk/sunxi/Makefile | 3 +++ 2 files

[linux-sunxi] [PATCH v2 10/13] ARM: dts: sun8i-a83t: add mmc0 CD pin

A83T Boards BPI-m3 and Allwinner H8Homletv2 boards use PF6 as Card Detect pin., so use PF6 as reference design CD pin in dtsi. Signed-off-by: Vishnu Patekar --- arch/arm/boot/dts/sun8i-a83t.dtsi | 7 +++ 1 file changed, 7 insertions(+) diff --git

[linux-sunxi] [PATCH 1/2] pinctrl: sunxi: Remove non existing irq's

While I was testing irq's on the cubietruck I found a couple of not working irq pins. Further diving into the problem it opened up a mess called "manual". This so called manual (A20 user manual v1.3 dated 2014-10-10) says: Pin overview: Page 233: EINT12 is on pin PC19 mux6. Page

[linux-sunxi] [PATCH 2/2] pinctrl: sunxi: Change mux setting on PI irq pins

While I was testing irq's on the cubietruck I found a couple of not working irq pins. Further diving into the problem it opened up a mess called "manual". This so called manual (A20 user manual v1.3 dated 2014-10-10) says: Pin overview: Page 237: EINT26 is on mux 5. Page 288:

[linux-sunxi] Re: [PATCH v2 02/13] clk: sunxi: add ahb1 clock for A83T

Hi, On Sun, Feb 28, 2016 at 7:18 AM, Vishnu Patekar wrote: > AHB1 on A83T is similar to ahb1 on A31, except parents are different. > clock index 0b1x is PLL6. > > Signed-off-by: Vishnu Patekar > Acked-by: Chen-Yu Tsai >