Hi,
On Tue, Aug 8, 2017 at 9:25 AM, Jonathan Liu wrote:
> The bindings were not updated when the sun5i CCU driver was added in
> commit 5e73761786d6 ("clk: sunxi-ng: Add sun5i CCU driver").
>
> Signed-off-by: Jonathan Liu
Looks good to me. Will wait for the device tree binding maintainers
to ha
The DE2 in Allwinner A64 SoC requires the SRAM C to be claimed to work.
This patchset adds the support of SRAM C in A64 for the sunxi-sram driver.
As the SRAM C controlling bit is a little different with other peripherals'
SRAM controlling bit (inverted), a function value to register value
remapp
When claiming SRAM, if the base is set to an error, it means that the
SRAM controller has been probed, but failed to remap the controller
memory zone. If the base is zero, thus the SRAM controller should be not
probed at all, and it should return -EPROBE_DEFER. However, currently we
returned -EPROB
Allwinner A64's display engine claims the SRAM C section to work.
Add support for the A64 SRAM controller and the SRAM C section of it.
Signed-off-by: Icenowy Zheng
---
drivers/soc/sunxi/sunxi_sram.c | 11 +++
1 file changed, 11 insertions(+)
diff --git a/drivers/soc/sunxi/sunxi_sram.c
The display engine on Allwinner A64 wants to claim the SRAM C section.
Add a SRAM controller compatible for A64, and a SRAM section compatible
for its SRAM C.
Signed-off-by: Icenowy Zheng
---
Documentation/devicetree/bindings/sram/sunxi-sram.txt | 9 +++--
1 file changed, 7 insertions(+), 2
On some Allwinner SoCs, sometimes the value needed to write into the
register to claim SRAM is not equal to the value specified in the
device tree.
We now defines 0 as "CPU" and 1 as "Device", however, for VE SRAM, the
register needs to be written 0x7FFF to claim it to VE, and for
Allwinner A6
On Wed, Aug 9, 2017 at 4:56 PM, Icenowy Zheng wrote:
> When claiming SRAM, if the base is set to an error, it means that the
> SRAM controller has been probed, but failed to remap the controller
> memory zone. If the base is zero, thus the SRAM controller should be not
> probed at all, and it shou
On Tue, Aug 01, 2017 at 09:12:52PM +0800, Icenowy Zheng wrote:
> Allwinner H3 features a "Display Engine 2.0".
>
> Add device tree bindings for the following parts:
> - H3 TCONs
> - H3 Mixers
> - H3 Display engine
>
> Signed-off-by: Icenowy Zheng
> ---
> .../bindings/display/sunxi/sun4i-drm.txt
On Wed, Aug 02, 2017 at 09:06:26PM +0200, Jernej Škrabec wrote:
> Hi,
>
> Dne sreda, 02. avgust 2017 ob 07:02:39 CEST je icen...@aosc.io napisal(a):
> > 在 2017-08-02 12:53，Jernej Škrabec 写道：
> >
> > > Hi Icenowy,
> > >
> > > Dne torek, 01. avgust 2017 ob 15:12:52 CEST je Icenowy Zheng
> > >
> >
sunxi_mmc_clk_set_phase expects the actual card clock rate to be passed
to it. When the internal divider code was reworked in commit 9a639c6073d3
("mmc: sunxi: Support MMC DDR52 transfer mode with new timing mode"),
this requirement was missed, and the module clock rate was passed in
instead. This
Hi,
On Sat, Jul 22, 2017 at 10:28 AM, Icenowy Zheng wrote:
> The Banana Pi M64 board uses the A64 chip's EMAC to provide Ethernet
> link.
>
> Add the ethernet0 alias in the device tree, in order to let U-Boot
> generate a MAC address from the chip's SID.
>
> Signed-off-by: Icenowy Zheng
As ment
于 2017年8月10日 GMT+08:00 上午11:56:02, Chen-Yu Tsai 写到:
>Hi,
>
>On Sat, Jul 22, 2017 at 10:28 AM, Icenowy Zheng
>wrote:
>> The Banana Pi M64 board uses the A64 chip's EMAC to provide Ethernet
>> link.
>>
>> Add the ethernet0 alias in the device tree, in order to let U-Boot
>> generate a MAC address
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