Allwinner PWM support need for ARM64 Allwinner SoC's
which used pwms, builds it as module.
Signed-off-by: Jagan Teki
---
Changes for v6:
- none
Changes for v5:
- new patch
arch/arm64/configs/defconfig | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm64/configs/defconfig
This patch add support for Bananapi S070WV20-CT16 DSI panel to
BPI-M64 board.
DSI panel connected via board DSI port with,
- DC1SW as AVDD supply
- DCDC1 as DVDD supply
- PD6 gpio for reset pin
- PD5 gpio for backlight enable pin
- PD7 gpio for backlight vdd supply
Signed-off-by: Jagan Teki
---
The MIPI DSI PHY HDMI controller on Allwinner A64 is similar
on the one on A31.
Add A64 compatible and append A31 compatible as fallback.
Signed-off-by: Jagan Teki
Reviewed-by: Rob Herring
---
Documentation/devicetree/bindings/display/sunxi/sun6i-dsi.txt | 1 +
1 file changed, 1 insertion(+)
Techstar TS8550B MIPI DSI panel is 480x854, 2-lane MIPI DSI
LCD panel. Add dt-bingings for it.
Signed-off-by: Jagan Teki
Reviewed-by: Rob Herring
---
.../display/panel/techstar,ts8550b.txt| 22 +++
1 file changed, 22 insertions(+)
create mode 100644
Amarula A64-Relic board by default bound with Techstar TS8550B
MIPI-DSI panel, add support for it.
DSI panel connected via board DSI port with,
- DC1SW as AVDD supply
- DCDC2 as DVDD supply
- DCDC1 as VCC-DSI supply
- PD24 gpio for reset pin
- PD23 gpio for backlight enable pin
Signed-off-by:
Techstar TS8550B MIPI DSI panel is 480x854, 2-lane MIPI DSI
LCD panel. Add panel driver for it.
Signed-off-by: Jagan Teki
---
MAINTAINERS | 6 +
drivers/gpu/drm/panel/Kconfig | 9 +
drivers/gpu/drm/panel/Makefile| 1 +
The A64 has a MIPI-DSI block which is similar to A31
without mod clock.
So, add dsi node with A64 compatible, dphy node with
A31 compatible and finally connect dsi to tcon0 to
make proper DSI pipeline.
Signed-off-by: Jagan Teki
---
arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi | 45
Manual noted to use PLL_MIPI rate 500MHz to 1.4GHz,
but lowering the min rate by 300MHz can result proper
working nkms divider with the help of desired dclock
rate from panel driver.
Signed-off-by: Jagan Teki
Acked-by: Stephen Boyd
---
drivers/clk/sunxi-ng/ccu-sun50i-a64.c | 2 ++
1 file
Bananapi S070WV20-CT16 ICN6211 is 800x480, 4-lane MIPI-DSI to RGB bridge
panel which can be used to connect via DSI port on BPI-M64 board,
so add a driver for it.
The same panel PCB comes with parallel RBG which is supported via
panel-simple driver with "bananapi,s070wv20-ct16" compatible.
BSP
Most of the Allwinner MIPI DSI controllers are supply with
VCC-DSI pin. which need to supply for some of the boards to
trigger the power.
So, document the supply property so-that the required board
can eable it via device tree.
Signed-off-by: Jagan Teki
---
Mod clock is not mandatory for all Allwinner MIPI DSI
controllers, it is connected as CLK_DSI_SCLK for A31
and not available in A64.
So add has_mod_clk quirk and process the clk accordingly.
Signed-off-by: Jagan Teki
---
drivers/gpu/drm/sun4i/sun6i_mipi_dsi.c | 39 ++
TCON DRQ set bits for non-burst DSI mode can computed via
horizontal front porch instead of front porch + sync timings.
BSP code form BPI-M64-bsp is computing TCON DRQ set bits
for non-burts as (from linux-sunxi/
drivers/video/sunxi/disp2/disp/de/lowlevel_sun50iw1/de_dsi.c)
=> panel->lcd_ht -
Bananapi S070WV20-CT16 ICN6211 is 800x480, 4-lane MIPI-DSI to RGB
bridge panel, which is available on same PCB with 24-bit RGB interface.
So, this patch adds DSI specific binding details on existing
dt-bindings file.
Signed-off-by: Jagan Teki
Reviewed-by: Rob Herring
---
Current driver is calculating hbp maximum value by subtracting
hsync_start with hdisplay which is front porch value, but the
hbp refers to back porch.
Back porch value is calculating by subtracting htotal with
hsync_end as per drm_mode timings, and BSP code from BPI-M64-bsp
is eventually
hblk is adding line with all porch timing values, or timings
values from htotal without sync time.
Current driver is subtracting htotal with hsa, but the hsa
is bounded with packet overhead. For real hblk calculation
needed by subtracting htotal with back and front porch values
and BSP code
Unlike hblk, the vblk timings should follow an equation to compute
the desired value for lane 4 devices and rest of devices it would be 0.
BSP code from BPI-M64-bsp is computing vblk as for 4-lane devices
(from linux-sunxi
drivers/video/sunxi/disp2/disp/de/lowlevel_sun50iw1/de_dsi.c)
tmp =
Some boards have VCC-DSI pin connected to voltage regulator which may
not be turned on by default.
Add support for such boards by adding voltage regulator handling code to
MIPI DSI driver.
Signed-off-by: Jagan Teki
---
drivers/gpu/drm/sun4i/sun6i_mipi_dsi.c | 14 ++
Current driver is calculating hfp maximum value by subtracting
htotal with hsync_end which is front back value, but the
hpp refers to front porch.
Front porch value is calculating by subtracting hsync_start with
hdisplay as per drm_mode timings, and BSP code from BPI-M64-bsp
is eventually
Add 10 bytes packet overhead for hblk where blank is set using
a blanking packet like (4 bytes + 4 bytes + payload + 2 bytes)
This is according to BSP code from BPI-M64-bsp (from linux-sunxi/
drivers/video/sunxi/disp2/disp/de/lowlevel_sun50iw1/de_dsi.c)
dsi_hblk =
On Tue, Nov 13, 2018 at 05:45:35PM +0530, Jagan Teki wrote:
> Allwinner PWM support need for ARM64 Allwinner SoC's
> which used pwms, builds it as module.
>
> Signed-off-by: Jagan Teki
Applied all 4 patches, thanks!
Maxime
--
Maxime Ripard, Bootlin
Embedded Linux and Kernel engineering
On Tue, Nov 13, 2018 at 04:46:10PM +0530, Jagan Teki wrote:
> Some NKM PLLs, frequency can be set above PLL working range.
>
> Add a constraint for maximum supported rate. This way, drivers can
> specify which is maximum allowed rate for PLL.
>
> Signed-off-by: Jagan Teki
> Acked-by: Stephen
Hi Yong,
On Tue, Oct 30, 2018 at 04:09:48PM +0800, Yong Deng wrote:
> I can't make v4l2-compliance always happy.
> The V3s CSI support many pixformats. But they are not always available.
> It's dependent on the input bus format (MEDIA_BUS_FMT_*).
> Example:
> V4L2_PIX_FMT_SBGGR8:
Allwinner DesignWare HDMI is needed for HDMI support
in ARM64 Allwinner SoC's, build it as module.
Signed-off-by: Jagan Teki
---
Changes for v6:
- none
Changes for v5:
- Enable it on defconfig
Changes for v4:
- none
Changes for v3:
- skip SUN8I enablement, since it built statically for arm32
Allwinner Display Engine 2.0 Mixer is need for ARM64
Allwinner SoC's, build it as module.
Signed-off-by: Jagan Teki
---
Changes for v6:
- none
Changes for v5:
- Enable it on defconfig
Changes for v4, v3:
- none
Changes for v2:
- Enable for SUN8I
arch/arm64/configs/defconfig | 1 +
1 file
Allwinner SoC like SUN8I and SUN50I has DE2 CCU so enable them
as default.
Signed-off-by: Jagan Teki
---
Changes for v6:
- droped "depends on" since the CCU select based on MACH defined.
Changes for v5:
- remove DRM dependency
Changes for v4, v3:
- none
Changes for v2:
- Enable for MACH_SUN8I
On Tue, Nov 13, 2018 at 04:46:08PM +0530, Jagan Teki wrote:
> DSI DPHY gate bit on MIPI DSI clock register is bit 15
> not bit 30.
>
> Signed-off-by: Jagan Teki
> Acked-by: Stephen Boyd
Applied, thanks!
Maxime
--
Maxime Ripard, Bootlin
Embedded Linux and Kernel engineering
On Tue, Nov 13, 2018 at 05:30:54PM +0530, Jagan Teki wrote:
> Add support for Allwinner A64 has Mali-400MP2.
>
> All interrupt lines are mentioned in the manual so used the same.
> Used 408MHz as assigned clock rate used by BSP, so used the same as
> well.
You're not using that frequency
The MIPI DSI controller on Allwinner A64 is similar to
Allwinner A31 without support of DSI mod clock.
Signed-off-by: Jagan Teki
Reviewed-by: Rob Herring
---
Documentation/devicetree/bindings/display/sunxi/sun6i-dsi.txt | 1 +
1 file changed, 1 insertion(+)
diff --git
Some NKM PLLs, frequency can be set above PLL working range.
Add a constraint for maximum supported rate. This way, drivers can
specify which is maximum allowed rate for PLL.
Signed-off-by: Jagan Teki
Acked-by: Stephen Boyd
---
drivers/clk/sunxi-ng/ccu_nkm.c | 3 +++
Video start delay can be computed by subtracting total vertical
timing with front porch timing and with adding 1 delay line for TCON.
BSP code form BPI-M64-bsp is computing video start delay as
(from linux-sunxi/
drivers/video/sunxi/disp2/disp/de/lowlevel_sun50iw1/de_dsi.c)
u32 vfp =
The horizontal and vertical back porch calculation in BSP
code is simply following the Linux drm comment diagram, in
include/drm/drm_modes.h which is
[hv]back porch = [hv]total - [hv]sync_end
BSP code form BPI-M64-bsp is calculating vertical back porch as
(from
Short transfer write support for DCS and Generic transfer types
share similar way to process command sequence in DSI block so
add generic write 2 param transfer type macro so-that the panels
which are requesting similar transfer type may process properly.
Signed-off-by: Jagan Teki
---
The MIPI DSI controller on Allwinner A64 is similar to
Allwinner A31 without support of DSI mod clock(CLK_DSI_SCLK)
So, alter has_mod_clk bool via driver data for respective
SoC's compatible.
Signed-off-by: Jagan Teki
---
drivers/gpu/drm/sun4i/sun6i_mipi_dsi.c | 7 +++
1 file changed, 7
Some NKM PLLs doesn't work well when their output clock rate is set below
certain rate.
So, add support for minimal rate for relevant PLLs.
Signed-off-by: Jagan Teki
Acked-by: Stephen Boyd
---
drivers/clk/sunxi-ng/ccu_nkm.c | 3 +++
drivers/clk/sunxi-ng/ccu_nkm.h | 1 +
2 files changed, 4
DSI DPHY gate bit on MIPI DSI clock register is bit 15
not bit 30.
Signed-off-by: Jagan Teki
Acked-by: Stephen Boyd
---
drivers/clk/sunxi-ng/ccu-sun50i-a64.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/clk/sunxi-ng/ccu-sun50i-a64.c
This series fixed the issues related to work DSI on 2-lane panel
which is reported on previous version[1].
This supposed to be a clean series, where it support Allwinner A64 MIPI-DSI
support for 4-lane, 2-lane DSI panels.
This series fixed all previous series comments along with checkpatch
On Tue, Nov 13, 2018 at 05:30:53PM +0530, Jagan Teki wrote:
> Allwinner A64 has Mali-400MP2, so document the relevant compatible
> as "allwinner,sun50i-a64-mali"
>
> Signed-off-by: Jagan Teki
> ---
> Changes for v2:
> - New patch, separated from previous version patch.
>
>
Add support for Allwinner A64 has Mali-400MP2.
All interrupt lines are mentioned in the manual so used the same.
Used 408MHz as assigned clock rate used by BSP, so used the same as
well.
Signed-off-by: Jagan Teki
---
Changes for v2:
- Drop assigned clock properties
- Separate dt-bindings as
Allwinner A64 has Mali-400MP2, so document the relevant compatible
as "allwinner,sun50i-a64-mali"
Signed-off-by: Jagan Teki
---
Changes for v2:
- New patch, separated from previous version patch.
Documentation/devicetree/bindings/gpu/arm,mali-utgard.txt | 1 +
1 file changed, 1 insertion(+)
On Tue, 13 Nov 2018 16:46:32 +0530
Jagan Teki wrote:
Hi,
> This patch add support for Bananapi S070WV20-CT16 DSI panel to
> BPI-M64 board.
>
> DSI panel connected via board DSI port with,
> - DC1SW as AVDD supply
Are you sure of that? I don't see anything in the schematic to support
this. The
On Tue, 13 Nov 2018 16:46:33 +0530
Jagan Teki wrote:
Hi,
I couldn't find a schematic for this board, but some things in here
look inconsistent:
> Amarula A64-Relic board by default bound with Techstar TS8550B
> MIPI-DSI panel, add support for it.
>
> DSI panel connected via board DSI port
Allwinner A64 has Mali-400MP2, so document the relevant compatible
as "allwinner,sun50i-a64-mali" along with reset line.
Signed-off-by: Jagan Teki
---
Changes for v3:
- document reset line
Changes for v2:
- New patch, separated from previous version patch.
Add support for Allwinner A64 has Mali-400MP2.
All interrupt lines are mentioned in the manual so used the same.
Signed-off-by: Jagan Teki
---
Changes for v3:
- Clean commit message
Changes for v2:
- Drop assigned clock properties
- Separate dt-bindings as separate patch.
在 2018-10-18四的 08:58 -0500，Rob Herring写道：
> On Sat, Oct 13, 2018 at 9:42 PM Icenowy Zheng
> wrote:
> >
> > 在 2018-10-05五的 15:58 -0500，Rob Herring写道：
> > > On Thu, Oct 04, 2018 at 08:28:52PM +0800, Icenowy Zheng wrote:
> > > > The new Allwinner H6 SoC contains a USB3 PHY that is wired to
> > > >
On Tue, Nov 13, 2018 at 7:37 AM Rob Herring wrote:
>
> On Wed, Nov 07, 2018 at 06:12:54PM +0800, Chen-Yu Tsai wrote:
> > The Broadcom Bluetooth controllers can take up to two external clocks:
> > an external frequency reference, substituting the main crystal, and a
> > LPO clock at 32.768 kHz
在 2018-10-04四的 20:28 +0800，Icenowy Zheng写道：
> Allwinner H6 SoC contains a USB3 PHY (with USB2 DP/DM lines also
> controlled).
>
> Add a driver for it.
>
> The register operations in this driver is mainly extracted from the
> BSP
> USB3 driver.
>
> Signed-off-by: Icenowy Zheng
> Reviewed-by:
On Tue, Nov 13, 2018 at 5:52 PM Andre Przywara wrote:
>
> On Tue, 13 Nov 2018 16:46:32 +0530
> Jagan Teki wrote:
>
> Hi,
>
> > This patch add support for Bananapi S070WV20-CT16 DSI panel to
> > BPI-M64 board.
> >
> > DSI panel connected via board DSI port with,
> > - DC1SW as AVDD supply
>
> Are
On Wed, Nov 14, 2018 at 2:31 PM Jagan Teki wrote:
>
> On Tue, Nov 13, 2018 at 5:52 PM Andre Przywara wrote:
> >
> > On Tue, 13 Nov 2018 16:46:32 +0530
> > Jagan Teki wrote:
> >
> > Hi,
> >
> > > This patch add support for Bananapi S070WV20-CT16 DSI panel to
> > > BPI-M64 board.
> > >
> > > DSI
On Thu, Nov 8, 2018 at 4:24 PM Maxime Ripard wrote:
>
> On Wed, Nov 07, 2018 at 06:13:07PM +0800, Chen-Yu Tsai wrote:
> > This patch adds the Bluetooth node, and the underlying UART node if it's
> > missing, to the board device tree file for several boards. The LPO clock
> > is also added to the
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