While comparing clocks between the H6 and H616, some of the M factor
ranges were found to be wrong: the manual says they are only covering
two bits [1:0], but our code had "5" in the number-of-bits field.
By writing 0xff into that register in U-Boot and via FEL, it could be
confirmed that bits
From: Yangtao Li
Add binding for A100's and H616's mmc and emmc controller.
Signed-off-by: Yangtao Li
Signed-off-by: Andre Przywara
Acked-by: Rob Herring
---
.../devicetree/bindings/mmc/allwinner,sun4i-a10-mmc.yaml | 8
1 file changed, 8 insertions(+)
diff --git
Hi,
an update from the v2 in December, to add support for the Allwinner H616
SoC. This time it's based on sunxi/for-next, which is based on 5.11-rc1.
The A100 watchdog binding patch is already merged, so omitted,
and Ulf has already queued the two MMC patch to his next branch. I am
still
From: Yangtao Li
This patch adds support for A100 MMC controller, which use word address
for internal dma.
Signed-off-by: Yangtao Li
Signed-off-by: Andre Przywara
---
drivers/mmc/host/sunxi-mmc.c | 28 +---
1 file changed, 25 insertions(+), 3 deletions(-)
diff --git
A new SoC, a new compatible string.
Also we were too miserly with just allowing seven interrupt banks.
Signed-off-by: Andre Przywara
---
.../pinctrl/allwinner,sun4i-a10-pinctrl.yaml| 17 +++--
1 file changed, 15 insertions(+), 2 deletions(-)
diff --git
On 1/18/21 12:00 AM, Samuel Holland wrote:
> This series cleans up some dead code in the sunxi-cir driver and adds
> system power management hooks.
>
> ---
> Changes from v1:
> - Unregister the RC device first thing in sunxi_ir_remove() [3]
I forgot to add:
Acked-by: Maxime Ripard
from v1.
The Allwinner H616 adds a second EMAC clock register at offset 0x34, for
controlling the second EMAC in this chip.
Allow to extend the regmap in this case, to cover more than the current
4 bytes exported.
Signed-off-by: Andre Przywara
---
drivers/soc/sunxi/sunxi_sram.c | 31
Currently the AXP chip requires to have its IRQ line connected to some
interrupt controller, and will fail probing when this is not the case.
On a new Allwinner SoC (H616) there is no NMI pin anymore, so the
interrupt functionality of the AXP chip is simply not available.
Check whether the DT
While the clocks are fairly similar to the H6, many differ in tiny
details, so a separate clock driver seems indicated.
Derived from the H6 clock driver, and adjusted according to the manual.
Signed-off-by: Andre Przywara
---
drivers/clk/sunxi-ng/Kconfig|5 +
The Allwinner H616 SoC has two EMAC controllers, with the second one
being tied to the internal PHY, but also using a separate EMAC clock
register.
To tell the driver about which clock register to use, we add a parameter
to our syscon phandle. The driver will use this value as an index into
the
The H616 adds a second EMAC clock register. We don't know about the
exact SRAM properties yet, so this gets omitted for now.
Signed-off-by: Andre Przywara
Acked-by: Rob Herring
---
.../bindings/sram/allwinner,sun4i-a10-system-control.yaml| 1 +
1 file changed, 1 insertion(+)
diff
Add simple "allwinner,sun50i-h616-xxx" compatible names to existing
bindings, and pair them with an existing fallback compatible string,
as the devices are compatible.
This covers I2C, infrared, RTC and SPI.
Use enums to group all compatible devices together.
Signed-off-by: Andre Przywara
This (relatively) new SoC is similar to the H6, but drops the (broken)
PCIe support and the USB 3.0 controller. It also gets the management
controller removed, which in turn removes *some*, but not all of the
devices formerly dedicated to the ARISC (CPUS).
There does not seem to be an extra
Signed-off-by: Andre Przywara
Acked-by: Rob Herring
---
Documentation/devicetree/bindings/arm/sunxi.yaml | 5 +
1 file changed, 5 insertions(+)
diff --git a/Documentation/devicetree/bindings/arm/sunxi.yaml
b/Documentation/devicetree/bindings/arm/sunxi.yaml
index 7ea4d9645e93..6a2fa84bb785
The OrangePi Zero 2 is a development board with the new H616 SoC.
It features the usual connectors used on those small boards, and comes
with the AXP305, which seems to be compatible with the AXP805.
For more details see: http://linux-sunxi.org/Xunlong_Orange_Pi_Zero2
Signed-off-by: Andre
The USB PHY used in the Allwinner H616 SoC inherits some traits from its
various predecessors: it has four full PHYs like the H3, needs some
extra bits to be set like the H6, and clears a different bit in the
PMU_UNK1 register like the A100.
Name all those properties in a new config struct and
Port A is used for an internal connection to some analogue circuitry
which looks like an AC200 IP (as in the H6), though this is not
mentioned in the manual.
Signed-off-by: Andre Przywara
---
drivers/pinctrl/sunxi/Kconfig | 5 +
drivers/pinctrl/sunxi/Makefile | 1
There are only two pins left now, used to connect to the PMIC via I2C.
Signed-off-by: Andre Przywara
Acked-by: Maxime Ripard
Reviewed-by: Jernej Skrabec
---
drivers/pinctrl/sunxi/Kconfig | 5 ++
drivers/pinctrl/sunxi/Makefile| 1 +
Signed-off-by: Andre Przywara
Acked-by: Rob Herring
---
.../devicetree/bindings/clock/allwinner,sun4i-a10-ccu.yaml | 2 ++
1 file changed, 2 insertions(+)
diff --git
a/Documentation/devicetree/bindings/clock/allwinner,sun4i-a10-ccu.yaml
The clocks itself are identical to the H6 R-CCU, it's just that the H616
has not all of them implemented (or connected).
Signed-off-by: Andre Przywara
---
drivers/clk/sunxi-ng/Kconfig | 2 +-
drivers/clk/sunxi-ng/ccu-sun50i-h6-r.c | 48 ++
2 files changed, 49
As Icenowy pointed out, newer manuals (starting with H6) actually
document the register block at offset 0x800 as "HCI controller and PHY
interface", also describe the bits in our "PMU_UNK1" register.
Let's put proper names to those "unknown" variables and symbols.
While we are at it, generalise
Use enums to group all compatible devices together on the way.
Signed-off-by: Andre Przywara
Acked-by: Rob Herring
---
.../bindings/watchdog/allwinner,sun4i-a10-wdt.yaml | 12 +---
1 file changed, 5 insertions(+), 7 deletions(-)
diff --git
The H616 MUSB peripheral is presumably compatible to the H3 one.
Signed-off-by: Andre Przywara
---
.../devicetree/bindings/usb/allwinner,sun4i-a10-musb.yaml | 3 +++
1 file changed, 3 insertions(+)
diff --git
a/Documentation/devicetree/bindings/usb/allwinner,sun4i-a10-musb.yaml
The H616 has four PHYs as the H3, along with their respective clock
gates and resets, so the property description is identical.
However the PHYs itself need some special bits, so we need a new
compatible string for it.
Signed-off-by: Andre Przywara
---
On 1/17/21 8:08 PM, Andre Przywara wrote:
> This (relatively) new SoC is similar to the H6, but drops the (broken)
> PCIe support and the USB 3.0 controller. It also gets the management
> controller removed, which in turn removes *some*, but not all of the
> devices formerly dedicated to the ARISC
On 1/17/21 8:08 PM, Andre Przywara wrote:
> Currently the AXP chip requires to have its IRQ line connected to some
> interrupt controller, and will fail probing when this is not the case.
>
> On a new Allwinner SoC (H616) there is no NMI pin anymore, so the
> interrupt functionality of the AXP
On 1/17/21 8:08 PM, Andre Przywara wrote:
> Add simple "allwinner,sun50i-h616-xxx" compatible names to existing
> bindings, and pair them with an existing fallback compatible string,
> as the devices are compatible.
> This covers I2C, infrared, RTC and SPI.
>
> Use enums to group all compatible
The register writes during driver removal occur after the device is
already put back in reset, so they never had any effect.
Signed-off-by: Samuel Holland
---
drivers/media/rc/sunxi-cir.c | 10 --
1 file changed, 10 deletions(-)
diff --git a/drivers/media/rc/sunxi-cir.c
This series cleans up some dead code in the sunxi-cir driver and adds
system power management hooks.
---
Changes from v1:
- Unregister the RC device first thing in sunxi_ir_remove() [3]
Samuel Holland (4):
media: sunxi-cir: Clean up dead register writes
media: sunxi-cir: Remove unnecessary
In preparation for adding suspend/resume hooks, factor out the hardware
initialization from the driver probe/remove functions.
The timeout programmed during init is taken from the `struct rc_dev` so
it is maintained across an exit/init cycle.
This resolves some trivial issues with the probe
Only one register, SUNXI_IR_CIR_REG, is accessed from outside the
interrupt handler, and that register is not accessed from inside it.
As there is no overlap between different contexts, no lock is needed.
Signed-off-by: Samuel Holland
---
drivers/media/rc/sunxi-cir.c | 10 --
1 file
To save power, gate/reset the hardware block while the system is
asleep or powered off.
Signed-off-by: Samuel Holland
---
drivers/media/rc/sunxi-cir.c | 21 +
1 file changed, 21 insertions(+)
diff --git a/drivers/media/rc/sunxi-cir.c b/drivers/media/rc/sunxi-cir.c
index
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