,
+};
+module_platform_driver(sunxi_mmc_driver);
+
+MODULE_DESCRIPTION(Allwinner's SD/MMC Card Controller Driver);
+MODULE_LICENSE(GPL v2);
+MODULE_AUTHOR(David Lanzendörfer david.lanzendoer...@o2s.ch);
+MODULE_ALIAS(platform:sunxi-mmc);
--
1.9.0
Kind regards
Ulf Hansson
--
You received
[snip]
On 05/05/2014 02:41 PM, Ulf Hansson wrote:
+struct sunxi_mmc_host {
+ struct mmc_host *mmc;
+ struct regulator *vmmc;
Instead of having a specific regulator for this driver, please use the
mmc_regulator_get_supply API.
We cannot use mmc_regulator_get_supply because
--;
+ }
+
+ clk_sunxi_mmc_phase_control(hw, sclk_dly, oclk_dly);
+
+ return sunxi_mmc_oclk_onoff(host, 1);
+}
+
[snip]
Besides the above, I think this looks good!
Kind regards
Ulf Hansson
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On 12 May 2014 13:20, Hans de Goede hdego...@redhat.com wrote:
Hi,
On 05/12/2014 11:15 AM, Ulf Hansson wrote:
On 11 May 2014 09:46, Hans de Goede hdego...@redhat.com wrote:
From: David Lanzendörfer david.lanzendoer...@o2s.ch
The Allwinner sunxi mmc host uses dma in bus-master mode using
will include this in the next PR I send to Chris, I will also take
the liberty to fixup the commit msg as pointed out by Arend.
Kind regards
Ulf Hansson
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On 12 May 2014 14:04, Hans de Goede hdego...@redhat.com wrote:
__clk_get_hw is supposed to be used by clk providers, not clk consumers.
Signed-off-by: Hans de Goede hdego...@redhat.com
Reviewed-by: Ulf Hansson ulf.hans...@linaro.org
---
drivers/clk/sunxi/clk-sunxi.c | 3 ++-
include/linux
with a decision on how-to
represent non probable info for sdio devices in device nodes. So do you
have any other remarks other then that the slot subnode should be dropped ?
And if not can you please review and ack (*) v3 of this patch-set once
I've send it?
Chris Ball and Ulf Hansson, what is your
On 2 June 2014 10:38, Jaehoon Chung jh80.ch...@samsung.com wrote:
On 06/02/2014 05:29 PM, Ulf Hansson wrote:
On 1 June 2014 11:23, Hans de Goede hdego...@redhat.com wrote:
Hi,
On 05/31/2014 10:13 PM, Olof Johansson wrote:
On Sat, May 31, 2014 at 12:03 PM, Hans de Goede hdego...@redhat.com
On 2 June 2014 10:46, Jaehoon Chung jh80.ch...@samsung.com wrote:
On 06/02/2014 05:38 PM, Jaehoon Chung wrote:
On 06/02/2014 05:29 PM, Ulf Hansson wrote:
On 1 June 2014 11:23, Hans de Goede hdego...@redhat.com wrote:
Hi,
On 05/31/2014 10:13 PM, Olof Johansson wrote:
On Sat, May 31, 2014
On 3 June 2014 03:50, Jaehoon Chung jh80.ch...@samsung.com wrote:
+Suegnwon Jeon
On 06/02/2014 05:48 PM, Ulf Hansson wrote:
On 2 June 2014 10:38, Jaehoon Chung jh80.ch...@samsung.com wrote:
On 06/02/2014 05:29 PM, Ulf Hansson wrote:
On 1 June 2014 11:23, Hans de Goede hdego...@redhat.com
On 30 June 2014 at 11:07, Hans de Goede hdego...@redhat.com wrote:
Hi All,
Here is a resend of 3 of my submission of Sascha Hauer's
mmc: Add SDIO function devicetree subnode parsing patch.
Can we please get some movement on these patches, either a review specifying
why this cannot go
On 29 March 2015 at 20:09, Hans de Goede hdego...@redhat.com wrote:
The eMMC on a tablet I've will stop working / communicating as soon as
the kernel executes:
mmc_switch(card, EXT_CSD_CMD_SET_NORMAL,
EXT_CSD_HPI_MGMT, 1,
On 12 August 2015 at 16:49, Hans de Goede hdego...@redhat.com wrote:
Hi,
On 08/12/2015 03:29 PM, Michal Suchanek wrote:
The 250ms timeout is too short.
On my system enabling the oclk takes under 50ms and disabling slightly
over 100ms when idle. Under load disabling the clock can take over
On 23 September 2015 at 22:06, Hans de Goede wrote:
> In recent allwinner kernel sources the mmc clk-delay settings have been
> slightly tweaked, and for sun9i they are completely different then what
> we are using.
>
> This commit brings us in sync with what allwinner does,
On 21 January 2016 at 06:26, Chen-Yu Tsai wrote:
> Allwinner's mmc controller supports signal voltage switching. This is
> supported in code in Allwinner's kernel. However, publicly available
> boards all tie it to a fixed 3.0/3.3V regulator, with options to tie
> it to 1.8V for
On 21 January 2016 at 06:26, Chen-Yu Tsai wrote:
> sunxi_mmc_init_host() originated from Allwinner kernel sources. The
> magic numbers written to various registers was never documented.
>
> Add comments for values found in Allwinner user manuals.
>
> Signed-off-by: Chen-Yu Tsai
On 21 January 2016 at 06:26, Chen-Yu Tsai wrote:
> eMMC chips require 2 power supplies, vmmc for internal logic, and vqmmc
> for driving output buffers. vqmmc also controls signaling voltage. Most
> boards we've seen use the same regulator for both, nevertheless the 2
> have
On 21 January 2016 at 06:26, Chen-Yu Tsai wrote:
> Let .set_ios() fail if mmc_regulator_set_ocr() fails to enable and set a
> proper voltage for vmmc.
>
> Signed-off-by: Chen-Yu Tsai
Thanks, applied for next!
Kind regards
Uffe
> ---
>
On 29 January 2016 at 18:21, Chen-Yu Tsai wrote:
> Hi everyone,
>
> This was "mmc: sunxi: Support vqmmc regulator and eMMC DDR modes". vqmmc
> support and DT patches were merged even though it was an RFC series, to
> my suprise.
>
> These are the remaining patches that add eMMC
On 13 August 2016 at 18:01, Jean-Francois Moine wrote:
> clk_round_rate() may return an error. Check it.
>
> Signed-off-by: Jean-Francois Moine
> Acked-by: Maxime Ripard
Please re-spins this as it doesn't apply cleanly due to
On 23 August 2016 at 10:51, Jean-Francois Moine wrote:
> clk_round_rate() may return an error. Check it.
>
> Signed-off-by: Jean-Francois Moine
> Acked-by: Maxime Ripard
Thanks, applied for next!
For some reason this patch
On 16 March 2017 at 14:29, Icenowy Zheng wrote:
> The controller's errors are usually normal (for example, for MMC or SDIO
> cards, some errors are expected to happen; and for boards without a
> dedicated card detect pin the error info will even flood console and
> hide other
On 26 July 2017 at 21:45, Maxime Ripard
wrote:
> On Wed, Jul 26, 2017 at 10:09:41PM +0800, Chen-Yu Tsai wrote:
>> On Mon, Jul 24, 2017 at 9:58 PM, Chen-Yu Tsai wrote:
>> > Hi everyone,
>> >
>> > This is v3 of my MMC controller support series.
>> >
+stable
On 14 July 2017 at 08:42, Chen-Yu Tsai wrote:
> The register for the "new timing mode" also has bit fields for setting
> output and sample timing phases. According to comments in Allwinner's
> BSP kernel, the default values are good enough.
>
> Keep the default values
On 14 July 2017 at 08:42, Chen-Yu Tsai wrote:
> The register for the "new timing mode" also has bit fields for setting
> output and sample timing phases. According to comments in Allwinner's
> BSP kernel, the default values are good enough.
>
> Keep the default values already in
On 14 July 2017 at 11:40, Chen-Yu Tsai <w...@csie.org> wrote:
> On Fri, Jul 14, 2017 at 5:26 PM, Ulf Hansson <ulf.hans...@linaro.org> wrote:
>> On 14 July 2017 at 08:42, Chen-Yu Tsai <w...@csie.org> wrote:
>>> On the SoCs that introduced the new timing mode f
On 8 August 2017 at 09:09, Icenowy Zheng wrote:
> The A83T MMC support code introduces the timings mode switch, however
> such a switch doesn't exist on new SoCs with only new timings mode.
>
> Only execute the switch if the SoC really have the timings mode switch,
> to fix the
On 8 August 2017 at 09:02, Chen-Yu Tsai wrote:
> Some SoCs do not support clk delays for MMC in the clock control unit.
> These include the old controllers in A10/A10s/A13/R8, and the new eMMC
> controller in A64. The config structure for these controllers do not
> specify
On 3 August 2017 at 13:25, Chen-Yu Tsai <w...@csie.org> wrote:
> On Thu, Aug 3, 2017 at 7:19 PM, Ulf Hansson <ulf.hans...@linaro.org> wrote:
>> On 26 July 2017 at 21:45, Maxime Ripard
>> <maxime.rip...@free-electrons.com> wrote:
>>> On Wed, Jul 26, 20
On 10 August 2017 at 05:29, Chen-Yu Tsai wrote:
> sunxi_mmc_clk_set_phase expects the actual card clock rate to be passed
> to it. When the internal divider code was reworked in commit 9a639c6073d3
> ("mmc: sunxi: Support MMC DDR52 transfer mode with new timing mode"),
> this
On 26 April 2018 at 16:07, Icenowy Zheng wrote:
> The new Allwinner H6 SoC have 3 MMC controllers. The first and second
> ones are similar to the ones on A64, but the third one adds EMCE
> (Embedded Crypto Engine) support which does hardware transparent crypto
> on the eMMC.
>
>
On Tue, 5 Feb 2019 at 16:42, Chen-Yu Tsai wrote:
>
> Some H5 boards seem to not have proper trace lengths for eMMC to be able
> to use the default setting for the delay chains under HS-DDR mode. These
> include the Bananapi M2+ H5 and NanoPi NEO Core2. However the Libre
> Computer ALL-H3-CC-H5
On Tue, 5 Feb 2019 at 16:42, Chen-Yu Tsai wrote:
>
> The MMC device tree bindings include properties used to signal various
> signalling speed modes. Until now the sunxi driver was accepting them
> without any further filtering, while the sunxi device trees were not
> actually using them.
>
>
On Wed, 28 Aug 2019 at 12:52, Alejandro González
wrote:
>
> El 27/8/19 a las 15:24, Ulf Hansson escribió:> Assuming this should go stable
> as well? Perhaps you can find a
> > relevant commit that we can put as a fixes tag as well?
> >
> > Kind regards
> > Uf
On Fri, 11 Dec 2020 at 02:20, Andre Przywara wrote:
>
> From: Yangtao Li
>
> Add binding for A100's and H616's mmc and emmc controller.
>
> Signed-off-by: Yangtao Li
> Signed-off-by: Andre Przywara
Applied for next to my mmc tree, thanks!
Kind regards
Uffe
> ---
>
On Fri, 11 Dec 2020 at 02:20, Andre Przywara wrote:
>
> From: Yangtao Li
>
> This patch adds support for A100 MMC controller, which use word address
> for internal dma.
>
> Signed-off-by: Yangtao Li
> Signed-off-by: Andre Przywara
Applied for next to my mmc tree, thanks!
Kind regards
Uffe
L schema.
>
> Some of these properties were already described in the MMC controller
> binding, even though they are not generic and do not apply to any
> device, so we took the occasion to fix this.
>
> Cc: linux-...@vger.kernel.org
> Cc: Ulf Hansson
> Signed-off-by: Maxime Ripard
>
Q
bindings/mmc/mmc-card.yaml
> > b/Documentation/devicetree/bindings/mmc/mmc-card.yaml
> > new file mode 100644
> > index ..aefdd8748b72
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/mmc/mmc-card.yaml
> > @@ -0,0 +1,48 @@
> > +
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