On Sat, Feb 03, 2018 at 11:49:40PM +0800, Icenowy Zheng wrote:
> The Allwinner H6 SoC has a CCU which has been largely rearranged.
>
> Add support for it in the sunxi-ng CCU framework.
>
> Signed-off-by: Icenowy Zheng
> ---
> Changes in v2:
> - Exported APB1 bus clock for PIO.
于 2018年2月7日 GMT+08:00 下午5:02:10, Maxime Ripard 写到:
>Hi,
>
>On Sat, Feb 03, 2018 at 11:49:40PM +0800, Icenowy Zheng wrote:
>> +/* Force the output divider of video PLLs to 0 */
>> +for (i = 0; i < ARRAY_SIZE(pll_video_regs); i++) {
>> +val =