Re: [linux-sunxi] [PATCH 1/2] sunxi: add PRCM secure switch register definition
在 2017-08-09 11:46，Chen-Yu Tsai 写道：
On Tue, Aug 8, 2017 at 2:46 PM, wrote:
在 2017-08-08 12:13，Chen-Yu Tsai 写道：
On Thu, Jul 20, 2017 at 2:00 PM, Icenowy Zheng
wrote:
Some new Allwinner SoCs' PRCM has a secure switch register, which
controls the access to some clock and power registers in PRCM block.
Add the definition of this register and its bits in the PRCM header
file.
Signed-off-by: Icenowy Zheng
Could you provide a reference as to where or how you found out
about this?
https://github.com/tinalinux/brandy/blob/r18-v0.9/arm-trusted-firmware-1.0/plat/sun50iw1p1/sunxi_security.c#L105
I assume you've mapped out what each bit means by testing it?
Yes.
Toggling bit 0 will make at least 0x0 (CPUS_CFG_REG) inaccessible.
Toggling bit 1 will make at least 0x40 and 0x44 (PLL_CTRL_REG{0,1})
inaccessible.
Toggling bit 2 will make at least 0x120 (VDD_SYS_PWR_RST)
inaccessible.
(The register names are from http://linux-sunxi.org/PRCM )
Tested-by: Chen-Yu Tsai
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Re: [linux-sunxi] [PATCH 1/2] sunxi: add PRCM secure switch register definition
On Tue, Aug 8, 2017 at 2:46 PM, wrote: > 在 2017-08-08 12:13，Chen-Yu Tsai 写道： >> >> On Thu, Jul 20, 2017 at 2:00 PM, Icenowy Zheng wrote: >>> >>> Some new Allwinner SoCs' PRCM has a secure switch register, which >>> controls the access to some clock and power registers in PRCM block. >>> >>> Add the definition of this register and its bits in the PRCM header >>> file. >>> >>> Signed-off-by: Icenowy Zheng >> >> >> Could you provide a reference as to where or how you found out >> about this? > > > https://github.com/tinalinux/brandy/blob/r18-v0.9/arm-trusted-firmware-1.0/plat/sun50iw1p1/sunxi_security.c#L105 I assume you've mapped out what each bit means by testing it? Tested-by: Chen-Yu Tsai -- You received this message because you are subscribed to the Google Groups "linux-sunxi" group. To unsubscribe from this group and stop receiving emails from it, send an email to linux-sunxi+unsubscr...@googlegroups.com. For more options, visit https://groups.google.com/d/optout.
Re: [linux-sunxi] [PATCH 1/2] sunxi: add PRCM secure switch register definition
在 2017-08-08 12:13，Chen-Yu Tsai 写道： On Thu, Jul 20, 2017 at 2:00 PM, Icenowy Zheng wrote: Some new Allwinner SoCs' PRCM has a secure switch register, which controls the access to some clock and power registers in PRCM block. Add the definition of this register and its bits in the PRCM header file. Signed-off-by: Icenowy Zheng Could you provide a reference as to where or how you found out about this? https://github.com/tinalinux/brandy/blob/r18-v0.9/arm-trusted-firmware-1.0/plat/sun50iw1p1/sunxi_security.c#L105 Thanks ChenYu -- You received this message because you are subscribed to the Google Groups "linux-sunxi" group. To unsubscribe from this group and stop receiving emails from it, send an email to linux-sunxi+unsubscr...@googlegroups.com. For more options, visit https://groups.google.com/d/optout.
Re: [linux-sunxi] [PATCH 1/2] sunxi: add PRCM secure switch register definition
On Thu, Jul 20, 2017 at 2:00 PM, Icenowy Zheng wrote: > Some new Allwinner SoCs' PRCM has a secure switch register, which > controls the access to some clock and power registers in PRCM block. > > Add the definition of this register and its bits in the PRCM header > file. > > Signed-off-by: Icenowy Zheng Could you provide a reference as to where or how you found out about this? Thanks ChenYu -- You received this message because you are subscribed to the Google Groups "linux-sunxi" group. To unsubscribe from this group and stop receiving emails from it, send an email to linux-sunxi+unsubscr...@googlegroups.com. For more options, visit https://groups.google.com/d/optout.
