Re: [linux-sunxi] Re: [PATCH 02/12] sunxi: simplify ACTLR.SMP bit set #ifdef
On Sun, Jan 22, 2017 at 01:06:47AM +, André Przywara wrote: > > If we still needs it, > > First: we definitely need this symbol, since it guards an implementation > defined register and the Cortex-A53 does not define it. So we have to > confine its use to the ARMv7 Cortex CPUs. Ack. > > x86 has a CONFIG_SMP symbol, that would be > > better to just leverage that. > > Sounds tempting, but this seems to be a generic symbol that enables SMP > support _within_ U-Boot, so it allows multiple cores to execute U-Boot > code. This is clearly not what we want. Defining it seems to enable > architecture specific and generic code paths in U-Boot. > > I can rename this symbol if that helps to avoid confusion, for instance > to read CONFIG_SUNXI_NO_ACTLR_SMP or to CONFIG_CPU_IS_NOT_SMP or > CONFIG_CPU_IS_UP. There's nothing sunxi specific about it, the last one is better imho. Thanks! Maxime -- Maxime Ripard, Free Electrons Embedded Linux and Kernel engineering http://free-electrons.com -- You received this message because you are subscribed to the Google Groups "linux-sunxi" group. To unsubscribe from this group and stop receiving emails from it, send an email to linux-sunxi+unsubscr...@googlegroups.com. For more options, visit https://groups.google.com/d/optout. signature.asc Description: PGP signature
Re: [linux-sunxi] Re: [PATCH 02/12] sunxi: simplify ACTLR.SMP bit set #ifdef
Hi, On 16/01/17 07:44, Maxime Ripard wrote: > On Fri, Jan 13, 2017 at 08:28:07AM +, André Przywara wrote: >> On 13/01/17 08:09, Vishnu Patekar wrote: >> Hi Vishnu, >> >>> Even for the single core cortex-a7, SMP bit should be set before >>> enabling MMU and cache. >>> >>> Reference: Cortex A7 r0p5 TRM. section 4.3.31. >> >> Ah, good point, thanks for the heads up. I was misled by the SMP name >> when answering Icenowy. >> So it's about coherency in general and we need the bit for TLBs and >> caches to work as well. >> Let me check what that means for the other SoCs and whether we need to >> rename the config symbol then. So I checked the other ARMv7 Cortex TRMs, in contrast to the A7 TRM they explicitly speak of cache and TLB requests from other _processors_. So it should not be needed to use caches and the MMU on a uni-core implementation (which seem to be pretty rare with Cortex-A7s). But: my understanding is that it actually controls handling coherency request from outside of the processor core, which could be from a coherent agent on the bus as well, if I get this correctly. So I think it does not hurt to enable the bit on the V3s as well and could avoid potential problems. As this lines up with what the TRM says, we should turn it on as in the other cores. Icenowy: did you see problems with setting this bit and turned it off for a reason or was that just because the bit is named "SMP"? > If we still needs it, First: we definitely need this symbol, since it guards an implementation defined register and the Cortex-A53 does not define it. So we have to confine its use to the ARMv7 Cortex CPUs. > x86 has a CONFIG_SMP symbol, that would be > better to just leverage that. Sounds tempting, but this seems to be a generic symbol that enables SMP support _within_ U-Boot, so it allows multiple cores to execute U-Boot code. This is clearly not what we want. Defining it seems to enable architecture specific and generic code paths in U-Boot. I can rename this symbol if that helps to avoid confusion, for instance to read CONFIG_SUNXI_NO_ACTLR_SMP or to CONFIG_CPU_IS_NOT_SMP or CONFIG_CPU_IS_UP. Cheers, Andre. -- You received this message because you are subscribed to the Google Groups "linux-sunxi" group. To unsubscribe from this group and stop receiving emails from it, send an email to linux-sunxi+unsubscr...@googlegroups.com. For more options, visit https://groups.google.com/d/optout.
Re: [linux-sunxi] Re: [PATCH 02/12] sunxi: simplify ACTLR.SMP bit set #ifdef
On Fri, Jan 13, 2017 at 08:28:07AM +, André Przywara wrote: > On 13/01/17 08:09, Vishnu Patekar wrote: > Hi Vishnu, > > > Even for the single core cortex-a7, SMP bit should be set before > > enabling MMU and cache. > > > > Reference: Cortex A7 r0p5 TRM. section 4.3.31. > > Ah, good point, thanks for the heads up. I was misled by the SMP name > when answering Icenowy. > So it's about coherency in general and we need the bit for TLBs and > caches to work as well. > Let me check what that means for the other SoCs and whether we need to > rename the config symbol then. If we still needs it, x86 has a CONFIG_SMP symbol, that would be better to just leverage that. Thanks! Maxime -- Maxime Ripard, Free Electrons Embedded Linux and Kernel engineering http://free-electrons.com -- You received this message because you are subscribed to the Google Groups "linux-sunxi" group. To unsubscribe from this group and stop receiving emails from it, send an email to linux-sunxi+unsubscr...@googlegroups.com. For more options, visit https://groups.google.com/d/optout. signature.asc Description: PGP signature
Re: [linux-sunxi] Re: [PATCH 02/12] sunxi: simplify ACTLR.SMP bit set #ifdef
On 13/01/17 08:09, Vishnu Patekar wrote: Hi Vishnu, > Even for the single core cortex-a7, SMP bit should be set before > enabling MMU and cache. > > Reference: Cortex A7 r0p5 TRM. section 4.3.31. Ah, good point, thanks for the heads up. I was misled by the SMP name when answering Icenowy. So it's about coherency in general and we need the bit for TLBs and caches to work as well. Let me check what that means for the other SoCs and whether we need to rename the config symbol then. Cheers, Andre. > > On Fri, Jan 13, 2017 at 12:41 PM, Icenowy Zheng wrote: >> >> >> 13.01.2017, 09:34, "Andre Przywara" : >>> Instead of enumerating all SoC families that need that bit set, let's >>> just express this more clearly: The SMP bits needs to be set on >>> SMP capable ARMv7 CPUs. It's much easier to Kconfig to express it the >>> other way round, so we use ! NO_SMP and ! ARM64. >> >> How about single-core Cortex-A7? >> >>> >>> Signed-off-by: Andre Przywara >>> --- >>> arch/arm/mach-sunxi/board.c | 5 + >>> board/sunxi/Kconfig | 6 ++ >>> 2 files changed, 7 insertions(+), 4 deletions(-) >>> >>> diff --git a/arch/arm/mach-sunxi/board.c b/arch/arm/mach-sunxi/board.c >>> index 58fbacb..5a63124 100644 >>> --- a/arch/arm/mach-sunxi/board.c >>> +++ b/arch/arm/mach-sunxi/board.c >>> @@ -180,10 +180,7 @@ void s_init(void) >>> /* No H3 BSP, boot0 seems to not modify SUNXI_SRAMC_BASE + 0x44 */ >>> #endif >>> >>> -#if defined CONFIG_MACH_SUN6I || \ >>> - defined CONFIG_MACH_SUN7I || \ >>> - defined CONFIG_MACH_SUN8I || \ >>> - defined CONFIG_MACH_SUN9I >>> +#if !defined(CONFIG_SUNXI_NO_SMP) && !defined(CONFIG_ARM64) >>> /* Enable SMP mode for CPU0, by setting bit 6 of Auxiliary Ctl reg >>> */ >>> asm volatile( >>> "mrc p15, 0, r0, c1, c0, 1\n" >>> diff --git a/board/sunxi/Kconfig b/board/sunxi/Kconfig >>> index 37b4252..79b6fa7 100644 >>> --- a/board/sunxi/Kconfig >>> +++ b/board/sunxi/Kconfig >>> @@ -27,6 +27,10 @@ config SPL_POWER_SUPPORT >>> config SPL_SERIAL_SUPPORT >>> default y >>> >>> +config SUNXI_NO_SMP >>> + bool >>> + default n >>> + >>> # Note only one of these may be selected at a time! But hidden choices are >>> # not supported by Kconfig >>> config SUNXI_GEN_SUN4I >>> @@ -50,12 +54,14 @@ choice >>> config MACH_SUN4I >>> bool "sun4i (Allwinner A10)" >>> select CPU_V7 >>> + select SUNXI_NO_SMP >>> select SUNXI_GEN_SUN4I >>> select SUPPORT_SPL >>> >>> config MACH_SUN5I >>> bool "sun5i (Allwinner A13)" >>> select CPU_V7 >>> + select SUNXI_NO_SMP >>> select SUNXI_GEN_SUN4I >>> select SUPPORT_SPL >>> >>> -- >>> 2.8.2 >> >> -- >> You received this message because you are subscribed to the Google Groups >> "linux-sunxi" group. >> To unsubscribe from this group and stop receiving emails from it, send an >> email to linux-sunxi+unsubscr...@googlegroups.com. >> For more options, visit https://groups.google.com/d/optout. -- You received this message because you are subscribed to the Google Groups "linux-sunxi" group. To unsubscribe from this group and stop receiving emails from it, send an email to linux-sunxi+unsubscr...@googlegroups.com. For more options, visit https://groups.google.com/d/optout.
Re: [linux-sunxi] Re: [PATCH 02/12] sunxi: simplify ACTLR.SMP bit set #ifdef
Even for the single core cortex-a7, SMP bit should be set before enabling MMU and cache. Reference: Cortex A7 r0p5 TRM. section 4.3.31. On Fri, Jan 13, 2017 at 12:41 PM, Icenowy Zheng wrote: > > > 13.01.2017, 09:34, "Andre Przywara" : >> Instead of enumerating all SoC families that need that bit set, let's >> just express this more clearly: The SMP bits needs to be set on >> SMP capable ARMv7 CPUs. It's much easier to Kconfig to express it the >> other way round, so we use ! NO_SMP and ! ARM64. > > How about single-core Cortex-A7? > >> >> Signed-off-by: Andre Przywara >> --- >> arch/arm/mach-sunxi/board.c | 5 + >> board/sunxi/Kconfig | 6 ++ >> 2 files changed, 7 insertions(+), 4 deletions(-) >> >> diff --git a/arch/arm/mach-sunxi/board.c b/arch/arm/mach-sunxi/board.c >> index 58fbacb..5a63124 100644 >> --- a/arch/arm/mach-sunxi/board.c >> +++ b/arch/arm/mach-sunxi/board.c >> @@ -180,10 +180,7 @@ void s_init(void) >> /* No H3 BSP, boot0 seems to not modify SUNXI_SRAMC_BASE + 0x44 */ >> #endif >> >> -#if defined CONFIG_MACH_SUN6I || \ >> - defined CONFIG_MACH_SUN7I || \ >> - defined CONFIG_MACH_SUN8I || \ >> - defined CONFIG_MACH_SUN9I >> +#if !defined(CONFIG_SUNXI_NO_SMP) && !defined(CONFIG_ARM64) >> /* Enable SMP mode for CPU0, by setting bit 6 of Auxiliary Ctl reg >> */ >> asm volatile( >> "mrc p15, 0, r0, c1, c0, 1\n" >> diff --git a/board/sunxi/Kconfig b/board/sunxi/Kconfig >> index 37b4252..79b6fa7 100644 >> --- a/board/sunxi/Kconfig >> +++ b/board/sunxi/Kconfig >> @@ -27,6 +27,10 @@ config SPL_POWER_SUPPORT >> config SPL_SERIAL_SUPPORT >> default y >> >> +config SUNXI_NO_SMP >> + bool >> + default n >> + >> # Note only one of these may be selected at a time! But hidden choices are >> # not supported by Kconfig >> config SUNXI_GEN_SUN4I >> @@ -50,12 +54,14 @@ choice >> config MACH_SUN4I >> bool "sun4i (Allwinner A10)" >> select CPU_V7 >> + select SUNXI_NO_SMP >> select SUNXI_GEN_SUN4I >> select SUPPORT_SPL >> >> config MACH_SUN5I >> bool "sun5i (Allwinner A13)" >> select CPU_V7 >> + select SUNXI_NO_SMP >> select SUNXI_GEN_SUN4I >> select SUPPORT_SPL >> >> -- >> 2.8.2 > > -- > You received this message because you are subscribed to the Google Groups > "linux-sunxi" group. > To unsubscribe from this group and stop receiving emails from it, send an > email to linux-sunxi+unsubscr...@googlegroups.com. > For more options, visit https://groups.google.com/d/optout. -- You received this message because you are subscribed to the Google Groups "linux-sunxi" group. To unsubscribe from this group and stop receiving emails from it, send an email to linux-sunxi+unsubscr...@googlegroups.com. For more options, visit https://groups.google.com/d/optout.
