Hi, all,
I'm playing with USB gadget with configfs on raspberry pi zero w. My
goal is to setup a generic functionfs function that uses Windows OS
descriptor so that windows would automatically install winusb driver.
It seems I would have to
- enable MS-specific os descriptor
- specify the compat
Hi,
On Sat, Dec 16, 2017 at 10:45 AM, Thang Q. Nguyen wrote:
> From: Tung Nguyen
>
> Currently, hcd->shared_hcd always creates and registers to the usb-core.
> If, for some reasons, USB3 downstream port is disabled, no roothub port for
> USB3.0 is found. This causes kernel to display an error:
>
The TUR commands come from the sd_mod (I think). Definitely not from
usb-storage. So I would take it up at that level.
Matt
On Wed, Jan 3, 2018 at 4:25 PM, Eduardo TrĂ¡pani wrote:
> Usually the kernel reads the pendrive like this:
>
> TEST UNIT READY
> READ(10)
> ...
> READ(10)
> TEST UNIT READ
The F81532/534 had auto RTS direction support for RS485 mode.
We'll read it from internal Flash with address 0x2f01~0x2f04 for 4 ports.
There are 4 conditions below:
0: F81534_PORT_CONF_RS232.
1: F81534_PORT_CONF_RS485.
2: value error, default to F81534_PORT_CONF_RS232.
The F81532/534 had 4 clocksource 1.846/18.46/14.77/24MHz and baud rates
can be up to 1.5Mbits with 24MHz. But on some baud rate (384~500kps), the
TX side will send the data frame too close to treat frame error on RX
side. This patch will force all TX data frame with delay 1bit gap.
Signed-off-by:
The F81532/534 had 4 clocksource 1.846/18.46/14.77/24MHz and baud rates
can be up to 1.5Mbits with 24MHz.
This device may generate data overrun when baud rate setting to 921600bps
or higher with old UART trigger level setting (8x14=112) with full
loading. We'll change trigger level from 8x14=112 t
The F81532/534 had 3 output pin (M0/SD, M1, M2) with open-drain mode to
control transceiver. We'll read it from internal Flash with address
0x2f05~0x2f08 for 4 ports. The value is range from 0 to 7. The M0/SD is
MSB of this value. For a examples, If read value is 6, we'll write M0/SD,
M1, M2 as 1,
The F81532/534 can be disable port by manufacturer with
following H/W design.
1: Connect DCD/DSR/CTS/RI pin to ground.
2: Connect RX pin to ground.
In driver, we'll implements some detect method likes following:
1: Read MSR.
2: Turn MCR LOOP bit on, off and read LSR after delay wit
Some low-speed devices (for example, bluetooth) do not have
time to initialize. For them, ETIMEDOUT is a valid error.
We need to give them another try. Otherwise, they will
never be initialized correctly and in dmesg will be messages
"Bluetooth: hci0 command 0x1002 tx timeout" or similars.
Fixes:
On Wed, Jan 03, 2018 at 12:51:51PM -0500, Alan Stern wrote:
> The error-handling pathways in usb_add_gadget_udc_release() are messed
> up. Aside from the uninformative statement labels, they can deallocate
> the udc structure after calling put_device(), which is a double-free.
> This was observed
On Wed, 3 Jan 2018 13:08:12 -0800
Matthew Wilcox wrote:
> > + mutex_lock(&rp->fetch_lock);
> > offset = vmf->pgoff << PAGE_SHIFT;
> > if (offset >= rp->b_size)
> > + mutex_unlock(&rp->fetch_lock);
> > return VM_FAULT_SIGBUS;
> > chunk_idx = offset / CHUNK_SIZE;
Usually the kernel reads the pendrive like this:
TEST UNIT READY
READ(10)
...
READ(10)
TEST UNIT READY
But under some conditions, the last TEST UNIT READY is not being sent
and because of that, on this device: Kingston DT 101 G2, the drive's
activity light keeps on blinking even though nothing is
On Wed, Jan 03, 2018 at 03:04:19PM -0600, Pete Zaitcev wrote:
> @@ -1231,12 +1233,15 @@ static int mon_bin_vma_fault(struct vm_fault *vmf)
> unsigned long offset, chunk_idx;
> struct page *pageptr;
>
> + mutex_lock(&rp->fetch_lock);
> offset = vmf->pgoff << PAGE_SHIFT;
>
On Wed, 3 Jan 2018 12:26:04 +0300
"Kirill A. Shutemov" wrote:
> > > +++ b/drivers/usb/mon/mon_bin.c
> > > @@ -1228,15 +1228,24 @@ static void mon_bin_vma_close(struct
> > > vm_area_struct *vma)
> > > static int mon_bin_vma_fault(struct vm_fault *vmf)
> > > {
> > > struct mon_reader_bin *rp =
This adds the ELV ALC 8xxx Battery Charging device
to the list of USB IDs of drivers/usb/serial/cp210x.c
Signed-off-by: Christian Holl
---
drivers/usb/serial/cp210x.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/usb/serial/cp210x.c b/drivers/usb/serial/cp210x.c
index 7c6273b..ea6e
The error-handling pathways in usb_add_gadget_udc_release() are messed
up. Aside from the uninformative statement labels, they can deallocate
the udc structure after calling put_device(), which is a double-free.
This was observed by KASAN in automatic testing.
This patch cleans up the routine. I
On Wed, Jan 03, 2018 at 12:59:53PM -0300, Cristian wrote:
> Hello,
>
> I am testing the development version:
> 4.15.0-041500rc6-generic
>
> [ 116.907874] cdc_ether 3-2:1.0 enx0c5b8f279a64: kevent 12 may have
> been dropped
> [ 116.907892] cdc_ether 3-2:1.0 enx0c5b8f279a64: kevent 12 may have
>
Hello,
All the technical information with the kernel version 4.10:
https://bugs.launchpad.net/bugs/1741080
Regards,
--
Cristian
2018-01-03 12:59 GMT-03:00 Cristian :
> Hello,
>
> I am testing the development version:
> 4.15.0-041500rc6-generic
>
> [ 116.907874] cdc_ether 3-2:1.0 enx0c5b8f27
Hello,
I am testing the development version:
4.15.0-041500rc6-generic
[ 116.907874] cdc_ether 3-2:1.0 enx0c5b8f279a64: kevent 12 may have
been dropped
[ 116.907892] cdc_ether 3-2:1.0 enx0c5b8f279a64: kevent 12 may have
been dropped
[ 118.670851] usbcore: registered new interface driver usbseri
Hello,
Testing kernel: 4.14.11
Regards,
--
Cristian
2017-12-27 17:05 GMT-03:00 Greg KH :
> On Wed, Dec 27, 2017 at 04:07:36PM -0300, Cristian wrote:
>> Hello,
>>
>> Report:
>> https://bugzilla.kernel.org/show_bug.cgi?id=198291
>>
>> dmesg:
>> [ 5519.779175] cdc_ether 3-2:1.0 enx0c5b8f279a64:
On Tuesday, December 19, 2017 10:15:07 AM Joe Perches wrote:
> Convert DEVICE_ATTR uses to DEVICE_ATTR_RW where possible.
>
> Done with perl script:
>
> $ git grep -w --name-only DEVICE_ATTR | \
> xargs perl -i -e 'local $/; while (<>) {
> s/\bDEVICE_ATTR\s*\(\s*(\w+)\s*,\s*\(?(\s*S_IRUGO\s*\|
From: Vivek Gautam
Move from using array of clocks to clk_bulk_* APIs that
are available now.
Signed-off-by: Vivek Gautam
Signed-off-by: Manu Gautam
---
drivers/phy/qualcomm/phy-qcom-qmp.c | 50 -
1 file changed, 16 insertions(+), 34 deletions(-)
diff --gi
From: Vivek Gautam
Pipe clock comes out of the phy and is available as long as
the phy is turned on. Clock controller fails to gate this
clock after the phy is turned off and generates a warning.
/ # [ 33.048561] gcc_usb3_phy_pipe_clk status stuck at 'on'
[ 33.048585] [ cut here
PHY block or asynchronous reset requires signal
to be asserted before de-asserting. Driver is only
de-asserting signal which is already low, hence
reset operation is a no-op. Fix this by asserting
signal first. Also, resetting requires PHY clocks
to be turned ON only after reset is finished. Fix
th
PHY must be powered on before turning ON clocks and
attempting to initialize it. Driver is exposing
separate init and power_on routines for this.
Apparently USB dwc3 core driver performs power-on
after init. Also, poweron and init for QUSB2 PHY
need to be executed together always, hence remove
powe
PHY regulators which are enabled from power_on() must be ON
before turning-on clocks and initializing it as part of init().
As most of the core drivers perform power_on() after init(), move
PHY regulators enable to com_init() and use power_on() to
only enable pipe_clk. This pipe_clk is output from
Driver is currently performing PHY reset after starting
SERDES/PCS. As per hardware datasheet reset must be done
before starting PHY. Hence, update the sequence.
Signed-off-by: Manu Gautam
---
drivers/phy/qualcomm/phy-qcom-qmp.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff -
New version of QUSB2 PHY has some registers offset changed.
Add support to have register layout for a target and update
the same in phy_configuration.
Signed-off-by: Manu Gautam
---
drivers/phy/qualcomm/phy-qcom-qusb2.c | 149 +-
1 file changed, 109 insertions(+),
Update compatible string and clock names for QMP version V3
USB PHY.
Acked-by: Rob Herring
Signed-off-by: Manu Gautam
---
Documentation/devicetree/bindings/phy/qcom-qmp-phy.txt | 6 +-
1 file changed, 5 insertions(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/phy/qcom-qm
New revision (v3) of QMP PHY uses different offsets
for almost all of the registers. Hence, move these
definitions to header file so that updated offsets
can be added for QMP v3.
Signed-off-by: Manu Gautam
---
drivers/phy/qualcomm/phy-qcom-qmp.c | 119 +--
drivers/phy
Use register layout to add additional registers present
on QUSB2 PHY V2 version for PHY initialization.
Other than new registers on V2, following two register's
offset and bit definitions are different: POWERDOWN control
and PLL_STATUS.
Signed-off-by: Manu Gautam
---
drivers/phy/qualcomm/phy-qco
Registers offsets for QMP V3 PHY are changed from
previous versions (1/2), update same in header file.
Signed-off-by: Manu Gautam
---
drivers/phy/qualcomm/phy-qcom-qmp.h | 149
1 file changed, 149 insertions(+)
diff --git a/drivers/phy/qualcomm/phy-qcom-qmp.
Update generic compatible string for QUSB2 V2 PHY. This will allow
all targets using QUSB2 V2 use same string.
Acked-by: Rob Herring
Signed-off-by: Manu Gautam
---
Documentation/devicetree/bindings/phy/qcom-qusb2-phy.txt | 5 -
1 file changed, 4 insertions(+), 1 deletion(-)
diff --git a/Do
Add following USB speed related PHY modes:
LS (Low Speed), FS (Full Speed), HS (High Speed), SS (Super Speed)
Speed related information is required by some QCOM PHY drivers
to program PHY monitor resume/remote-wakeup events in suspended
state. Speed is needed in order to set correct polarity of wa
QMP V3 USB3 PHY is a DisplayPort (DP) and USB combo PHY
with dual RX/TX lanes to support type-c. There is a
separate block DP_COM for configuration related to type-c
or DP. Add support for dp_com region and secondary rx/tx
lanes initialization.
Signed-off-by: Manu Gautam
---
drivers/phy/qualcomm
Disable clocks and enable PHY autonomous mode to detect
wakeup events when PHY is suspended.
Core driver should notify speed to PHY driver to enable
LFPS and/or RX_DET interrupts.
Signed-off-by: Manu Gautam
---
drivers/phy/qualcomm/phy-qcom-qmp.c | 186 +++-
drive
Disable clocks and enable DP/DM wakeup interrupts when
suspending PHY.
Core driver should notify speed to PHY driver to enable
appropriate DP/DM wakeup interrupts polarity in suspend state.
Signed-off-by: Manu Gautam
---
drivers/phy/qualcomm/phy-qcom-qusb2.c | 184 +++
QUSB-v2 and QMP-v3 USB PHYs are present on Qualcomm's 14nm
and 10nm SOCs.
This patch series adds support for runtime PM for these
USB PHYs and adds fixes in drivers to follow PHY reset and
initialization sequence as per hardware programming manual.
Changes since v3:
- Add extra PHY_MODEs for updat
On Wed, Jan 03, 2018 at 01:02:38AM -0600, Pete Zaitcev wrote:
> On Fri, 29 Dec 2017 16:24:20 +0300
> "Kirill A. Shutemov" wrote:
>
> > Looks like MON_IOCT_RING_SIZE reallocates ring buffer without any
> > serialization wrt mon_bin_vma_fault(). By the time of get_page() the page
> > may be freed.
From: Colin Ian King
Trivial fix to spelling mistake in dev_dbg debug message.
Signed-off-by: Colin Ian King
---
drivers/usb/usbip/vhci_rx.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/usb/usbip/vhci_rx.c b/drivers/usb/usbip/vhci_rx.c
index 112ebb90d8c9..44cd645
Add two arguments in "mediatek,syscon-wakeup" to support multi
wakeup glue layer between SSUSB and SPM, and use standard property
"wakeup-source" to replace the private "mediatek,wakeup-src"
Signed-off-by: Chunfeng Yun
---
.../devicetree/bindings/usb/mediatek,mtk-xhci.txt| 16 ++-
The old way of usb wakeup only supports platform with single xHCI IP,
such as mt8173, but mt2712 has two xHCI IPs, so rebuild its flow and
supports the new glue layer of usb wakeup on mt2712 which is different
from mt8173.
Due to there is a hardware bug with the LINE STATE wakeup mode on
mt8173 whi
When failing to get extcon device, extcon_get_edev_by_phandle()
may return different error codes, but not only -EPROBE_DEFER,
so can't always return -EPROBE_DEFER, and fix it.
Signed-off-by: Chunfeng Yun
---
drivers/usb/mtu3/mtu3_plat.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff
The old way of usb wakeup only supports platform with single SSUSB IP,
such as mt8173, but mt2712 has two SSUSB IPs, so rebuild its flow and
also supports the new glue layer of usb wakeup on mt2712 which is
different from mt8173.
Signed-off-by: Chunfeng Yun
---
drivers/usb/mtu3/mtu3.h | 11
Add two arguments in "mediatek,syscon-wakeup" to support multi
wakeup glue layer between SSUSB and SPM, and use standard property
"wakeup-source" to replace the private "mediatek,enable-wakeup"
Signed-off-by: Chunfeng Yun
---
Documentation/devicetree/bindings/usb/mediatek,mtu3.txt | 15 +
Use new binding about USB wakeup which now supports multi USB
wakeup glue layer between SSUSB and SPM.
Meanwhile remove dummy clocks of USB wakeup.
Signed-off-by: Chunfeng Yun
---
arch/arm64/boot/dts/mediatek/mt8173-evb.dts | 2 +-
arch/arm64/boot/dts/mediatek/mt8173.dtsi| 12 +++-
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