RE: [PATCH] USB TYPEC: RT1711H Type-C Chip Driver

Hi Guenter, We try to use the TCPCI driver on RT1711H and here are some questions. Q1. Is current TCPCI driver written according to TypeC Port Controller Interface Specification Revision 1.0 & Version 1.2? Q2. Because 0x80~0xFF are vendor defined registers. Some of them are needed to be

RE: [RFC/RFT usb-next v1 5/6] usb: chipidea: do not set the "phy" field in struct usb_hcd

> > > >> > >> Now that usb_add_hcd parses all generic PHYs anyways the code which > >> skips initialization of a single PHY will go away. > >> Remove the code which sets struct usb_hcd's phy field from the > >> chipidea driver as this field will go away soon. > >> > >> Signed-off-by: Martin

[PATCH] usbip: Correct maximum value of CONFIG_USBIP_VHCI_HC_PORTS

Now that usbip supports USB3, the maximum number of ports allowed on a hub is 15 (USB_SS_MAXPORTS), not 31 (USB_MAXCHILDREN). Reported-by: Gianluigi Tiesi Reported-by: Borissh1983 References: https://bugs.debian.org/878866 Fixes: 1c9de5bf4286 ("usbip:

[PATCH 0/3] DWC3 support for Amlogic Meson AXG and GXL SoCs

Amlogic Meson AXG and GXL SoCs can use the dwc3-of-simple with little modifications. These SoCs use: - a gate clock for the USB components (DWC3, USB PHYs) - a reset line which is shared across all USB components (DWC3, USB2 and USB3 PHYs, OTG detection logic inside the USB3 PHY registers) - a

[PATCH 1/3] dt-bindings: usb: add support for dwc3 controller on Amlogic Meson GX

Amlogic Meson GX SoCs (GXL and AXG) come with a (host-only) dwc3 USB controller. This requires a clock to be enabled and a reset line to be pulsed to get the hardware into a known state. Add the documentation for this IP block, similar to "qcom,dwc3.txt". Signed-off-by: Martin Blumenstingl

[PATCH 3/3] usb: dwc3: of-simple: add support for the Amlogic Meson GXL and AXG SoCs

Amlogic Meson GXL and AXG SoCs come with a (host-only) dwc3 USB controller. To use this controller a clock has to be enabled and a reset line has to be pulsed. Enabling the clock works identical to other SoCs. However, the reset line has to be pulsed (using reset_control_reset) instead of using a

[PATCH 2/3] usb: dwc3: of-simple: add support for shared and pulsed reset lines

Some SoCs (such as Amlogic Meson GXL for example) share the reset line with other components (in case of the Meson GXL example there's a shared reset line between the USB2 PHYs, USB3 PHYs and the dwc3 controller). Additionally SoC implementations may prefer a reset pulse over level resets. Add an

Re: [PATCH 4.9] usbip: vhci_hcd: clear just the USB_PORT_STAT_POWER bit

On Fri, Jan 26, 2018 at 11:54:35AM -0700, Shuah Khan wrote: > Upstream commit 1c9de5bf4286 ("usbip: vhci-hcd: Add USB3 SuperSpeed > support") Hm, I think you have the wrong commit id here. I don't see any commit upstream with the Subject you have here, what are you referring to? thanks, greg