Hi,
Just to add my tested-by to the patch sent by Grygorii Strashko on 03/31/2016
(https://lkml.org/lkml/2016/3/31/609).
The patch was tested on a v4.6 kernel, running in a Juno r1 development board,
being the USB 3.0 Host prototyped in a FPGA.
Tested-by: Joao Pinto <jpi...@synopsys.com>
Hi,
Just to give you an update.
All is working great, the cause was an FPGA configuration issue.
Thank you for your support.
Joao
On 5/19/2016 4:42 PM, Joao Pinto wrote:
>
> After a few moments the schedule problem happen again:
>
> # INFO: task kworker/0:1:349 blocked for m
] usb_alloc_dev+0x68/0x2cc
[] hub_event+0x784/0x11f4
[] process_one_work+0x130/0x2f4
[] worker_thread+0x54/0x434
[] kthread+0xd4/0xe8
[] ret_from_fork+0x10/0x40
So Chris' patch did not solve this problem either.
Thanks.
On 5/19/2016 4:39 PM, Joao Pinto wrote:
> Hi Felipe and Mathias,
>
>
Hi Felipe and Mathias,
On 5/19/2016 1:22 PM, Mathias Nyman wrote:
> On 19.05.2016 14:23, Joao Pinto wrote:
>> Hi Felipe,
>>
>> On 5/19/2016 11:32 AM, Felipe Balbi wrote:
>>>
>>> Hi,
>>>
>>>
>>> Note that we really did get
Hi Mathias and Felipe,
On 5/19/2016 1:22 PM, Mathias Nyman wrote:
> On 19.05.2016 14:23, Joao Pinto wrote:
>> Hi Felipe,
>>
>> On 5/19/2016 11:32 AM, Felipe Balbi wrote:
>>>
>>> Hi,
>>>
>>>
>>> Note that we really did get
Hi Felipe,
On 5/19/2016 11:32 AM, Felipe Balbi wrote:
>
> Hi,
>
> Joao Pinto <joao.pi...@synopsys.com> writes:
>> Hi Felipe and Mathias,
>>
>> Sending kernel log with extra xhci messages in attachment!
>> Thanks you for the help!
>
> y
Hi Felipe and Mathias,
Sending kernel log with extra xhci messages in attachment!
Thanks you for the help!
On 5/19/2016 11:02 AM, Joao Pinto wrote:
> Hi Felipe!
>
> On 5/19/2016 10:57 AM, Felipe Balbi wrote:
>>
>> Hi João,
>>
>> Adding Mathias, who's xHCI's mai
Hi Felipe,
I am trying to bring up a DWC USB 3.0 Host with linux (v4.6-rc5) running in a
ARM64 development board.
I have implemented the following suggested fix to overcome the DMA problem I was
having:
https://lkml.org/lkml/2016/3/31/609
I received one interrupt but I am getting cyclic
Hi Felipe,
I confirmed that no interrupts are received. My hw colleague is going to check
the design!
On 4/29/2016 11:25 AM, Felipe Balbi wrote:
>
> Hi João,
>
> Joao Pinto <joao.pi...@synopsys.com> writes:
>> I am trying to bring up a USB 3.0 Host Controller with an
Hi Felipe,
I am trying to bring up a USB 3.0 Host Controller with an ARM64 platform (Juno)
and I was also getting the dma issue discussed in this thread:
https://www.mail-archive.com/linux-usb@vger.kernel.org/msg73137.html
I then applied Grygorii Strashko' patch and managed to have a bus
Hi Felipe,
On 2/22/2016 8:39 AM, Felipe Balbi wrote:
>
> Could this be a bug in your emulation environment ? Have you tested any
> other PCIe endpoints ?
>
We tried with a SATA endpoint and experienced the same problem, so there's some
problem that must be solved in our virtualization
Hi to all!
I am testing a PCIe Root Complex prototyping setup in which I have a USB 3.0
host as a PCI Endpoint.
Running in an ARC CPU platform it works well, but when running in an emulated
ARM64 (this is done by a Synopsys virtualization tool) the endpoint
initialization fails as can be seen in
and baseline besl values.
Signed-off-by: Joao Pinto <jpi...@synopsys.com>
Tested-by: Joao Pinto <jpi...@synopsys.com>
---
drivers/usb/gadget/composite.c | 12 +++-
1 file changed, 11 insertions(+), 1 deletion(-)
diff --git a/drivers/usb/gadget/composite.c b/drivers/usb/gadget/compo
previously?
Thanks,
Joao Pinto
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Hi Filipe!
We are experiencing a problem in a solution using the dwc3 driver.
I will start by enumerating the setup:
a) CPU running Linux Kernel 3.18
b) DesignWare USB 3.0 Device IP
c) Windows 7 Host PC
The dwc3 is loading successfully, but when we plug to the Windows 7 PC, it takes
Hi Filipe!
Hope you are doing well!
At Synopsys we are developing a system using our DesignWare USB 3.0 Controller,
configured to operate as an USB 2.0 (featuring OTG 2.0).
I talked to Jonh Youn about this and he said that something was being done to
make dwc3 driver support OTG 2.0.
I would
Hi,
My name is Joao Pinto and I am working at Synopsys as a Software Engineer mainly
in the USB Subsystem.
I am sending you this email in order to know if someone is already working in
the driver' development for Synopsys' USB 3.1 Host Device and USB 2.0 OTG
Controllers.
a) If no one
Hi Filipe,
On 4/27/2015 3:56 PM, Felipe Balbi wrote:
Hi Joao,
On Mon, Apr 27, 2015 at 03:48:48PM +0100, Joao Pinto wrote:
My name is Joao Pinto and I am working at Synopsys as a Software Engineer
mainly
in the USB Subsystem.
I am sending you this email in order to know if someone
Hi Greg,
On 4/27/2015 3:27 PM, Greg KH wrote:
On Mon, Apr 27, 2015 at 09:59:19AM +0100, Joao Pinto wrote:
Hi,
My name is Joao Pinto and I am working at Synopsys as a Software Engineer
mainly
in the USB Subsystem.
I am sending you this email in order to know if someone is already working
Hi,
On 4/27/2015 4:49 PM, Felipe Balbi wrote:
Hi,
On Mon, Apr 27, 2015 at 04:04:08PM +0100, Joao Pinto wrote:
Hi Filipe,
that's Felipe (and yes, I know it's João, but you spelled it without ~)
:-)
On 4/27/2015 3:56 PM, Felipe Balbi wrote:
Hi Joao,
On Mon, Apr 27, 2015 at 03:48
On 3/3/2015 6:48 PM, Greg KH wrote:
On Tue, Mar 03, 2015 at 05:06:45PM +, Joao Pinto wrote:
Hello,
I am sending this email in order to get some feedback from you about a
feature that I am planning to do in a driver I am working on.
I don't see any code here, or really, any specifics
Hello,
I am sending this email in order to get some feedback from you about a feature
that I am planning to do in a driver I am working on.
This new feature basically is to turn the relationship between driver and
hardware IP more transparent, making the software more robust.
Let me explain
Hello Peter,
On 3/3/2015 5:35 PM, Peter Stuge wrote:
Hello Joao,
Joao Pinto wrote:
This new feature basically is to turn the relationship between driver
and hardware IP more transparent, making the software more robust.
This is an important matter already today, and will only become more
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