Doug,
Thanks for your detail debug information, pls add my Reviewed-by for
this patch.
Thanks,
- Kever
On 02/03/2016 06:47 AM, Doug Anderson wrote:
Kever,
On Mon, Feb 1, 2016 at 11:46 PM, Kever Yang <kever.y...@rock-chips.com> wrote:
Doug,
On 01/29/2016 10:20 AM, Douglas Anderson
Doug,
On 02/02/2016 08:36 AM, Doug Anderson wrote:
Kever,
On Sun, Jan 31, 2016 at 8:36 PM, Doug Anderson <diand...@chromium.org> wrote:
Kever,
On Sun, Jan 31, 2016 at 7:32 PM, Kever Yang <kever.y...@rock-chips.com> wrote:
Doug,
On 02/01/2016 06:09 AM, Doug Anderson wrote:
Ke
Doug,
On 01/29/2016 10:20 AM, Douglas Anderson wrote:
When setting up ISO and INT transfers dwc2 needs to specify whether the
transfer is for an even or an odd frame (or microframe if the controller
is running in high speed mode).
The controller appears to use this as a simple way to figure
Doug,
On 02/01/2016 06:09 AM, Doug Anderson wrote:
Kever,
On Sun, Jan 31, 2016 at 1:36 AM, Kever Yang <kever.y...@rock-chips.com> wrote:
Doug,
On 01/29/2016 10:20 AM, Douglas Anderson wrote:
In dwc2_hcd_qh_deactivate() we will put some things on the
periodic_sched_ready list. These
Doug,
On 01/29/2016 10:20 AM, Douglas Anderson wrote:
According to the most up to date version of the dwc2 databook, the FRINT
field of the HFIR register should be programmed to:
* 125 us * (PHY clock freq for HS) - 1
* 1000 us * (PHY clock freq for FS/LS) - 1
I got 3 version of dwc_otg
Doug,
Reviewed-by: Kever Yang <kever.y...@rock-chips.com>
Thanks,
- Kever
On 01/29/2016 10:20 AM, Douglas Anderson wrote:
I find that when I plug a full speed (NOT high speed) hub into a dwc2
port and then I plug a bunch of devices into that full speed hub that
dwc2 goes bat guano
Doug,
On 01/29/2016 10:20 AM, Douglas Anderson wrote:
In dwc2_hcd_qh_deactivate() we will put some things on the
periodic_sched_ready list. These things won't be taken off the ready
list until the next SOF, which might be a little late. Let's put them
on right away.
Signed-off-by: Douglas
Hi Doug,
On 01/28/2016 03:44 AM, Doug Anderson wrote:
If it's all the same to you, I'll probably change it back to 525 and
then increase the periodic FIFO size by 3 DWORDS in the next patch.
12 bytes may not be much, but might as well make use of them to
improve performance / compatibility?
Hi Doug,
I test this patch with USB 2.0 analyzer, and it make the CSPLIT in the
same order with the SSPLIT, so
Reviewed-by: Kever Yang <kever.y...@rock-chips.com>
Tested-by: Kever Yang <kever.y...@rock-chips.com>
Thanks,
- Kever
On 01/23/2016 02:18 AM, Douglas Anderson wrote:
We
,
- Kever
On 01/28/2016 11:28 AM, Doug Anderson wrote:
Kever,
On Wed, Jan 27, 2016 at 7:10 PM, Kever Yang <kever.y...@rock-chips.com> wrote:
Hi Doug,
We are using the minimum FIFO size mode for TX now, which only
equal to one max packet size.
The addition FIFO size may help shorten the inter-
Hi Doug,
We are using the minimum FIFO size mode for TX now, which only
equal to one max packet size.
The addition FIFO size may help shorten the inter-packet data
prepare latency when the bus/DRAM is busy.
For the actual usage in TX, we have very little change to use the
period TX FIFO with
driver.
For this patch:
Reviewed-by: Kever Yang <kever.y...@rock-chips.com>
Thanks,
- Kever
On 01/23/2016 02:18 AM, Douglas Anderson wrote:
In preparation for future changes to the scheduler let's add some
tracing that makes it easy for us to see what's happening. By default
this t
Hi Doug,
The NULL pointer bug is one of the most frequent issue we met
during hot plug stress test, thanks for this bug fix.
Reviewed-by: Kever Yang <kever.y...@rock-chips.com>
Thanks,
- Kever
On 01/23/2016 02:18 AM, Douglas Anderson wrote:
When poking around with USB devices with slub
We've got 960 / 972 total_fifo_size on rk3288 (and presumably on
rk3066) and 525 + 128 + 256 = 909 so we're still under on both ports
even when we increment by 5.
Since we have space, Kever Yang suggests bumping by 8. He says this
will meet INCR16 access and next fifo type can start with a aligned
Hi Doug,
This is obviously a bug in dwc2 driver which not meet the usb 2.0
spec, and this patch can fix it.
Reviewed-by: Kever Yang <kever.y...@rock-chips.com>
Thanks,
- Kever
On 01/23/2016 02:18 AM, Douglas Anderson wrote:
The queues the the dwc2 host controller used are truly
Hi Paul,
I think you need this patch to fix the problem:
usb: dwc2: resume root hub when device detect with suspend state
https://patchwork.kernel.org/patch/5325111/
Thanks,
- Kever
On 01/06/2015 09:23 AM, Paul Zimmerman wrote:
From: Kever Yang [mailto:kever.y...@rock-chips.com]
Sent
Hi Roy,
Why you send two patches with different commit message but the same
change,
you should use V2 for a new patch.
On 12/03/2014 09:46 PM, LiYunzhi wrote:
From: lyz l...@rock-chips.com
You don't need the From for the patches from yourself.
Add a driver for the Rockchip SoC
After we implement the bus_suspend/resume, auto suspend id enabled.
The root hub will be auto suspend if there is no device connected,
we need to resume the root hub when a device connect detect.
This patch tested on rk3288.
Signed-off-by: Roy Li roy...@rock-chips.com
Signed-off-by: Kever Yang
On 11/14/2014 11:55 PM, Alan Stern wrote:
On Thu, 13 Nov 2014, Julius Werner wrote:
Another thing might be that the port connect interrupt does not
correctly resume the root hub. I don't really know many details about
how that works, and it seems pretty complicated. But I can see that
all
This patch is no complete, Sorry for that, I will upload a new version
tomorrow.
- Kever
On 11/17/2014 09:14 PM, Kever Yang wrote:
After we implement the bus_suspend/resume, auto suspend id enabled.
The root hub will be auto suspend if there is no device connected,
we need to resume the root
Hi Julius,
On 11/18/2014 05:21 AM, Julius Werner wrote:
On Mon, Nov 17, 2014 at 5:14 AM, Kever Yang kever.y...@rock-chips.com wrote:
After we implement the bus_suspend/resume, auto suspend id enabled.
The root hub will be auto suspend if there is no device connected,
we need to resume the root
After we implement the bus_suspend/resume, auto suspend id enabled.
The root hub will be auto suspend if there is no device connected,
we need to resume the root hub when a device connect detect.
This patch tested on rk3288.
Signed-off-by: Roy Li roy...@rock-chips.com
Signed-off-by: Kever Yang
Doug,
On 11/13/2014 07:22 AM, Doug Anderson wrote:
Kever,
On Mon, Nov 10, 2014 at 5:09 AM, Kever Yang kever.y...@rock-chips.com wrote:
Hcd controller needs bus_suspend/resume, dwc2 controller make
root hub generate suspend/resume signal with hprt0 register
when work in host mode.
After
Hi Julius,
On 11/07/2014 06:11 AM, Julius Werner wrote:
On Wed, Nov 5, 2014 at 5:30 PM, Kever Yang kever.y...@rock-chips.com wrote:
Hcd controller needs bus_suspend/resume, dwc2 controller make
root hub generate suspend/resume signal with hprt0 register
when work in host mode.
After the root
.
This patch has tested on rk3288 with suspend/resume.
Signed-off-by: Kever Yang kever.y...@rock-chips.com
Acked-by: Paul Zimmerman pa...@synopsys.com
---
Changes in v3:
- remove CONFIG_PM macro for bus_suspend/resume
- add PCGCTL operation for no device connect case
Changes in v2:
- update commit
.
This patch has tested on rk3288 with suspend/resume.
Signed-off-by: Kever Yang kever.y...@rock-chips.com
---
Changes in v2:
- update commit message
- make dwc2 suspend/resume sourcecode work
drivers/usb/dwc2/hcd.c | 78 +++---
1 file changed, 67 insertions
This patch adds suspend/resume for dwc2 hcd controller.
Signed-off-by: Kever Yang kever.y...@rock-chips.com
---
drivers/usb/dwc2/hcd.c | 74 ++
1 file changed, 63 insertions(+), 11 deletions(-)
diff --git a/drivers/usb/dwc2/hcd.c b/drivers/usb
Hi Dinh,
On 10/29/2014 07:25 AM, dingu...@opensource.altera.com wrote:
From: Dinh Nguyen dingu...@opensource.altera.com
Since the dwc2 hcd driver is currently not looking for a clock node during
init, we should not completely fail if there isn't a clock provided.
For dual-role mode, we will
Hi Dinh
On 10/29/2014 07:25 AM, dingu...@opensource.altera.com wrote:
From: Dinh Nguyen dingu...@opensource.altera.com
Adds the gadget data structure and appropriate data structure pointers
to the common dwc2_hsotg data structure. To keep the driver data
dereference code looking clean, the
me
how to test the usb suspend/resume API easily?
Changes in v2:
- remove the clock from hcd
- adjust the delay time when resume
- move all the clock operation into platform
Kever Yang (2):
usb: dwc2: add bus suspend/resume for dwc2
usb: dwc2: move the clock management from gadget to platform
This patch adds suspend/resume for dwc2 hcd controller.
Signed-off-by: Kever Yang kever.y...@rock-chips.com
---
Changes in v2:
- remove the clock from hcd
- adjust the delay time when resume
drivers/usb/dwc2/hcd.c | 75 ++
1 file changed, 64
This patch move clock management out of gadget into platform,
make both hcd and gadget can use the clock.
Signed-off-by: Kever Yang kever.y...@rock-chips.com
---
Changes in v2:
- move all the clock operation into platform
drivers/usb/dwc2/gadget.c | 24 ++--
drivers/usb
Hi Felipe,
Thank for comment.
On 10/16/2014 06:23 AM, Felipe Balbi wrote:
Hi,
On Wed, Oct 15, 2014 at 10:46:17PM -0700, Kever Yang wrote:
This patch move clock init out of gadget into platform,
make both hcd and gadget can use the clock
Signed-off-by: Kever Yang kever.y...@rock
Hi Felipe,
On 10/16/2014 06:30 AM, Felipe Balbi wrote:
On Wed, Oct 15, 2014 at 10:46:18PM -0700, Kever Yang wrote:
This patch add suspend/resume for dwc2 hcd controller.
adds
Signed-off-by: Kever Yang kever.y...@rock-chips.com
---
drivers/usb/dwc2/hcd.c | 71
This patch add suspend/resume for dwc2 hcd controller.
Signed-off-by: Kever Yang kever.y...@rock-chips.com
---
drivers/usb/dwc2/hcd.c | 71 ++
1 file changed, 60 insertions(+), 11 deletions(-)
diff --git a/drivers/usb/dwc2/hcd.c b/drivers/usb
This patchset add clock manage and suspend/resume for dwc2.
Based on Dinh's patch usb: dwc2: Add support for dual role.
Kever Yang (2):
usb: dwc2: add clock manage for hcd
usb: dwc2: add bus suspend/resume for dwc2
drivers/usb/dwc2/gadget.c | 16 ++
drivers/usb/dwc2/hcd.c
This patch move clock init out of gadget into platform,
make both hcd and gadget can use the clock
Signed-off-by: Kever Yang kever.y...@rock-chips.com
---
drivers/usb/dwc2/gadget.c | 16 ++--
drivers/usb/dwc2/hcd.c | 3 +++
drivers/usb/dwc2/platform.c | 30
This patch add compatible data for dwc2 controller found on
rk3066, rk3188 and rk3288 processors from rockchip.
Signed-off-by: Kever Yang kever.y...@rock-chips.com
Acked-by: Paul Zimmerman pa...@synopsys.com
---
Changes in v4:
- max_transfer_size change to 65536, this should be enough
for most
bingding info
- set most parameters as driver auto-detect
- evb patch added in version 2
Kever Yang (4):
Documentation: dt-bindings: add dt binding info for Rockchip dwc2
usb: dwc2: add compatible data for rockchip soc
ARM: dts: add rk3288 dwc2 controller support
ARM: dts: Enable USB otg
Paul,
On 08/08/2014 02:26 AM, Paul Zimmerman wrote:
From: Kever Yang [mailto:kever.y...@gmail.com] On Behalf Of Kever Yang
Sent: Thursday, August 07, 2014 2:35 AM
This patch add compatible data for dwc2 controller found on
rk3066, rk3188 and rk3288 processors from rockchip.
Signed-off
this value if they use the dwc2
controller.
The way we get the register value here can not make sure this is the
power-on
value which we actually need.
Let me do more test for that, and maybe we need another patch.
Anyway, this patch works and reasonable.
Reviewed-by: Kever Yang kever.y...@rock
This patch add compatible data for dwc2 controller found on
rk3066, rk3188 and rk3288 processors from rockchip.
Signed-off-by: Kever Yang kever.y...@rock-chips.com
Acked-by: Paul Zimmerman pa...@synopsys.com
---
Changes in v5:
- max_transfer_size change to 65535 to met the requirement
had post it seprately.
Changes in v3:
- EHCI and HSIC move new for version 3.
- Rebase
Changes in v2:
- Split out dr_mode and rk3288 bindings.
- add compatible snps,dwc2 bingding info
- set most parameters as driver auto-detect
- evb patch added in version 2
Kever Yang (4):
Documentation: dt
struct
- From Jingoo's suggestion:
change the commit message
- add dr_mode init from Kconfig
Changes in v2:
- Split out dr_mode and rk3288 bindings.
- put spaces around '+' operator
- expand the comment for dr_mode
- handle dr_mode is USB_DR_MODE_OTG
Kever Yang (2):
Documentation: dt
According to the dr_mode, the otg controller can work as
device role and host role. Some boards always want to use host mode
and some other boards want to use gadget mode. We use the dts setting
to set dwc2's mode, rather than fixing it to whatever hardware says.
Signed-off-by: Kever Yang kever.y
According to the dr_mode, the otg controller can work as
device role during firmware period, and work as host role in
the kernel, without use of usb_id pin. As the commit usb: dwc3:
set 'mode' based on selected Kconfig choices.
Signed-off-by: Kever Yang kever.y...@rock-chips.com
---
Changes
bindings.
- put spaces around '+' operator
- expand the comment for dr_mode
- handle dr_mode is USB_DR_MODE_OTG
Kever Yang (2):
Documentation: dt-bindings: add dt binding info for dwc2 dr_mode
usb: dwc2: add 'mode' which based on Kconfig select or dts setting
Documentation/devicetree/bindings
Doug,
On 08/05/2014 12:34 AM, Doug Anderson wrote:
Kever,
On Mon, Aug 4, 2014 at 6:45 AM, Kever Yang kever.y...@rock-chips.com wrote:
According to the dr_mode, the otg controller can work as
device role during firmware period, and work as host role in
the kernel, without use of usb_id pin
and rk3288 bindings.
- add compatible snps,dwc2 bingding info
- set most parameters as driver auto-detect
- change the node name from 'dwc2' to 'usb'
- evb patch added in version 2
Doug Anderson (1):
ARM: dts: Fix the sort ordering of EHCI and HSIC in rk3288.dtsi
Kever Yang (4):
Documentation: dt
This patch add compatible data for dwc2 controller found on
rk3066, rk3188 and rk3288 processors from rockchip.
Signed-off-by: Kever Yang kever.y...@rock-chips.com
Acked-by: Paul Zimmerman pa...@synopsys.com
---
Changes in v3: None
Changes in v2:
- set most parameters as driver auto-detect
in rk3288.dtsi
Kever Yang (4):
Documentation: dt-bindings: add dt binding info for Rockchip dwc2
usb: dwc2: add compatible data for rockchip soc
ARM: dts: add rk3288 dwc2 controller support
ARM: dts: Enable USB otg and host1(dwc) on rk3288-evb
Documentation/devicetree/bindings/usb/dwc2.txt |3
This patch add compatible data for dwc2 controller found on
rk3066, rk3188 and rk3288 processors from rockchip.
Signed-off-by: Kever Yang kever.y...@rock-chips.com
Acked-by: Paul Zimmerman pa...@synopsys.com
---
Changes in v3: None
Changes in v2:
- set most parameters as driver auto-detect
These two patches enable the dr_mode for the dwc2 usb
controller. These are split from the patch series adding
rk3288 dwc2 support.
Changes in v2:
- Split out dr_mode and rk3288 bindings.
- put spaces around '+' operator
- expand the comment for dr_mode
- handle dr_mode is USB_DR_MODE_OTG
Kever
Some devices with A female host port and without use of usb_id pin
will need this for the otg controller works as device role
during firmware period and works as host role in rich os.
Signed-off-by: Kever Yang kever.y...@rock-chips.com
---
Changes in v2:
- put spaces around '+' operator
From: Kever Yang kever.y...@gmail.com
These patches to add support for dwc2 controller found in
Rockchip processors rk3066, rk3188 and rk3288,
and enable dts for rk3288 evb.
Changes in v2:
- Split out dr_mode and rk3288 bindings.
- add compatible snps,dwc2 bingding info
- set most parameters
This patch add compatible data for dwc2 controller found on
rk3066, rk3188 and rk3288 processors from rockchip.
Signed-off-by: Kever Yang kever.y...@rock-chips.com
---
Changes in v2:
- set most parameters as driver auto-detect
drivers/usb/dwc2/platform.c | 29 +
1
This path is to add the support for dwc2 controller found ind
Rockchip processors rk3066, rk3188 and rk3288
This patch also add dr_mode for dwc2 driver.
Kever Yang (4):
Documentation: dt-bindings: add dt binding info for Rockchip dwc2
ARM: dts: add rk3288 dwc2 controller support
usb: dwc2
This add necessary dwc2 binding documentation for Rockchip socs:
rk3066, rk3188 and rk3288
add dr_mode as optional properties.
Signed-off-by: Kever Yang kever.y...@rock-chips.com
---
Documentation/devicetree/bindings/usb/dwc2.txt |5 +
1 file changed, 5 insertions(+)
diff --git
rk3288 has two kind of usb controller, this add the dwc2 controller
for otg and host1.
Controller can works with usb PHY default setting and Vbus on.
Signed-off-by: Kever Yang kever.y...@rock-chips.com
---
arch/arm/boot/dts/rk3288.dtsi | 20
1 file changed, 20 insertions
This patch add compatible data for dwc2 controller found on
rk3066, rk3188 and rk3288 processors from rockchip.
Signed-off-by: Kever Yang kever.y...@rock-chips.com
---
drivers/usb/dwc2/platform.c | 29 +
1 file changed, 29 insertions(+)
diff --git a/drivers/usb
Some devices with A female host port and without use of usb_id pin
will need this for the otg controller works as device role
during firmware period and works as host role in rich os.
Signed-off-by: Kever Yang kever.y...@rock-chips.com
---
drivers/usb/dwc2/core.c | 13
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