Hi,
On Thu, Mar 29, 2018 at 01:57:24PM +0200, Paul Kocialkowski wrote:
> On Thu, 2018-03-29 at 11:23 +0200, Maxime Ripard wrote:
> > On Wed, Mar 28, 2018 at 11:52:13PM +0200, Paul Kocialkowski wrote:
> > > This allows dual-role ports to be reported as
gned-off-by: Paul Kocialkowski <cont...@paulk.fr>
Surely there's more to it than that. The gadget mode of A20 boards
have been working in the past, including when compiling with mUSB
setup as dual role.
Is this a regression since a particular commit? Or is there another,
deeper issue overlooked in
line kernel or a way to
> make that device work?
https://linux-sunxi.org/Wifi#RTL8189ES_.2F_RTL8189ETV
Maxime
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On Wed, Jan 18, 2017 at 04:09:32AM +0800, Chen-Yu Tsai wrote:
> Hi,
>
> On Wed, Jan 18, 2017 at 4:06 AM, Maxime Ripard
> <maxime.rip...@free-electrons.com> wrote:
> > On Wed, Jan 18, 2017 at 12:57:08AM +0800, Icenowy Zheng wrote:
> >>
> >>
> >
On Wed, Jan 18, 2017 at 12:57:08AM +0800, Icenowy Zheng wrote:
>
>
> 17.01.2017, 16:06, "Maxime Ripard" <maxime.rip...@free-electrons.com>:
> > On Tue, Jan 17, 2017 at 03:14:46AM +0800, Icenowy Zheng wrote:
> >> The PHY0 on H3 can be wired either to MUSB
at? What's wrong with it?
Maxime
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Hi Bin,
On Thu, Jan 12, 2017 at 08:50:14AM -0600, Bin Liu wrote:
> On Wed, Jan 11, 2017 at 10:06:38PM +0100, Maxime Ripard wrote:
> > On Wed, Jan 11, 2017 at 02:08:11PM -0600, Bin Liu wrote:
> > > On Thu, Jan 12, 2017 at 03:55:33AM +0800, Icenowy Zheng wrote:
> > > >
> Why not set this default mode in dtsi instead?
> > >
> > > Regards,
> > > -Bin.
> >
> > There's possibly boards which do not have OTG functions.
>
> That is board specific.
Exactly, and this is why it should be done in the board DT.
The controller in the Allwinner SoCs do not handle directly the ID pin
and VBUS, but rather rely on a GPIO to do so.
So boards with OTG will need setup anyway, at least to tell which
GPIOs are used. There's no point in enforcing a default if it doesn't
work by default.
Maxime
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On Tue, Jan 03, 2017 at 11:25:31PM +0800, Icenowy Zheng wrote:
> Allwinner V3s come with a USB PHY controller slightly different to other
> SoCs, with only one PHY.
>
> Add support for it.
>
> Signed-off-by: Icenowy Zheng <icen...@aosc.xyz>
Acked-by: Maxime Ri
On Tue, Jan 03, 2017 at 11:25:32PM +0800, Icenowy Zheng wrote:
> Allwinner H3/V3s features a variant of MUSB controller, which lacks one
> endpoint.
>
> Add support for it.
>
> Signed-off-by: Icenowy Zheng <icen...@aosc.xyz>
Acked-by: Maxime Ripard <maxime.rip...@
On Tue, Jan 03, 2017 at 11:25:33PM +0800, Icenowy Zheng wrote:
> V3s SoC features a USB PHY controller and a MUSB OTG controller.
>
> Add device nodes for them.
>
> Signed-off-by: Icenowy Zheng <icen...@aosc.xyz>
This can be merged in your other DTSI patch.
Maxime
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On Wed, Nov 30, 2016 at 02:57:35PM +0900, Chanwoo Choi wrote:
> This patch just uses the resource-managed extcon API when registering
> the extcon notifier.
>
> Signed-off-by: Chanwoo Choi <cw00.c...@samsung.com>
Acked-by: Maxime Ripard <maxime.rip...@free-electrons
Hi,
On Wed, Jun 08, 2016 at 12:30:20PM +0200, Hans de Goede wrote:
> Hi,
>
> On 08-06-16 12:23, Maxime Ripard wrote:
> >Hi,
> >
> >On Sun, Jun 05, 2016 at 04:59:36PM +0200, Hans de Goede wrote:
> >>phy-sun4i-usb now has proper dr_mode handling, it alway
nful to track all the patches needed so that it
applies properly, but I've finally been able to test it on a Sinlinx
SinA33 with peripheral-only mUSB, and it works like a charm.
You can add my Tested-by.
Thanks!
Maxime
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That would be allwinner in this case, sunxi is the SoC family
Allwinner produces.
Maxime
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On Wed, Dec 16, 2015 at 12:21:48PM +0100, Philipp Zabel wrote:
> Hi Maxime,
>
> Am Mittwoch, den 16.12.2015, 11:29 +0100 schrieb Maxime Ripard:
> > On Mon, Dec 14, 2015 at 10:50:55AM +0100, Philipp Zabel wrote:
> > > Am Montag, den 14.12.2015, 10:36 +0100 schrieb M
On Mon, Dec 14, 2015 at 10:50:55AM +0100, Philipp Zabel wrote:
> Am Montag, den 14.12.2015, 10:36 +0100 schrieb Maxime Ripard:
> > Hi,
> >
> > On Fri, Dec 11, 2015 at 04:41:58PM +0100, Hans de Goede wrote:
> > > diff --git a/include/linux/reset.h b/include/lin
e pattern used everywhere else
(irqs, regulator, clocks, etc.), so it's going to be easier to review
as well.
Maxime
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t/sunxi_hci.c#L899
>
> Notice how it uses different addr and write register addresses
> their through the usb_phy_csr_add and usb_phy_csr_write helper
> functions as well as directly poking offset 0x20.
Then it easy to support: one u8 for each register that changes, one
bool to tell if you need to clear the phyctl register or not, And you
don't have to duplicate the switch everywhere, and basically just
reimplement of_device_is_compatible without an actual compatible to
workaround the review ;)
Maxime
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? It would be really good to be able to
> move forward with this, how do you want to proceed ?
Yeah, sorry, Chen-Yu and I were busy because of $LIFE the past weeks,
we're getting back to speed.
Maxime
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om>
>
> Acked-by: Chen-Yu Tsai <w...@csie.org>
Applied, thanks!
Maxime
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ared bool is true
I don't think silently failing (at least from the driver point of
view) is the right approach. You've used clocks as an example, but
there's a quite significant difference between clocks and reset lines:
you never really care if the clock is actually disabled or not while
eassert will deassert the reset, whether
> you count or not.
> But if the two drivers have deasserted an initially asserted reset, a
> reset_control_assert for one of them will silently fail.
Then maybe we can just make it return an error when someone calls
_assert or _reset on a reset lin
ushback.
>
> This patch series has stack on review due to different views
> on checking input parameters of externally visible function.
>
> I see there is no any way to get these patches accepted other
> than skip checking validity of some input parameters as
> was pointed by A
They're fixing some real
issue that we're seeing, and it seems to both work quite well and not
generate a lot of pushback.
Thanks!
Maxime
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On Thu, Sep 10, 2015 at 08:38:38PM +0200, Hans de Goede wrote:
> Hi,
>
> On 10-09-15 20:30, Maxime Ripard wrote:
> >On Thu, Sep 10, 2015 at 08:23:23PM +0200, Hans de Goede wrote:
> >>Hi,
> >>
> >>On 04-09-15 08:43, Olliver Schinagl wrote:
> >&
't really followed the rest of the discussion, so sorry if you
already talked about that, but why can't you just set the dr_mode to
peripheral in such a case?
Maxime
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Hi,
On Mon, Jun 01, 2015 at 11:28:23AM +0200, Hans de Goede wrote:
On 01-06-15 11:22, Maxime Ripard wrote:
On Sun, May 31, 2015 at 06:10:25PM +0200, Hans de Goede wrote:
+ /* We either want both gpio pins or neither (when in host mode) */
+ if (!data-id_det_gpio != !data-vbus_det_gpio
;
+ }
The fact that the driver expects both to be set if one is should be in
the binding documentation.
Maxime
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On Tue, Apr 21, 2015 at 01:46:36PM +0300, Roger Quadros wrote:
On 21/04/15 11:08, Maxime Ripard wrote:
On Tue, Apr 21, 2015 at 12:49:54PM +0300, Roger Quadros wrote:
On 20/04/15 15:35, Mathias Nyman wrote:
Hi
On 02.04.2015 15:23, Roger Quadros wrote:
As xhci_hcd is now allocated
() is already handling the phy for us.
If it handles USB phy, then I don't really have an issue with it.
Maxime
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Hi,
On Thu, Feb 05, 2015 at 02:21:42PM +0100, Maxime Ripard wrote:
Hi,
On Thu, Jan 22, 2015 at 08:37:45AM +0100, Yegor Yefremov wrote:
I have the same experience with 3.15. The switching is working when
CONFIG_USB_MUSB_DUAL_ROLE is set and dr_mode = otg. But since 3.16
it seems
the SRAM controller patches are in next we can also merge
the musb: Add support for the Allwinner sunxi musb commit and the dts
changes.
All the DT bits look fine to me. I'll wait for Felipe and Kishon
comments before merging those.
Thanks!
Maxime
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with this using syscon?
(see above for my arguments why)
If you can address my objections above, sure.
Thanks for your awesome work on this,
Maxime
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= pio 7 5 GPIO_ACTIVE_HIGH; /* PH5 */
+ dr_mode = otg;
Is there a reason to not put that in the DTSI?
All the users seem to be wiring it as OTG.
Thanks!
Maxime
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On Tue, Mar 10, 2015 at 04:23:09PM +0100, Hans de Goede wrote:
Hi,
On 03/10/2015 04:07 PM, Maxime Ripard wrote:
Hi Hans,
On Mon, Mar 09, 2015 at 09:40:25PM +0100, Hans de Goede wrote:
Enable the otg/drc usb controller on the Chuwi V7 CW0825 tablet.
Signed-off-by: Hans de Goede hdego
Hi Matthias,
On Tue, Mar 03, 2015 at 06:12:44PM +0200, Mathias Nyman wrote:
On 03.03.2015 11:59, Maxime Ripard wrote:
On Mon, Mar 02, 2015 at 08:23:37PM +0100, Gregory CLEMENT wrote:
Hi Maxime,
On 19/01/2015 14:01, Maxime Ripard wrote:
The Armada 385 AP board has a USB3 port exposed
On Mon, Mar 02, 2015 at 08:23:37PM +0100, Gregory CLEMENT wrote:
Hi Maxime,
On 19/01/2015 14:01, Maxime Ripard wrote:
The Armada 385 AP board has a USB3 port exposed that uses a GPIO to drive
the
VBUS line. Enable the needed drivers to support this.
it seems that this patch
On Tue, Feb 24, 2015 at 11:33:57AM -0600, Felipe Balbi wrote:
Hi,
On Tue, Feb 24, 2015 at 05:50:50PM +0100, Maxime Ripard wrote:
Hi Felipe,
On Tue, Feb 24, 2015 at 08:54:01AM -0600, Felipe Balbi wrote:
Hi,
On Tue, Feb 24, 2015 at 11:39:11AM +0100, Maxime Ripard wrote
On Thu, Feb 05, 2015 at 02:21:42PM +0100, Maxime Ripard wrote:
Hi,
On Thu, Jan 22, 2015 at 08:37:45AM +0100, Yegor Yefremov wrote:
I have the same experience with 3.15. The switching is working when
CONFIG_USB_MUSB_DUAL_ROLE is set and dr_mode = otg. But since 3.16
it seems to be broken
Hi Felipe,
On Tue, Feb 24, 2015 at 08:54:01AM -0600, Felipe Balbi wrote:
Hi,
On Tue, Feb 24, 2015 at 11:39:11AM +0100, Maxime Ripard wrote:
On Thu, Feb 05, 2015 at 02:21:42PM +0100, Maxime Ripard wrote:
Hi,
On Thu, Jan 22, 2015 at 08:37:45AM +0100, Yegor Yefremov wrote:
I have
On Wed, Feb 04, 2015 at 05:04:18AM -0800, Greg Kroah-Hartman wrote:
On Wed, Feb 04, 2015 at 10:35:22AM +0100, Maxime Ripard wrote:
Hi Mathias, Greg,
On Mon, Jan 19, 2015 at 02:01:12PM +0100, Maxime Ripard wrote:
The commit 973747928514 (usb: host: xhci-plat: add support for the Armada
cable, with the AM335x acting as a device
work once. Then, when it switches to the host mode, we end up with
the same scenario than in the coldplug as gadget case: USB read
error, before then having all the a_wait_vfall messages.
Maxime
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Hi Mathias, Greg,
On Mon, Jan 19, 2015 at 02:01:12PM +0100, Maxime Ripard wrote:
The commit 973747928514 (usb: host: xhci-plat: add support for the Armada
375/38x XHCI controllers) extended the xhci-plat driver to support the Armada
375/38x SoCs, mostly by adding a quirk configuring the MBUS
Hi Markus,
On Thu, Jan 22, 2015 at 12:01:13PM +0100, Markus Pargmann wrote:
Hi,
On Thu, Jan 22, 2015 at 11:43:30AM +0100, Maxime Ripard wrote:
Hi Yegor,
On Thu, Jan 22, 2015 at 08:37:45AM +0100, Yegor Yefremov wrote:
On 21.01.2015 19:53, Bin Liu wrote:
Hi,
On Wed, Jan
Hi Yegor,
On Thu, Jan 22, 2015 at 08:37:45AM +0100, Yegor Yefremov wrote:
On 21.01.2015 19:53, Bin Liu wrote:
Hi,
On Wed, Jan 21, 2015 at 10:06 AM, Maxime Ripard
maxime.rip...@free-electrons.com wrote:
Hi Felipe,
I'm currently working on a custom AM335x-based board, that has a OTG
in the driver nor the datasheet.
Have you already experienced something alike with that driver?
Thanks,
Maxime
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On Tue, Jan 20, 2015 at 09:43:07PM +0100, Andrew Lunn wrote:
On Tue, Jan 20, 2015 at 09:30:28PM +0100, Maxime Ripard wrote:
Hi Andrew,
On Mon, Jan 19, 2015 at 10:35:07PM +0100, Andrew Lunn wrote:
On Mon, Jan 19, 2015 at 02:01:11PM +0100, Maxime Ripard wrote:
Hi all
Hi Andrew,
On Mon, Jan 19, 2015 at 10:35:07PM +0100, Andrew Lunn wrote:
On Mon, Jan 19, 2015 at 02:01:11PM +0100, Maxime Ripard wrote:
Hi all,
This serie enables the Armada 385 AP XHCI controller.
Since the controller uses a GPIO-controlled VBUS, we used the
phy-generic driver
error path, the driver will rightfully disable the clock. When the
driver will be reprobed, it will retry to access the MBUS registers, but this
time with the clock disabled, which hangs forever.
Fix this by running the quirks after the clock has been enabled by the driver.
Signed-off-by: Maxime
The Marvell Armada 385 AP needs a dumb phy in order to enable the USB3 VBUS.
Add a call to retrieve a USB PHY to XHCI plat in order to support this.
Signed-off-by: Maxime Ripard maxime.rip...@free-electrons.com
---
drivers/usb/host/xhci-plat.c | 19 ++-
1 file changed, 18
The Armada 385 AP board has a USB3 port exposed that uses a GPIO to drive the
VBUS line. Enable the needed drivers to support this.
Signed-off-by: Maxime Ripard maxime.rip...@free-electrons.com
---
arch/arm/boot/dts/armada-385-db-ap.dts | 28
1 file changed, 28
The Armada 385 AP board has a USB3 port exposed that uses a GPIO to drive the
VBUS line. Enable the needed drivers to support this.
Signed-off-by: Maxime Ripard maxime.rip...@free-electrons.com
---
arch/arm/boot/dts/armada-385-ap.dts | 28
1 file changed, 28
The Marvell Armada 385 AP needs a dumb phy in order to enable the USB3 VBUS.
Add a call to retrieve a USB PHY to XHCI plat in order to support this.
Signed-off-by: Maxime Ripard maxime.rip...@free-electrons.com
---
drivers/usb/host/xhci-plat.c | 13 +
drivers/usb/host/xhci.h
error path, the driver will rightfully disable the clock. When the
driver will be reprobed, it will retry to access the MBUS registers, but this
time with the clock disabled, which hangs forever.
Fix this by running the quirks after the clock has been enabled by the driver.
Signed-off-by: Maxime
, and ENODEV if try_module_get fails.
Signed-off-by: Maxime Ripard maxime.rip...@free-electrons.com
---
drivers/usb/phy/phy.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/drivers/usb/phy/phy.c b/drivers/usb/phy/phy.c
index b4066a001ba0..353c686498d4 100644
--- a/drivers/usb
for the the A385 AP board.
Thanks,
Maxime
Maxime Ripard (4):
usb: phy: Fix deferred probing
usb: XHCI: platform: Move the Marvell quirks after the enabling the
clocks
usb: xhci: plat: Add USB phy support
ARM: mvebu: armada-385-ap: Enable USB3 port
arch/arm/boot/dts/armada-385-ap.dts
On Tue, May 27, 2014 at 03:53:18PM -0700, Greg Kroah-Hartman wrote:
On Thu, May 15, 2014 at 11:14:38AM +0200, Maxime Ripard wrote:
Hi Greg,
On Wed, May 14, 2014 at 06:05:20PM +0200, Greg Kroah-Hartman wrote:
On Wed, May 14, 2014 at 02:34:19PM +0200, Maxime Ripard wrote:
On Tue, May
On Sat, May 24, 2014 at 07:19:40AM +0900, Greg Kroah-Hartman wrote:
On Fri, May 23, 2014 at 08:33:39PM +0200, Maxime Ripard wrote:
Hi Greg,
On Wed, May 14, 2014 at 06:05:20PM +0200, Greg Kroah-Hartman wrote:
On Wed, May 14, 2014 at 02:34:19PM +0200, Maxime Ripard wrote:
On Tue, May
Hi Greg,
On Wed, May 14, 2014 at 06:05:20PM +0200, Greg Kroah-Hartman wrote:
On Wed, May 14, 2014 at 02:34:19PM +0200, Maxime Ripard wrote:
On Tue, May 13, 2014 at 05:44:14PM +0200, Maxime Ripard wrote:
Hi everyone,
This patchset adds support for the USB controllers found
Hi Greg,
On Wed, May 14, 2014 at 06:05:20PM +0200, Greg Kroah-Hartman wrote:
On Wed, May 14, 2014 at 02:34:19PM +0200, Maxime Ripard wrote:
On Tue, May 13, 2014 at 05:44:14PM +0200, Maxime Ripard wrote:
Hi everyone,
This patchset adds support for the USB controllers found
On Wed, May 14, 2014 at 11:18:51AM +0530, Kishon Vijay Abraham I wrote:
Hi,
On Tuesday 13 May 2014 09:14 PM, Maxime Ripard wrote:
Move the phy initialization and variables declaration to the loop itself,
since
it is where it really belongs. Also remove all the temporary variables, we
},
{ .compatible = allwinner,sun5i-a13-usb-phy },
+ { .compatible = allwinner,sun6i-a31-usb-phy },
Do you have Documentation for this comptible binding? Would be good to mention
that in the commit log.
Ah right. I forgot.
I'm sending you a followup patch.
Thanks!
Maxime
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On Tue, May 13, 2014 at 05:44:14PM +0200, Maxime Ripard wrote:
Hi everyone,
This patchset adds support for the USB controllers found in the
Allwinner A31.
While the design is similar to the earlier Allwinner SoCs that are
already supported, a few details here and there change, like
On Mon, May 12, 2014 at 04:06:16PM -0400, Alan Stern wrote:
On Mon, 12 May 2014, Maxime Ripard wrote:
From: Boris BREZILLON boris.brezil...@free-electrons.com
On the Allwinner's A31 SoC the reset line connected to the EHCI IP has to
be deasserted for the EHCI block to be usable
-electrons.com
Signed-off-by: Maxime Ripard maxime.rip...@free-electrons.com
Reviewed-by: Hans de Goede hdego...@redhat.com
---
arch/arm/boot/dts/Makefile| 1 +
arch/arm/boot/dts/sun6i-a31-app4-evb1.dts | 57 +++
2 files changed, 58 insertions(+)
create mode
The A31 has two ECHI/OHCI controllers, and one OHCI-only phy-less controller.
Signed-off-by: Maxime Ripard maxime.rip...@free-electrons.com
Reviewed-by: Hans de Goede hdego...@redhat.com
---
arch/arm/boot/dts/sun6i-a31.dtsi | 77
1 file changed, 77
function instead of the
private structure since it was the only user
Boris BREZILLON (2):
usb: ehci-platform: add optional reset controller retrieval
ARM: sunxi: dt: add APP4-EVB1 board support
Maxime Ripard (6):
clk: sunxi: Implement A31 USB clock
ARM: sun6i: Add the USB clocks to the DTSI
The OHCI controllers used in the Allwinner A31 are asserted in reset using a
global reset controller.
Add optional support for such a controller in the OHCI platform driver.
Signed-off-by: Maxime Ripard maxime.rip...@free-electrons.com
Reviewed-by: Hans de Goede hdego...@redhat.com
The A31 USB clock slightly differ from its older counterparts, mostly because
it has a different gate for each PHY, while the older one had a single gate for
all the phy.
Signed-off-by: Maxime Ripard maxime.rip...@free-electrons.com
Reviewed-by: Hans de Goede hdego...@redhat.com
Acked-by: Mike
-off-by: Boris BREZILLON boris.brezil...@free-electrons.com
Signed-off-by: Maxime Ripard maxime.rip...@free-electrons.com
Reviewed-by: Hans de Goede hdego...@redhat.com
---
Documentation/devicetree/bindings/usb/usb-ehci.txt | 1 +
drivers/usb/host/ehci-platform.c | 26
Move the phy initialization and variables declaration to the loop itself, since
it is where it really belongs. Also remove all the temporary variables, we can
use the structure members directly.
Signed-off-by: Maxime Ripard maxime.rip...@free-electrons.com
Reviewed-by: Hans de Goede hdego
The USB clocks of the A31 seems to be parented to the 24MHz oscillator, and
handle the clocks for the USB phys and OHCI devices.
Signed-off-by: Maxime Ripard maxime.rip...@free-electrons.com
Reviewed-by: Hans de Goede hdego...@redhat.com
---
arch/arm/boot/dts/sun6i-a31.dtsi | 11 +++
1
The USB phy controller in the A31 differs mostly from the older controllers
because it has a clock dedicated for each phy, while the older ones were having
a single clock for all the phys.
Signed-off-by: Maxime Ripard maxime.rip...@free-electrons.com
Reviewed-by: Hans de Goede hdego...@redhat.com
The A31 USB clock slightly differ from its older counterparts, mostly because
it has a different gate for each PHY, while the older one had a single gate for
all the phy.
Signed-off-by: Maxime Ripard maxime.rip...@free-electrons.com
Reviewed-by: Hans de Goede hdego...@redhat.com
Acked-by: Mike
The OHCI controllers used in the Allwinner A31 are asserted in reset using a
global reset controller.
Add optional support for such a controller in the OHCI platform driver.
Signed-off-by: Maxime Ripard maxime.rip...@free-electrons.com
Reviewed-by: Hans de Goede hdego...@redhat.com
Acked
The USB clocks of the A31 seems to be parented to the 24MHz oscillator, and
handle the clocks for the USB phys and OHCI devices.
Signed-off-by: Maxime Ripard maxime.rip...@free-electrons.com
Reviewed-by: Hans de Goede hdego...@redhat.com
---
arch/arm/boot/dts/sun6i-a31.dtsi | 11 +++
1
The A31 has two ECHI/OHCI controllers, and one OHCI-only phy-less controller.
Signed-off-by: Maxime Ripard maxime.rip...@free-electrons.com
Reviewed-by: Hans de Goede hdego...@redhat.com
---
arch/arm/boot/dts/sun6i-a31.dtsi | 77
1 file changed, 77
-off-by: Boris BREZILLON boris.brezil...@free-electrons.com
Signed-off-by: Maxime Ripard maxime.rip...@free-electrons.com
Reviewed-by: Hans de Goede hdego...@redhat.com
Acked-by: Alan Stern st...@rowland.harvard.edu
---
Documentation/devicetree/bindings/usb/usb-ehci.txt | 1 +
drivers/usb/host/ehci
assertion/deassertion to probe/remove
- Moved the dedicated_clocks to the probe function instead of the
private structure since it was the only user
Boris BREZILLON (2):
usb: ehci-platform: add optional reset controller retrieval
ARM: sunxi: dt: add APP4-EVB1 board support
Maxime Ripard
-electrons.com
Signed-off-by: Maxime Ripard maxime.rip...@free-electrons.com
Reviewed-by: Hans de Goede hdego...@redhat.com
---
arch/arm/boot/dts/Makefile| 1 +
arch/arm/boot/dts/sun6i-a31-app4-evb1.dts | 57 +++
2 files changed, 58 insertions(+)
create mode
The USB phy controller in the A31 differs mostly from the older controllers
because it has a clock dedicated for each phy, while the older ones were having
a single clock for all the phys.
Signed-off-by: Maxime Ripard maxime.rip...@free-electrons.com
Reviewed-by: Hans de Goede hdego...@redhat.com
Move the phy initialization and variables declaration to the loop itself, since
it is where it really belongs. Also remove all the temporary variables, we can
use the structure members directly.
Signed-off-by: Maxime Ripard maxime.rip...@free-electrons.com
Reviewed-by: Hans de Goede hdego
. Is there any reason not to put the new code
outside the if statement, so it applies to all devices?
Hmmm, I did this because so far, the reset framework only handles the
DT case. But that's right that it can be extended in the future, I'll
update it.
Thanks!
Maxime
--
Maxime Ripard, Free
On Mon, May 12, 2014 at 05:14:26PM +0800, Chen-Yu Tsai wrote:
Hi,
On Sat, May 10, 2014 at 8:56 PM, Maxime Ripard
maxime.rip...@free-electrons.com wrote:
The USB phy controller in the A31 differs mostly from the older controllers
because it has a clock dedicated for each phy, while
The USB phy controller in the A31 differs mostly from the older controllers
because it has a clock dedicated for each phy, while the older ones were having
a single clock for all the phys.
Signed-off-by: Maxime Ripard maxime.rip...@free-electrons.com
Reviewed-by: Hans de Goede hdego...@redhat.com
The OHCI controllers used in the Allwinner A31 are asserted in reset using a
global reset controller.
Add optional support for such a controller in the OHCI platform driver.
Signed-off-by: Maxime Ripard maxime.rip...@free-electrons.com
Reviewed-by: Hans de Goede hdego...@redhat.com
retrieval
ARM: sunxi: dt: add APP4-EVB1 board support
Maxime Ripard (6):
clk: sunxi: Implement A31 USB clock
ARM: sun6i: Add the USB clocks to the DTSI.
phy: sunxi: Rework phy initialization
phy: usb: sunxi: Introduce Allwinner A31 USB PHY support
usb: ohci-platform: Enable optional use
-electrons.com
Signed-off-by: Maxime Ripard maxime.rip...@free-electrons.com
Reviewed-by: Hans de Goede hdego...@redhat.com
---
arch/arm/boot/dts/Makefile| 1 +
arch/arm/boot/dts/sun6i-a31-app4-evb1.dts | 57 +++
2 files changed, 58 insertions(+)
create mode
-off-by: Boris BREZILLON boris.brezil...@free-electrons.com
Signed-off-by: Maxime Ripard maxime.rip...@free-electrons.com
Reviewed-by: Hans de Goede hdego...@redhat.com
---
Documentation/devicetree/bindings/usb/usb-ehci.txt | 1 +
drivers/usb/host/ehci-platform.c | 17
The A31 has two ECHI/OHCI controllers, and one OHCI-only phy-less controller.
Signed-off-by: Maxime Ripard maxime.rip...@free-electrons.com
Reviewed-by: Hans de Goede hdego...@redhat.com
---
arch/arm/boot/dts/sun6i-a31.dtsi | 77
1 file changed, 77
Move the phy initialization and variables declaration to the loop itself, since
it is where it really belongs. Also remove all the temporary variables, we can
use the structure members directly.
Signed-off-by: Maxime Ripard maxime.rip...@free-electrons.com
---
drivers/phy/phy-sun4i-usb.c | 44
The USB clocks of the A31 seems to be parented to the 24MHz oscillator, and
handle the clocks for the USB phys and OHCI devices.
Signed-off-by: Maxime Ripard maxime.rip...@free-electrons.com
Reviewed-by: Hans de Goede hdego...@redhat.com
---
arch/arm/boot/dts/sun6i-a31.dtsi | 11 +++
1
The A31 USB clock slightly differ from its older counterparts, mostly because
it has a different gate for each PHY, while the older one had a single gate for
all the phy.
Signed-off-by: Maxime Ripard maxime.rip...@free-electrons.com
Reviewed-by: Hans de Goede hdego...@redhat.com
---
drivers/clk
-electrons.com
Signed-off-by: Maxime Ripard maxime.rip...@free-electrons.com
Reviewed-by: Hans de Goede hdego...@redhat.com
---
arch/arm/boot/dts/Makefile| 1 +
arch/arm/boot/dts/sun6i-a31-app4-evb1.dts | 57 +++
2 files changed, 58 insertions(+)
create mode
The A31 has two ECHI/OHCI controllers, and one OHCI-only phy-less controller.
Signed-off-by: Maxime Ripard maxime.rip...@free-electrons.com
Reviewed-by: Hans de Goede hdego...@redhat.com
---
arch/arm/boot/dts/sun6i-a31.dtsi | 77
1 file changed, 77
-off-by: Boris BREZILLON boris.brezil...@free-electrons.com
Signed-off-by: Maxime Ripard maxime.rip...@free-electrons.com
Reviewed-by: Hans de Goede hdego...@redhat.com
---
Documentation/devicetree/bindings/usb/usb-ehci.txt | 1 +
drivers/usb/host/ehci-platform.c | 18
controller retrieval
ARM: sunxi: dt: add APP4-EVB1 board support
Maxime Ripard (5):
clk: sunxi: Implement A31 USB clock
ARM: sun6i: Add the USB clocks to the DTSI.
phy: usb: sunxi: Introduce Allwinner A31 USB PHY support
usb: ohci-platform: Enable optional use of reset controller
ARM: sun6i
The USB clocks of the A31 seems to be parented to the 24MHz oscillator, and
handle the clocks for the USB phys and OHCI devices.
Signed-off-by: Maxime Ripard maxime.rip...@free-electrons.com
Reviewed-by: Hans de Goede hdego...@redhat.com
---
arch/arm/boot/dts/sun6i-a31.dtsi | 11 +++
1
The USB phy controller in the A31 differs mostly from the older controllers
because it has a clock dedicated for each phy, while the older ones were having
a single clock for all the phys.
Signed-off-by: Maxime Ripard maxime.rip...@free-electrons.com
Reviewed-by: Hans de Goede hdego...@redhat.com
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