On 28-11-18, 13:15, Peter Ujfalusi wrote:
>
>
> On 12/11/2018 17.40, Bin Liu wrote:
>
> Can you fix up the subject line to:
> dmaengine: ti: cppi4: delete channel from pending list when stop channel
>
> > The driver defines three states for a cppi channel.
> > - idle: .chan_busy == 0 && not in
On 12-11-18, 09:43, Bin Liu wrote:
> The driver defines three states for a cppi channel.
> - idle: .chan_busy == 0 && not in .pending list
> - pending: .chan_busy == 0 && in .pending list
> - busy: .chan_busy == 1 && not in .pending list
>
> There are cases in which the cppi channel could be in
to verify both direction it turned
> out that the setup was incorrect:
> omap_desc members are settings for the slave port while the omap_sg members
> apply to the memory side of the sDMA setup.
Acked-by: Vinod Koul <vinod.k...@intel.com>
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On Wed, Apr 05, 2017 at 06:35:16PM +0200, Alexandre Bailon wrote:
> This fix an Oops happening on all platforms using the old dt bindings
> (all platforms but da8xx).
> This update cppi41_dma_probe() to use the index variable which is
> required to keep compatibility between old and new dt
On Mon, Jan 30, 2017 at 06:49:18PM +0100, Alexandre Bailon wrote:
> This series add support of DA8xx to CPPI 4.1 driver.
> As the CPPI 4.1 is now generic, we only had to add the glue for DA8xx.
Applied this one as well, thanks
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On Wed, Feb 15, 2017 at 02:56:31PM +0100, Alexandre Bailon wrote:
> This series intend to make the CPPI 4.1 more generic in order to
> add a new platform (the DA8xx).
> To achieve that, all the IRQ code present in CPPI 4.1 driver has been moved
> to MUSB DSPS driver.
> Other changes mainly update
On Wed, Feb 15, 2017 at 02:56:31PM +0100, Alexandre Bailon wrote:
> This series intend to make the CPPI 4.1 more generic in order to
> add a new platform (the DA8xx).
> To achieve that, all the IRQ code present in CPPI 4.1 driver has been moved
> to MUSB DSPS driver.
> Other changes mainly update
and accesses to USBSS's register, which making CPPI 4.1 driver not
> really generic.
> Move the interrupt management to DSPS driver.
>
> Signed-off-by: Alexandre Bailon <abai...@baylibre.com>
> ---
> drivers/dma/cppi41.c | 28 ++++---
Acked-by: Vinod Kou
On Thu, Jan 19, 2017 at 08:49:06AM -0800, Tony Lindgren wrote:
> Hi all,
>
> I'm using v4 naming here as the earlier patch "dmaengine: cppi41: Add dma
> support to da8xx" has been separated from the error -115 issue. We've
> identified so far three musb and cppi41 regressions:
>
> 1. Error -71
On Thu, Jan 19, 2017 at 08:49:06AM -0800, Tony Lindgren wrote:
> Hi all,
>
> I'm using v4 naming here as the earlier patch "dmaengine: cppi41: Add dma
> support to da8xx" has been separated from the error -115 issue. We've
> identified so far three musb and cppi41 regressions:
Hi,
Can we get
On Wed, Nov 16, 2016 at 10:24:15AM -0800, Tony Lindgren wrote:
> Fix use of u32 instead of int for checking for negative errors values
> as pointed out by Dan Carpenter .
>
> And while testing the PM runtime error path by randomly returning
> failed values in runtime
On Mon, Nov 14, 2016 at 06:49:12AM -0800, Tony Lindgren wrote:
> * Vinod Koul <vinod.k...@intel.com> [161113 21:19]:
> > On Wed, Nov 09, 2016 at 09:47:57AM -0700, Tony Lindgren wrote:
> > > Hi,
> > >
> > > I found two pm runtime
On Wed, Nov 09, 2016 at 09:47:57AM -0700, Tony Lindgren wrote:
> Hi,
>
> I found two pm runtime issues when testing with usb on beaglebone.
>
> In the am335x case cppi41 and two instances of musb controller share
> the same interconnect wrapper module, so any pm issues with musb or
> cppi41 will
On Tue, Sep 13, 2016 at 10:22:43AM -0700, Tony Lindgren wrote:
> We can occasionally get -EINPROGRESS for pm_runtime_get. In that case
> we can just continue as we're queueing transfers anyways when
> pm_runtime_active is not set.
Applied, thanks
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On Wed, Aug 31, 2016 at 07:30:55AM -0700, Tony Lindgren wrote:
> * Vinod Koul <vinod.k...@intel.com> [160830 21:45]:
> > On Fri, Aug 19, 2016 at 03:59:40PM -0700, Tony Lindgren wrote:
> > > Let's keep the device enabled between
On Fri, Aug 19, 2016 at 03:59:39PM -0700, Tony Lindgren wrote:
> Let's just move code from cppi41_dma_issue_pending() to
> push_desc_queue() as that's the only call to push_desc_queue().
>
> We want to do this for PM runtime as we need to call push_desc_queue()
> also for pending queued transfers
On Fri, Aug 19, 2016 at 03:59:40PM -0700, Tony Lindgren wrote:
> Let's keep the device enabled between cppi41_dma_issue_pending()
> and dmaengine_desc_get_callback_invoke() and rely on the PM runtime
> autoidle timeout elsewhere.
>
> As the PM runtime is for whole device, not for each channel,
>
On Mon, Aug 22, 2016 at 07:21:48AM -0700, Tony Lindgren wrote:
> Hi,
>
> * Vinod Koul <vinod.k...@intel.com> [160821 23:34]:
> > On Fri, Aug 19, 2016 at 03:59:40PM -0700, Tony Lindgren wrote:
> > @@ -349,6 +358,12 @@ static dma_cookie_t cppi41_tx_submit(struct
>
On Fri, Aug 19, 2016 at 03:59:40PM -0700, Tony Lindgren wrote:
> Let's keep the device enabled between cppi41_dma_issue_pending()
> and dmaengine_desc_get_callback_invoke() and rely on the PM runtime
> autoidle timeout elsewhere.
>
> As the PM runtime is for whole device, not for each channel,
>
On Sun, Feb 21, 2016 at 10:26:35PM -0300, Emilio López wrote:
> From: Emilio López
>
> MODULE_DEVICE_TABLE() is missing, so the module isn't auto-loading on
> supported systems. This commit adds the missing line so it loads
> automatically when building it as a
On Wed, Apr 08, 2015 at 11:45:42AM -0500, Felipe Balbi wrote:
Add missing directions, residue_granularity,
srd_addr_widths and dst_addr_widths bitfields.
Without those we will see a kernel WARN()
when loading musb on am335x devices.
I have applied this and will send to Linus as well
--
On Wed, Feb 25, 2015 at 04:54:02PM -0600, Felipe Balbi wrote:
Without those we will see a kernel WARN()
when loading musb on am335x devices.
Signed-off-by: Felipe Balbi ba...@ti.com
---
drivers/dma/cppi41.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/dma/cppi41.c
On Sat, Oct 11, 2014 at 09:09:33PM +0530, Vinod Koul wrote:
The recent discussion [1] on the API have resulted in moving away from
device_control ioctl method to proper channel APIs.
There are still few users on the device_control which should use the wrappers
existing rather than access
-dma.git/shortlog/refs/heads/topic/dma_control_cleanup
Vinod Koul (12):
pata_arasan_cf: use dmaengine_terminate_all() API
dmaengine: coh901318: use dmaengine_terminate_all() API
[media] V4L2: mx3_camer: use dmaengine_pause() API
mtd: fsmc_nand: use dmaengine_terminate_all() API
mtd
On Wed, Sep 24, 2014 at 10:28:07PM +0200, Rafael J. Wysocki wrote:
OK, I guess this is as good as it gets.
What tree would you like it go through?
Since rest of the patches are dependent upon 1st patch which should go thru
your tree, we should merge this thru your tree
Thanks
--
~Vinod
replacements.
If all are okay, this should be merged thru PM tree as it depends on macro
addition.
Subhransu S. Prusty (1):
PM: Add helper pm_runtime_last_busy_and_autosuspend()
Vinod Koul (26):
dmaengine: ste_dma: use pm_runtime_last_busy_and_autosuspend helper
extcon: arizona: use
Use the new pm_runtime_last_busy_and_autosuspend helper instead of open
coding the same code
Signed-off-by: Vinod Koul vinod.k...@intel.com
---
drivers/usb/musb/omap2430.c |6 ++
1 files changed, 2 insertions(+), 4 deletions(-)
diff --git a/drivers/usb/musb/omap2430.c b/drivers/usb/musb
On Mon, May 26, 2014 at 02:52:34PM +0200, Daniel Mack wrote:
When a 0-length packet is received on the bus, desc-pd0 yields 1,
which confuses the driver's users. This information is clearly wrong
and not in accordance to the datasheet, but it's been observed on an
AM335x board, very
On Mon, Jun 30, 2014 at 09:40:06PM +0200, Daniel Mack wrote:
On 06/30/2014 09:31 PM, Felipe Balbi wrote:
On Mon, Jun 30, 2014 at 09:29:10PM +0200, Daniel Mack wrote:
-BEGIN PGP SIGNED MESSAGE-
Hash: SHA1
On 06/30/2014 09:26 PM, Felipe Balbi wrote:
On Mon, Jun 30, 2014 at
On Thu, Feb 27, 2014 at 10:44:39AM +0530, George Cherian wrote:
Warinings are seen after ISOCH transfers, during channel tear down.
This is mainly beacause we handle ISOCH differently as compared to
other transfers.
Patch 1: make sure we do channel tear down only if channel is busy.
On Mon, Sep 23, 2013 at 07:53:11AM +0200, Daniel Mack wrote:
On 23.09.2013 06:09, Vinod Koul wrote:
On Sun, Sep 22, 2013 at 04:50:04PM +0200, Daniel Mack wrote:
+#ifdef CONFIG_PM_SLEEP
a
+static int cppi41_suspend(struct device *dev)
+{
+ struct cppi41_dd *cdd
On Sun, Sep 22, 2013 at 04:50:04PM +0200, Daniel Mack wrote:
This patch adds support for suspend/resume functionality to the cppi41
DMA driver. The steps necessary to make the system resume properly were
figured out by trial-and-error. The code as it stands now is the
minimum that has to be
On Thu, Sep 19, 2013 at 10:48:01PM +0100, Russell King wrote:
The DMA API requires drivers to call the appropriate dma_set_mask()
functions before doing any DMA mapping. Add this required call to
the AMBA PL08x driver.
Signed-off-by: Russell King rmk+ker...@arm.linux.org.uk
Acked-by: Vinod
-off-by: Russell King rmk+ker...@arm.linux.org.uk
Acked-by: Vinod Koul vinod.k...@intel.com
This also brings me question that should we force the driver to use the
dma_set_mask_and_coherent() API or they have below flexiblity too?
~Vinod
---
drivers/dma/edma.c |6 ++
1 files changed
doing any DMA mapping. Add this required call to
the AMBA PL08x driver.
^--- copy and paste error - should of course be PL330
Fixed, thanks.
with fixed changelog...
Acked-by: Vinod Koul vinod.k...@intel.com
~Vinod
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On Sun, Sep 22, 2013 at 04:50:04PM +0200, Daniel Mack wrote:
This patch adds support for suspend/resume functionality to the cppi41
DMA driver. The steps necessary to make the system resume properly were
figured out by trial-and-error. The code as it stands now is the
minimum that has to be
On Sun, Sep 22, 2013 at 04:50:01PM +0200, Daniel Mack wrote:
Fix a misspelled function name.
Signed-off-by: Daniel Mack zon...@gmail.com
Applied, thanks
~Vinod
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More
On Sun, Sep 22, 2013 at 04:50:00PM +0200, Daniel Mack wrote:
Instead of passing around struct plafform_device, use struct device and
save one level of dereferencing. This affects the following functions:
* cppi41_add_chans
* purge_descs
* deinit_cpii41
* init_descs
* init_cppi41
*
On Sun, Sep 22, 2013 at 04:50:02PM +0200, Daniel Mack wrote:
Makes the code more readable and compact. No functional change.
Signed-off-by: Daniel Mack zon...@gmail.com
Applied, thanks
~Vinod
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On Sun, Sep 22, 2013 at 04:50:03PM +0200, Daniel Mack wrote:
cdd-cd and cdd-descs_phys are allocated DESCS_AREAS times from
init_descs() and freed as often from purge_descs(). This leads to both
memory leaks and double-frees.
Fix this by pulling the calls to dma_{alloc,free}_coherent() out
On Tue, Aug 20, 2013 at 06:35:53PM +0200, Sebastian Andrzej Siewior wrote:
With enabled pm_runtime in the kernel the device won't work because it
is not on during the probe function. This patch enables the device via
pm_runtime on probe so it remains activated.
Cc: Vinod Koul vinod.k
-by: Vinod Koul vinod.k...@intel.com
~Vinod
---
drivers/dma/cppi41.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/dma/cppi41.c b/drivers/dma/cppi41.c
index 5dcebca..e696178 100644
--- a/drivers/dma/cppi41.c
+++ b/drivers/dma/cppi41.c
@@ -579,7 +579,7
. The real size of the
transfer has to be notified to the user / caller so he set this to the
caller.
This patch adds the transfered member to the dma_async_tx_descriptor
where the caller can obtain the final size.
Cc: Vinod Koul vinod.k...@intel.com
Cc: Dan Williams d...@fb.com
Signed-off
On Thu, Jul 18, 2013 at 01:21:55PM +0200, Sebastian Andrzej Siewior wrote:
On 07/11/2013 07:14 PM, Sebastian Andrzej Siewior wrote:
Dan, Vinod,
do you guys have an idea how the dma driver could inform its user how
much of the requested data got really transferred? This requirement
seems
On Wed, Jun 12, 2013 at 05:27:53PM +0530, Jassi Brar wrote:
IIRC, TI's Sundaram Raju proposed a TI specific api to DMAEngine for
this very purpose, which was generalized into
device_prep_interleaved_dma(). Which I think should already be enough
to serve the purpose. Is it not?
The
On Thu, May 30, 2013 at 11:19:33PM +0200, Linus Walleij wrote:
On Thu, May 30, 2013 at 10:31 PM, Tony Lindgren t...@atomide.com wrote:
There are many devices where the device FIFO is memory mapped to the
GPMC bus on omaps, like TUSB, OneNAND, smc911x etc. I believe the
only reason why
OR:ing with 0.
Cc: Vinod Koul vinod.k...@intel.com
Cc: Dan Williams d...@fb.com
Cc: Per Forlin per.for...@stericsson.com
Cc: Rabin Vincent ra...@rab.in
Signed-off-by: Lee Jones lee.jo...@linaro.org
Tentatively applied. Missing Vinod's ACK.
Acked-by: Vinod Koul vinod.k...@intel.com
as well add the infrastructure.
Cc: Vinod Koul vinod.k...@intel.com
Cc: Dan Williams d...@fb.com
Cc: Per Forlin per.for...@stericsson.com
Cc: Rabin Vincent ra...@rab.in
Acked-by: Arnd Bergmann a...@arndb.de
Signed-off-by: Lee Jones lee.jo...@linaro.org
Acked-by: Vinod Koul vinod.k
to shift '1' by the bit pattern (1 data_width)
times to make any sense of it.
This patch flips the semantics on its head and only converts the value
to its respective register bit pattern when writing to registers. This
way we can use the true data_width (in Bytes) value.
Cc: Vinod Koul vinod.k
as well add the infrastructure.
Cc: Vinod Koul vinod.k...@intel.com
Cc: Dan Williams d...@fb.com
Cc: Per Forlin per.for...@stericsson.com
Cc: Rabin Vincent ra...@rab.in
Signed-off-by: Lee Jones lee.jo...@linaro.org
---
Acked-by: Vinod Koul vinod.k...@intel.com
drivers/dma/ste_dma40.c |7
separating out this required code so it will be possible to move
the remaining code in d40_phy_cfg(), which is mostly runtime configuration
into the runtime_config() routine.
Cc: Vinod Koul vinod.k...@intel.com
Cc: Dan Williams d...@fb.com
Cc: Per Forlin per.for...@stericsson.com
Cc
On Wed, May 15, 2013 at 10:51:25AM +0100, Lee Jones wrote:
All configuration left in d40_phy_cfg() is runtime configurable and
there is already a call into it from d40_runtime_config(), so let's
rely on that.
Acked-by: Vinod Koul vnod.k...@intel.com
That needs up update!
Acked-by: Arnd
On Wed, May 15, 2013 at 10:51:31AM +0100, Lee Jones wrote:
Addresses are now stored in local data structures and are easy to
obtain, thus a specialist function used to fetch them is now surplus
to requirement.
Signed-off-by: Lee Jones lee.jo...@linaro.org
---
Acked-by: Vinod Koul vinod.k
On Wed, May 15, 2013 at 10:51:33AM +0100, Lee Jones wrote:
'struct stedma40_half_channel_info's header comment says that it's
called 'struct stedma40_chan_cfg'. Let's straighten that out.
Signed-off-by: Lee Jones lee.jo...@linaro.org
---
Acked-by: Vinod Koul vinod.k...@intel.com
--
~Vinod
On Thu, May 16, 2013 at 08:06:38AM +0100, Lee Jones wrote:
On Thu, 16 May 2013, Vinod Koul wrote:
On Wed, May 15, 2013 at 10:51:54AM +0100, Lee Jones wrote:
STEDMA40_*_TO_* direction definitions are identical in all but name to
the pre-defined generic DMA_*_TO_* ones. Let's make things
On Thu, May 16, 2013 at 08:25:57AM +0100, Lee Jones wrote:
On Thu, 16 May 2013, Vinod Koul wrote:
On Wed, May 15, 2013 at 10:51:25AM +0100, Lee Jones wrote:
All configuration left in d40_phy_cfg() is runtime configurable and
there is already a call into it from d40_runtime_config(), so
On Thu, May 16, 2013 at 08:35:53AM +0100, Lee Jones wrote:
On Thu, 16 May 2013, Vinod Koul wrote:
On Wed, May 15, 2013 at 10:51:57AM +0100, Lee Jones wrote:
+u8 d40_width_to_bits(enum dma_slave_buswidth width)
+{
+ if (width == DMA_SLAVE_BUSWIDTH_1_BYTE)
+ return
to be tailored. Fortunately, these platforms will be DT
only, so this change has very little impact on platform data.
Cc: Vinod Koul vinod.k...@intel.com
Cc: Dan Williams d...@fb.com
Cc: Per Forlin per.for...@stericsson.com
Cc: Rabin Vincent ra...@rab.in
Acked-by: Arnd Bergmann a...@arndb.de
Signed
On Wed, May 15, 2013 at 10:51:56AM +0100, Lee Jones wrote:
The aim is to make the code that little more readable.
Cc: Vinod Koul vinod.k...@intel.com
Cc: Dan Williams d...@fb.com
Cc: Per Forlin per.for...@stericsson.com
Cc: Rabin Vincent ra...@rab.in
Signed-off-by: Lee Jones lee.jo
On Wed, May 15, 2013 at 10:51:54AM +0100, Lee Jones wrote:
STEDMA40_*_TO_* direction definitions are identical in all but name to
the pre-defined generic DMA_*_TO_* ones. Let's make things easy by not
duplicating such things.
Cc: Vinod Koul vinod.k...@intel.com
Cc: Dan Williams d...@fb.com
to blame)
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~Vinod
Cc: Vinod Koul vinod.k...@intel.com
Cc: Dan Williams d...@fb.com
Cc: Per Forlin per.for...@stericsson.com
Cc: Rabin Vincent ra...@rab.in
Signed-off-by: Lee Jones lee.jo...@linaro.org
---
drivers/dma/ste_dma40_ll.c |6 --
1 file changed, 4 insertions(+), 2
this patch on
your email? They would be the natural ones to help fix it :)
Yes, ofcourse. missed :-(
Thanks
These set of patches are dependent on vinod koul generic dma dt binding
patches. I mentioned the dependency info in my cover-letter.
Hi Vinod,
Can you please tell when
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