On 28.04.2017 04:04, Peter Chen wrote:
On Thu, Apr 27, 2017 at 03:43:28PM +0300, Mathias Nyman wrote:
Hi
On 27.04.2017 12:49, Peter Chen wrote:
On Mon, Apr 17, 2017 at 04:20:43PM +0800, Peter Chen wrote:
According to xHCI spec Figure 30: Interrupt Throttle Flow Diagram
If PCI
On Thu, Apr 27, 2017 at 03:43:28PM +0300, Mathias Nyman wrote:
> Hi
>
> On 27.04.2017 12:49, Peter Chen wrote:
> >On Mon, Apr 17, 2017 at 04:20:43PM +0800, Peter Chen wrote:
> >>According to xHCI spec Figure 30: Interrupt Throttle Flow Diagram
> >>
> >>If PCI Message Signaled Interrupts (MSI
Hi
On 27.04.2017 12:49, Peter Chen wrote:
On Mon, Apr 17, 2017 at 04:20:43PM +0800, Peter Chen wrote:
According to xHCI spec Figure 30: Interrupt Throttle Flow Diagram
If PCI Message Signaled Interrupts (MSI or MSI-X) are enabled,
then the assertion of the Interrupt
On Mon, Apr 17, 2017 at 04:20:43PM +0800, Peter Chen wrote:
> According to xHCI spec Figure 30: Interrupt Throttle Flow Diagram
>
> If PCI Message Signaled Interrupts (MSI or MSI-X) are enabled,
> then the assertion of the Interrupt Pending (IP) flag in Figure
> 30
>
According to xHCI spec Figure 30: Interrupt Throttle Flow Diagram
If PCI Message Signaled Interrupts (MSI or MSI-X) are enabled,
then the assertion of the Interrupt Pending (IP) flag in Figure 30
generates a PCI Dword write. The IP flag is automatically cleared
by