On Wed, Jul 31, 2013 at 05:29:40PM -0600, Stephen Warren wrote:
On 07/31/2013 04:20 PM, Sergei Shtylyov wrote:
On 08/01/2013 02:06 AM, Stephen Warren wrote:
...
That's really horrible design.
Yup. Both USB PHY and EHCI controller registers really are interleaved
in one range.
Hello.
On 01-08-2013 3:29, Stephen Warren wrote:
Don't they cause numerous resource conflicts while device nodes
being
instantiated as the platform devices?
No; the driver knows that the HW is screwy and there's lots of
register-range sharing going on, so it simply maps the registers,
From: Mikko Perttunen mperttu...@nvidia.com
Device tree entries for the three EHCI controllers on Tegra114.
Enables the the third controller (USB host) on Dalmore.
Signed-off-by: Mikko Perttunen mperttu...@nvidia.com
---
arch/arm/boot/dts/tegra114-dalmore.dts | 9 +
Hello.
On 07/31/2013 09:42 PM, Tuomas Tynkkynen wrote:
From: Mikko Perttunen mperttu...@nvidia.com
Device tree entries for the three EHCI controllers on Tegra114.
Enables the the third controller (USB host) on Dalmore.
I would have done the board patch separately from the SoC one.
Hello,
On 31/07/13 21:18, Sergei Shtylyov wrote:
Hello.
On 07/31/2013 09:42 PM, Tuomas Tynkkynen wrote:
From: Mikko Perttunen mperttu...@nvidia.com
Device tree entries for the three EHCI controllers on Tegra114.
Enables the the third controller (USB host) on Dalmore.
I would have
Hello.
On 07/31/2013 11:31 PM, Tuomas Tynkkynen wrote:
From: Mikko Perttunen mperttu...@nvidia.com
Device tree entries for the three EHCI controllers on Tegra114.
Enables the the third controller (USB host) on Dalmore.
I would have done the board patch separately from the SoC one.
On 07/31/2013 01:53 PM, Sergei Shtylyov wrote:
Hello.
On 07/31/2013 11:31 PM, Tuomas Tynkkynen wrote:
Device tree entries for the three EHCI controllers on Tegra114.
Enables the the third controller (USB host) on Dalmore.
diff --git a/arch/arm/boot/dts/tegra114.dtsi
On 08/01/2013 02:06 AM, Stephen Warren wrote:
Device tree entries for the three EHCI controllers on Tegra114.
Enables the the third controller (USB host) on Dalmore.
diff --git a/arch/arm/boot/dts/tegra114.dtsi
b/arch/arm/boot/dts/tegra114.dtsi
index abf6c40..2905145 100644
---
On 07/31/2013 04:20 PM, Sergei Shtylyov wrote:
On 08/01/2013 02:06 AM, Stephen Warren wrote:
...
That's really horrible design.
Yup. Both USB PHY and EHCI controller registers really are interleaved
in one range.
But the standard EHCI register space has no holes IIRC, so they can't
