Hi,
Doug Anderson writes:
isn't this a regression ? You're first clearing the interrupts and only
then reading to check what's pending, however, what's pending has just
been cleared. Seems like this should be:
hprt0 = dwc2_readl(HPRT0);
Hi,
On Wed, Nov 18, 2015 at 5:43 PM, John Youn wrote:
> On 11/16/2015 9:22 AM, Doug Anderson wrote:
>> Felipe,
>>
>> On Mon, Nov 16, 2015 at 8:28 AM, Felipe Balbi wrote:
>>>
>>> Hi,
>>>
>>> Douglas Anderson writes:
In general it
On 11/16/2015 9:22 AM, Doug Anderson wrote:
> Felipe,
>
> On Mon, Nov 16, 2015 at 8:28 AM, Felipe Balbi wrote:
>>
>> Hi,
>>
>> Douglas Anderson writes:
>>> In general it is wise to clear interrupts before processing them. If
>>> you don't do that, you can
Hi,
Douglas Anderson writes:
> In general it is wise to clear interrupts before processing them. If
> you don't do that, you can get:
> 1. Interrupt happens
> 2. You look at system state and process interrupt
> 3. A new interrupt happens
> 4. You clear interrupt
Felipe,
On Mon, Nov 16, 2015 at 8:28 AM, Felipe Balbi wrote:
>
> Hi,
>
> Douglas Anderson writes:
>> In general it is wise to clear interrupts before processing them. If
>> you don't do that, you can get:
>> 1. Interrupt happens
>> 2. You look at system
On 11/3/2015 12:31 PM, Douglas Anderson wrote:
> In general it is wise to clear interrupts before processing them. If
> you don't do that, you can get:
> 1. Interrupt happens
> 2. You look at system state and process interrupt
> 3. A new interrupt happens
> 4. You clear interrupt without
In general it is wise to clear interrupts before processing them. If
you don't do that, you can get:
1. Interrupt happens
2. You look at system state and process interrupt
3. A new interrupt happens
4. You clear interrupt without processing it.
This patch was actually a first attempt to fix