On Mon, Mar 03, 2014 at 09:25:13PM -0600, dingu...@altera.com wrote:
From: Dinh Nguyen dingu...@altera.com
The dwc2 IP on the SOCFPGA cannot use the default HW configured
FIFO sizes. The total FIFO depth as read from GHWCFG3 reports 0x1f80 or 8064
32-bit words. But the GRXFSIZ, GNPTXFSIZ,
On Tue, 2014-03-04 at 09:18 -0600, Felipe Balbi wrote:
On Mon, Mar 03, 2014 at 09:25:13PM -0600, dingu...@altera.com wrote:
From: Dinh Nguyen dingu...@altera.com
The dwc2 IP on the SOCFPGA cannot use the default HW configured
FIFO sizes. The total FIFO depth as read from GHWCFG3 reports
Hi,
On Tue, Mar 04, 2014 at 11:34:26AM -0600, Dinh Nguyen wrote:
On Tue, 2014-03-04 at 09:18 -0600, Felipe Balbi wrote:
On Mon, Mar 03, 2014 at 09:25:13PM -0600, dingu...@altera.com wrote:
From: Dinh Nguyen dingu...@altera.com
The dwc2 IP on the SOCFPGA cannot use the default HW
From: Dinh Nguyen dingu...@altera.com
The dwc2 IP on the SOCFPGA cannot use the default HW configured
FIFO sizes. The total FIFO depth as read from GHWCFG3 reports 0x1f80 or 8064
32-bit words. But the GRXFSIZ, GNPTXFSIZ, and HPTXFSIZ register defaults
to 0x2000 or 8192 32-bit words. So the driver
