From: Mason
> Sent: 14 March 2017 12:06
> On 14/03/2017 11:23, David Laight wrote:
>
> > Mason wrote:
> >
> >> I'd like to push support for this PCIe controller upstream.
> >>
> >> Is the code I posted on the right track?
> >> Maybe I can post a RFC patch tomorrow?
> >
> > I think you need to
On 14/03/2017 11:23, David Laight wrote:
> Mason wrote:
>
>> I'd like to push support for this PCIe controller upstream.
>>
>> Is the code I posted on the right track?
>> Maybe I can post a RFC patch tomorrow?
>
> I think you need to resolve the problem of config space (and IO) cycles
> before
From: Mason
> Sent: 13 March 2017 21:58
...
> I'd like to push support for this PCIe controller upstream.
>
> Is the code I posted on the right track?
> Maybe I can post a RFC patch tomorrow?
I think you need to resolve the problem of config space (and IO) cycles
before the driver can be deemed
On Mon, Mar 13, 2017 at 10:57:48PM +0100, Mason wrote:
> On 13/03/2017 22:40, Bjorn Helgaas wrote:
>
> > On Sat, Mar 11, 2017 at 11:57:56AM +0100, Mason wrote:
> >
> >> On 10/03/2017 18:49, Mason wrote:
> >>
> >>> static void tango_pcie_bar_quirk(struct pci_dev *dev)
> >>> {
> >>> struct
On 13/03/2017 22:40, Bjorn Helgaas wrote:
> On Sat, Mar 11, 2017 at 11:57:56AM +0100, Mason wrote:
>
>> On 10/03/2017 18:49, Mason wrote:
>>
>>> static void tango_pcie_bar_quirk(struct pci_dev *dev)
>>> {
>>> struct pci_bus *bus = dev->bus;
>>>
>>> printk("%s: bus=%d devfn=%d\n",
On Sat, Mar 11, 2017 at 11:57:56AM +0100, Mason wrote:
> On 10/03/2017 18:49, Mason wrote:
> > static void tango_pcie_bar_quirk(struct pci_dev *dev)
> > {
> > struct pci_bus *bus = dev->bus;
> >
> > printk("%s: bus=%d devfn=%d\n", __func__, bus->number, dev->devfn);
> >
> >
On 10/03/2017 18:49, Mason wrote:
> And my current code, to work-around the silicon bugs:
>
> #include
> #include
> #include
> #include
> #include
> #include
> #include
>
> //#define DEBUG_CONFIG
>
> static int tango_config_read(struct pci_bus *bus, unsigned int devfn,
>
On Fri, Mar 10, 2017 at 04:05:50PM +0100, Mason wrote:
> On 10/03/2017 15:06, David Laight wrote:
>
> > Robin Murphy wrote:
> >
> >> On 09/03/17 23:43, Mason wrote:
> >>
> >>> I think I'm making progress, in that I now have a better
> >>> idea of what I don't understand. So I'm able to ask
> >>>
On 10/03/2017 17:45, Mason wrote:
> Time to clean up a million hacks to be able to discuss the finer points.
Here is my current boot log:
[1.133895] OF: PCI: host bridge /soc/pcie@5000 ranges:
[1.139607] pci_add_resource_offset: res=[bus 00-0f] offset=0x0
[1.145659] OF: PCI:
On 10/03/2017 00:43, Mason wrote:
> I think I'm making progress [...]
Yes! I was able to plug a USB3 Flash drive, mount it,
and read its contents. A million thanks, my head was
starting to hurt from too much banging.
Time to clean up a million hacks to be able to discuss
the finer points.
On 10/03/17 15:35, David Laight wrote:
> From: Robin Murphy
>> Sent: 10 March 2017 15:23
> ...
So you have 128MB (max) of system memory that has cpu physical
addresses 0x8000 upwards.
I'd expect it all to be accessible from any PCIe card at some PCIe
address, it might be
From: Robin Murphy
> Sent: 10 March 2017 15:23
...
> >> So you have 128MB (max) of system memory that has cpu physical
> >> addresses 0x8000 upwards.
> >> I'd expect it all to be accessible from any PCIe card at some PCIe
> >> address, it might be at address 0, 0x8000 or any other offset.
On 10/03/2017 16:14, David Laight wrote:
> Mason wrote:
>
>> My RC drops packets not targeting its BAR0.
>
> I suspect the fpga/cpld logic supports RC and endpoint modes
> and is using much the same names for the registers (and logic
> implementation).
Your guess is spot on.
In the
On 10/03/17 15:05, Mason wrote:
> On 10/03/2017 15:06, David Laight wrote:
>
>> Robin Murphy wrote:
>>
>>> On 09/03/17 23:43, Mason wrote:
>>>
I think I'm making progress, in that I now have a better
idea of what I don't understand. So I'm able to ask
(hopefully) less vague
From: Mason
> Sent: 10 March 2017 15:06
...
> My RC drops packets not targeting its BAR0.
I suspect the fpga/cpld logic supports RC and endpoint modes
and is using much the same names for the registers (and logic
implementation).
If your cpu support more than 1GB of memory but only part is
PCIe
On 10/03/2017 15:06, David Laight wrote:
> Robin Murphy wrote:
>
>> On 09/03/17 23:43, Mason wrote:
>>
>>> I think I'm making progress, in that I now have a better
>>> idea of what I don't understand. So I'm able to ask
>>> (hopefully) less vague questions.
>>>
>>> Take the USB3 PCIe adapter I've
On 10/03/2017 14:15, Robin Murphy wrote:
> On 09/03/17 23:43, Mason wrote:
>> On 08/03/2017 16:17, Bjorn Helgaas wrote:
>> [snip excellent in-depth overview]
>>
>> I think I'm making progress, in that I now have a better
>> idea of what I don't understand. So I'm able to ask
>> (hopefully) less
From: Robin Murphy
> Sent: 10 March 2017 13:16
> On 09/03/17 23:43, Mason wrote:
> > On 08/03/2017 16:17, Bjorn Helgaas wrote:
> > [snip excellent in-depth overview]
> >
> > I think I'm making progress, in that I now have a better
> > idea of what I don't understand. So I'm able to ask
> >
On 09/03/17 23:43, Mason wrote:
> On 08/03/2017 16:17, Bjorn Helgaas wrote:
> [snip excellent in-depth overview]
>
> I think I'm making progress, in that I now have a better
> idea of what I don't understand. So I'm able to ask
> (hopefully) less vague questions.
>
> Take the USB3 PCIe adapter
On 08/03/2017 16:17, Bjorn Helgaas wrote:
[snip excellent in-depth overview]
I think I'm making progress, in that I now have a better
idea of what I don't understand. So I'm able to ask
(hopefully) less vague questions.
Take the USB3 PCIe adapter I've been testing with. At some
point during
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