hi sarah
On Sat, Oct 06, 2012 at 12:53:43PM +0800, loody wrote:
hi sarah:
2012/10/6 Sarah Sharp sarah.a.sh...@linux.intel.com:
I see. Is there a particular reason why the current Linux xHCI driver
doesn't meet your needs? Like maybe your host isn't PCI based? I'm
confused as to why
On Sat, Oct 06, 2012 at 12:53:43PM +0800, loody wrote:
hi sarah:
2012/10/6 Sarah Sharp sarah.a.sh...@linux.intel.com:
I see. Is there a particular reason why the current Linux xHCI driver
doesn't meet your needs? Like maybe your host isn't PCI based? I'm
confused as to why you would
On Fri, Oct 05, 2012 at 01:27:10PM +0800, loody wrote:
hi Sarah:
2012/10/5 Sarah Sharp sarah.a.sh...@linux.intel.com:
On Thu, Oct 04, 2012 at 01:47:44PM +0800, loody wrote:
Hi all:
from below out put slot context it shows ep0 consumer cycle bit is 1
but why when we enqueue control
On Fri, Oct 05, 2012 at 10:34:19AM +0800, loody wrote:
hi Sarah:
2012/10/5 Sarah Sharp sarah.a.sh...@linux.intel.com:
On Thu, Oct 04, 2012 at 01:47:44PM +0800, loody wrote:
Hi all:
from below out put slot context it shows ep0 consumer cycle bit is 1
but why when we enqueue control
On Thu, Oct 04, 2012 at 01:47:44PM +0800, loody wrote:
Hi all:
from below out put slot context it shows ep0 consumer cycle bit is 1
but why when we enqueue control transfer we purposely leave setup
status cycle bit as 0.
(below I purpose dump control trb content and 0xcf01c80c should be
hi Sarah:
2012/10/5 Sarah Sharp sarah.a.sh...@linux.intel.com:
On Thu, Oct 04, 2012 at 01:47:44PM +0800, loody wrote:
Hi all:
from below out put slot context it shows ep0 consumer cycle bit is 1
but why when we enqueue control transfer we purposely leave setup
status cycle bit as 0.
(below
