On Wed, Jun 26, 2013 at 05:17:29PM +0530, Kishon Vijay Abraham I wrote:
+menuconfig GENERIC_PHY
+ tristate PHY Subsystem
+ help
+ Generic PHY support.
+
+ This framework is designed to provide a generic interface for PHY
+ devices present in the kernel. This layer
This patchset moves the USB UTMI interface parameters from hardcoded tables
in the PHY driver to device tree and adds code to read them from there.
This is a repost of the v2 version of the patchset.
Mikko Perttunen (2):
ARM: dts: tegra20: Rename USB UTMI parameters according to new
This patch changes the Tegra20 USB PHY nodes to use the UTMI configuration
parameter names as specified in the device tree binding documentation
after patch ARM: tegra: finalize USB EHCI and PHY bindings.
Signed-off-by: Mikko Perttunen mperttu...@nvidia.com
Acked-by: Stephen Warren
UTMIP parameters used to be hardcoded into tables in the
PHY driver. This patch reads them from the device tree instead
in accordance with the phy-tegra-usb DT documentation.
Signed-off-by: Mikko Perttunen mperttu...@nvidia.com
Reviewed-by: Stephen Warren swar...@nvidia.com
Tested-by: Stephen
On Wed, 2013-07-17 at 03:10 +, WangChen wrote:
Sorry, I think existing code should already handle retry for blcoking case.
My idea to retry anyway @line328 is just intention to make the code looks
better
and handle the return of -EAGAIN in one place which is handled by retry
logic.
USB VBUS regulators are now specified with the vbus-supply property
instead of nvidia,vbus-gpio, so remove the obsolete properties.
The equivalent vbus-supply properties were already added in patch
ARM: tegra: update device trees for USB binding rework.
Signed-off-by: Mikko Perttunen
Document vbus-supply as an optional property for host mode phy-tegra-usb PHYs.
Signed-off-by: Mikko Perttunen mperttu...@nvidia.com
Reviewed-by: Stephen Warren swar...@nvidia.com
Tested-by: Stephen Warren swar...@nvidia.com
---
Documentation/devicetree/bindings/usb/nvidia,tegra20-usb-phy.txt | 2
The tegra ehci driver has enabled USB vbus regulators directly using
GPIOs and the device tree attribute nvidia,vbus-gpio. This is ugly
and causes error messages on boot when both the regulator driver
and the ehci driver want access to the same GPIO.
After this patch, usb vbus regulators for
This patchset removes the ehci-tegra device tree property nvidia,vbus-gpio
and adds support for the vbus-supply property to phy-tegra-usb.
v3:
Change commit messages, fix one 80 character line
Mikko Perttunen (3):
usb: tegra: Use regulators instead of GPIOs for USB PHY VBUS
usb: tegra: Add
Hi,
On Mon, Jul 15, 2013 at 11:31:17PM -0700, Greg KH wrote:
The question is since we default GADGET, so the g_mass_storage.ko is
installed early but connecting to a host PC
is randomly, But the udev has no idea when a host PC connects our device.
So we consider it's reasonable to let
From: Kishon Vijay Abraham I kis...@ti.com
some MUSB incarnations, such as those governed by
omap2430.c and tusb6010.c, have three resources, not
two.
Fix the bug created by commit 09fc7d2 (usb: musb:
fix incorrect usage of resource pointer) where only
two of the three resources would be passed
Cc: ARM list
On Wed, Jul 17, 2013 at 1:03 PM, 김기오 gioh@lge.com wrote:
Hi,
I have a missing urb completion problem on ARMv7 based platform.
I thought the above problem was caused by coherent memory between the
EHCI device and CPU so I tryied to allocates device type memory
for EHCI via
Hi,
On Wednesday 17 July 2013 11:59 AM, Greg KH wrote:
On Wed, Jun 26, 2013 at 05:17:29PM +0530, Kishon Vijay Abraham I wrote:
+menuconfig GENERIC_PHY
+tristate PHY Subsystem
+help
+ Generic PHY support.
+
+ This framework is designed to provide a generic interface for
Hi Paul,
On Tue, Jul 16, 2013 at 12:22:12PM -0700, Paul Zimmerman wrote:
The dwc2 driver sets the value of the DWC2 GAHBCFG register to 0x6,
which is GAHBCFG_HBSTLEN_INCR4. But different platforms may require
different values. In particular, the Broadcom 2835 SOC used in the
Raspberry Pi
Hi Felipe,
On Wed, Jul 17, 2013 at 3:57 PM, Felipe Balbi ba...@ti.com wrote:
Hi,
On Mon, Jul 15, 2013 at 11:31:17PM -0700, Greg KH wrote:
The question is since we default GADGET, so the g_mass_storage.ko is
installed early but connecting to a host PC
is randomly, But the udev has no idea
On Wed, Jul 17, 2013 at 09:04:54PM +0800, Rong Wang wrote:
Hi Felipe,
On Wed, Jul 17, 2013 at 3:57 PM, Felipe Balbi ba...@ti.com wrote:
Hi,
On Mon, Jul 15, 2013 at 11:31:17PM -0700, Greg KH wrote:
The question is since we default GADGET, so the g_mass_storage.ko is
installed early
Hey Stephen,
Ah, that makes sense. It wasn't clear to me from the config structure
that some of the variables didn't correspond directly to config
fields/registers in the HW.
I have a patch pending that separates configured values from hardware
values, which would help here. I'll try to send
This patch moves at91_pmc.h header from machine specific directory
(arch/arm/mach-at91/include/mach/at91_pmc.h) to clk include directory
(include/linux/clk/at91.h).
We need this to avoid reference to machine specific headers in clk
drivers.
Signed-off-by: Boris BREZILLON b.brezil...@overkiz.com
Hello Alan,
On Tuesday, July 16, 2013 5:17 PM Alan Stern wrote:
On Tue, 16 Jul 2013, Andrzej Pietrasiewicz wrote:
When configfs is in place, the things related to intialization of
struct fsg_common will be split over a number of places.
This patch adds several functions which together
Hello Alan,
Thank you for your review. Please see below for a comment.
On Tuesday, July 16, 2013 5:13 PM Alan Stern wrote:
On Tue, 16 Jul 2013, Andrzej Pietrasiewicz wrote:
This is needed to prepare for configfs integration.
So far the luns have been allocated during gadget's
On Tue, 16 Jul 2013, James Stone wrote:
Thanks. The patch allows jack to now start at (playback only) 64
frames/period. It doesn't work with 32 frames/period though (I think
you predicted this). This is still a regression from 3.5.0-28, which
will work with 8 frames/period for playback only.
On Tue, 16 Jul 2013, Boris BREZILLON wrote:
The AT91 PMC (Power Management Controller) provides an USB clock used by
USB Full Speed host (ohci) and USB Full Speed device (udc).
The usb drivers (ohci and udc) must configure this clock to 48Mhz.
This configuration was formely done in
On Wed, 17 Jul 2013, Felipe Balbi wrote:
On Wed, Jul 17, 2013 at 09:04:54PM +0800, Rong Wang wrote:
Hi Felipe,
On Wed, Jul 17, 2013 at 3:57 PM, Felipe Balbi ba...@ti.com wrote:
Hi,
On Mon, Jul 15, 2013 at 11:31:17PM -0700, Greg KH wrote:
The question is since we default
On Wed, 17 Jul 2013, Andrzej Pietrasiewicz wrote:
Hello Alan,
Hello.
@@ -179,7 +179,7 @@ EXPORT_SYMBOL(fsg_ss_function); void
fsg_lun_close(struct fsg_lun *curlun) {
if (curlun-filp) {
- LDBG(curlun, close backing file\n);
+ pr_debug(close backing file\n);
This (read-only) register was read twice, storing it for later use the
second time. Now it is only read once, storing it right away.
Signed-off-by: Matthijs Kooijman matth...@stdin.nl
---
drivers/staging/dwc2/hcd.c | 12 ++--
1 file changed, 6 insertions(+), 6 deletions(-)
diff --git
This commit changes expressions from (val shift) (mask shift) to
(val mask) shift.
Signed-off-by: Matthijs Kooijman matth...@stdin.nl
---
drivers/staging/dwc2/core.c | 20 ++---
drivers/staging/dwc2/hcd.c | 62 +++--
Previously, the max_packet_count could be set to 1 x, where x is the
number of bits available (width + 4 in the code). Since 1 x requires
x + 1 bits to represent, this will not work. The real maximum value is
(1 x) - 1. This value is already used the default when the set value
is invalid, but
Before, the hwcfg registers were read at device init time, but
interpreted at various parts in the code. This commit unpacks the hwcfg
register values into a struct with properly labeled variables at init
time, which makes all the other code using these values more consise and
easier to read. Some
Various register fields wider than one bit have constants defined for
their value. Previously, these registers would define the values as they
appear in the register, so shifted to the right to the position the
value appears in the register.
This commit changes those constants to their natural
Some of the defaults were missing or unclear. In particular, I suspect
the defaults were documented assuming there were still module parameters
and taking the default module parameters into account. Now, the defaults
are the values that will get chosen when the params passed to
dwc2_hcd_init are
Bits 16-31 are reserved, so the old code just reads the whole register to
get bits 0-15, assuming the reserved bits would be 0 (which seems true
on current hardware, but who knows...).
This commit properly masks out the reserved bits when reading and
doesn't touch the reserved bits while writing.
A generic set of FIFOSIZE_* constants was used for both the GNPTXFSIZ
and HPTXFSIZ registers, even where a specific set of constants was a
available for the GNPTXFSIZ register. This change adds specific
constants for the HPTXFSIZ register as well, changes the code to use
those specific constants
For some reason, the value of the HPTXFSIZ register was built in the
ptxfsiz variable, while there was also a hptxfsiz variable availble.
Better just use that and remove the (now unused) ptxfsiz variable.
Signed-off-by: Matthijs Kooijman matth...@stdin.nl
---
drivers/staging/dwc2/core.c | 12
The AT91 PMC (Power Management Controller) provides an USB clock used by
USB Full Speed host (ohci) and USB Full Speed device (udc).
The usb drivers (ohci and udc) must configure this clock to 48Mhz.
This configuration was formely done in mach-at91/clock.c, but this
implementation will be removed
The AT91 PMC (Power Management Controller) provides an USB clock used by
USB Full Speed host (ohci) and USB Full Speed device (udc).
The usb drivers (ohci and udc) must configure this clock to 48Mhz.
This configuration was formely done in mach-at91/clock.c, but this
implementation will be removed
On 17/07/2013 17:33, Alan Stern wrote:
On Tue, 16 Jul 2013, Boris BREZILLON wrote:
The AT91 PMC (Power Management Controller) provides an USB clock used by
USB Full Speed host (ohci) and USB Full Speed device (udc).
The usb drivers (ohci and udc) must configure this clock to 48Mhz.
This
The value of the hcchar register is built from individual values by
shifting and masking. Before, the debug output extracted the individual
values out of the complete hcchar register again by doing the reverse.
This commit makes the debug output use the original values instead.
One debug message
The HWCFG4 register stores the supported utmi width values (8, 16 or
both). This commit reads that value and validates the configured value
against that.
If no (valid) value is given, the parameter defaulted to 8 bits
previously. However, the documentation for dwc2_core_params_struct
suggests
For calculating FIFO offsets, the sizes of preceding fifos need to be
known. For filling the GDFIFOCFG register, these fifo sizes were read
from hardware registers. However, these values were written to these
registers just a few lines before, so we can just use the values written
instead.
There was some code that cleared the dma_mask when dma was disabled in
the driver. Given that clearing the mask doesn't actually tell the usb
core we're not using dma, and a previous commit explicitely sets the
hcd-self.uses_dma value, it seems these values are unneeded and can
only potentially
If the platform or bus driver failed to setup a dma_mask, but the
hardware advertises support for DMA, before DMA would be enabled in
dwc2, but disabled in the usb core, making all connectivity break.
With this commit, the dwc2 driver will emit a warning and fall back to
slave mode in this case.
Here's a resend of three patches I sent a while ago as part of a bigger
series. These were the unimportant patches to be included later, so here
they are again.
Gr.
Matthijs
Matthijs Kooijman (3):
staging: dwc2: disable dma when no dma_mask was setup
staging: dwc2: when dma is disabled,
When dma is disabled inside dwc2 (because the hardware does not support
it, or the code was changed to disable it for testing), let the usb core
know about this by clearing hcd-self.uses_dma.
By default, the usb core assumes that dma is used when a dma_mask is
set, but this might not always match
On Wed, 17 Jul 2013, boris brezillon wrote:
On 17/07/2013 17:33, Alan Stern wrote:
On Tue, 16 Jul 2013, Boris BREZILLON wrote:
The AT91 PMC (Power Management Controller) provides an USB clock used by
USB Full Speed host (ohci) and USB Full Speed device (udc).
The usb drivers (ohci and
On Wed, Jul 17, 2013 at 3:59 PM, Alan Stern st...@rowland.harvard.edu wrote:
On Tue, 16 Jul 2013, James Stone wrote:
Thanks. The patch allows jack to now start at (playback only) 64
frames/period. It doesn't work with 32 frames/period though (I think
you predicted this). This is still a
* Ezequiel Garcia | 2013-07-06 18:39:50 [-0300]:
Hi Sebastian,
Hi Ezequiel,
After some minor DT tweaking on the current patchset,
I've managed to detect an USB mass storage device in the
second instance (host / usb1) using a Beaglebone black board.
Beaglebone black, that one has a different
Hi,
What is the expected behavior if a host controller does not implement
bus_suspend and bus_resume? I am seeing that with the HWA HCD, kworker
and khubd peg the CPU at 100% because the kernel is constantly calling
hcd_bus_suspend and hcd_bus_resume. The calls to hcd_bus_suspend and
On Wed, Jul 17, 2013 at 10:57:06AM +0300, Felipe Balbi wrote:
Hi,
On Mon, Jul 15, 2013 at 11:31:17PM -0700, Greg KH wrote:
The question is since we default GADGET, so the g_mass_storage.ko is
installed early but connecting to a host PC
is randomly, But the udev has no idea when a host
On Wed, Jul 17, 2013 at 03:02:59PM +0530, Kishon Vijay Abraham I wrote:
Hi,
On Wednesday 17 July 2013 11:59 AM, Greg KH wrote:
On Wed, Jun 26, 2013 at 05:17:29PM +0530, Kishon Vijay Abraham I wrote:
+menuconfig GENERIC_PHY
+ tristate PHY Subsystem
+ help
+Generic PHY support.
Hi Sebastian,
On Wed, Jul 17, 2013 at 07:12:29PM +0200, Sebastian Andrzej Siewior wrote:
After some minor DT tweaking on the current patchset,
I've managed to detect an USB mass storage device in the
second instance (host / usb1) using a Beaglebone black board.
Beaglebone black, that one
From: Matthijs Kooijman [mailto:matth...@stdin.nl]
Sent: Wednesday, July 17, 2013 4:15 AM
On Tue, Jul 16, 2013 at 12:22:12PM -0700, Paul Zimmerman wrote:
The dwc2 driver sets the value of the DWC2 GAHBCFG register to 0x6,
which is GAHBCFG_HBSTLEN_INCR4. But different platforms may require
From: Matthijs Kooijman [mailto:matth...@stdin.nl]
Sent: Wednesday, July 17, 2013 8:10 AM
A generic set of FIFOSIZE_* constants was used for both the GNPTXFSIZ
and HPTXFSIZ registers, even where a specific set of constants was a
available for the GNPTXFSIZ register. This change adds
From: Matthijs Kooijman [mailto:matth...@stdin.nl]
Sent: Wednesday, July 17, 2013 8:10 AM
these are the last of that huge series of patches I sent a few months
ago. What's left is mostly cleanups related to register and
configuration values.
Note that this series does not apply cleanly
On Wed, 17 Jul 2013, James Stone wrote:
On Wed, Jul 17, 2013 at 3:59 PM, Alan Stern st...@rowland.harvard.edu wrote:
On Tue, 16 Jul 2013, James Stone wrote:
Thanks. The patch allows jack to now start at (playback only) 64
frames/period. It doesn't work with 32 frames/period though (I
From: Matthijs Kooijman [mailto:matth...@stdin.nl]
Sent: Wednesday, July 17, 2013 8:10 AM
Various register fields wider than one bit have constants defined for
their value. Previously, these registers would define the values as they
appear in the register, so shifted to the right to the
On Wed, 17 Jul 2013, Thomas Pugliese wrote:
Hi,
What is the expected behavior if a host controller does not implement
bus_suspend and bus_resume? I am seeing that with the HWA HCD, kworker
and khubd peg the CPU at 100% because the kernel is constantly calling
hcd_bus_suspend and
On Thu, 4 Jul 2013, Alan Stern wrote:
On Thu, 4 Jul 2013, Ming Lei wrote:
If so, your coming change may break ABI because as you described
that the flag should be set in the first URB of a new stream, but
some user-space drivers may not set it before. Even USB audio driver
doesn't
The transfer scheduler in the dwc2 driver is pretty basic, not to
mention buggy. It works fairly well with just a couple of devices
plugged in, but if you add, say, multiple devices with periodic
endpoints, the scheduler breaks down and can't even enumerate all
the devices.
To fix this, import
From: Stephen Warren [mailto:swar...@wwwdotorg.org]
Sent: Saturday, July 13, 2013 10:35 PM
On 07/13/2013 04:34 PM, Paul Zimmerman wrote:
I just sent out a patch series with a number of fixes for the dwc2
driver. With that, plus the hack patch below to add all the driver
parameters
Hi Paul,
I was about to send out another patch which enhances the scheduling
code in the driver. It finally makes the driver work well on the
Raspberry Pi, at least in my testing. So I would rather submit that
code first rather than risk breaking it with this big set of changes.
So can you
Hi Paul,
On Wed, Jul 17, 2013 at 06:44:04PM +, Paul Zimmerman wrote:
From: Matthijs Kooijman [mailto:matth...@stdin.nl]
Sent: Wednesday, July 17, 2013 8:10 AM
A generic set of FIFOSIZE_* constants was used for both the GNPTXFSIZ
and HPTXFSIZ registers, even where a specific set of
On Wed, 17 Jul 2013, Alan Stern wrote:
On Wed, 17 Jul 2013, Thomas Pugliese wrote:
Hi,
What is the expected behavior if a host controller does not implement
bus_suspend and bus_resume? I am seeing that with the HWA HCD, kworker
and khubd peg the CPU at 100% because the kernel is
On Wed, 17 Jul 2013, Thomas Pugliese wrote:
On Wed, 17 Jul 2013, Alan Stern wrote:
On Wed, 17 Jul 2013, Thomas Pugliese wrote:
Hi,
What is the expected behavior if a host controller does not implement
bus_suspend and bus_resume? I am seeing that with the HWA HCD, kworker
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Thanks for your reply.
-Original Message-
From: Ming Lei [mailto:tom.leim...@gmail.com]
Sent: Wednesday, July 17, 2013 5:52 PM
To: 김기오
Cc: Alan Stern; linux-usb@vger.kernel.org; linux-ker...@vger.kernel.org;
Mark Salter; namhyung@lge.com; Minchan Kim; Chanho Min; Jong-Sung Kim;
On Thu, Jul 18, 2013 at 3:24 AM, Alan Stern st...@rowland.harvard.edu wrote:
On Thu, 4 Jul 2013, Alan Stern wrote:
On Thu, 4 Jul 2013, Ming Lei wrote:
If so, your coming change may break ABI because as you described
that the flag should be set in the first URB of a new stream, but
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