[PATCH v2 4/4] Staging: rtl8723bs: Use !x instead of NULL comparison

If "x" is compared to NULL, use "!x" instead of it, so as to follow the kernel coding style. Signed-off-by: Shreeya Patel --- Changes in v2 -Rebase and resend. drivers/staging/rtl8723bs/hal/sdio_ops.c | 18 +- 1 file changed, 9 insertions(+), 9

[PATCH v2 3/4] Staging: rtl8723bs: Change condition to assignment

Change the conditional operator to assignment as it is not a conditional statement. Signed-off-by: Shreeya Patel --- Changes in v2 -Rebase and resend. drivers/staging/rtl8723bs/hal/sdio_ops.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git

[PATCH v2 2/4] Staging: rtl8723bs: Change names to conform to the kernel code

Change names of some variables and functions to conform to the kernel coding style. Signed-off-by: Shreeya Patel --- Changes in v2 -Rebase and resend. drivers/staging/rtl8723bs/hal/sdio_ops.c | 714 +++ 1 file changed, 357

[PATCH v2 0/4] Remove checkpatch warnings

This patchset removes some warnings generated by checkpatch for cleanup of the rtl8723bs driver. Also some additional cleanups are introduced in the *[1/4] and *[3/4] patches to make the code according to the kernel coding style. Changes in v2 -Rebase and resend the patches [2/4], [3/4] and

Re: [PATCH] usb: xhci-mtk: fix semicolon.cocci warnings

On 13.01.2018 08:35, Chunfeng Yun wrote: On Sat, 2018-01-13 at 01:46 +0800, kbuild test robot wrote: From: Fengguang Wu drivers/usb/host/xhci-mtk.c:311:2-3: Unneeded semicolon Remove unneeded semicolon. Generated by: scripts/coccinelle/misc/semicolon.cocci Fixes:

Re: [PATCH v1 1/1] usb: xhci: do not create and register shared_hcd when USB3.0 is disabled

Hi, Sorry about the delay On 04.01.2018 07:17, Thang Q. Nguyen wrote: Hi, On Sat, Dec 16, 2017 at 10:45 AM, Thang Q. Nguyen wrote: From: Tung Nguyen Currently, hcd->shared_hcd always creates and registers to the usb-core. If, for some reasons, USB3

Re: [RESEND PATCH v9] xhci : AMD Promontory USB disable port support

On 11.12.2017 11:42, Joe Lee wrote: From: Joe Lee For AMD Promontory xHCI host,although you can disable USB ports in BIOSsettings,those ports will be enabled anyway after you remove a device onthat port and re-plug it in again. It's a known limitation of the chip.As a

[PATCH 1/6] usb: dwc2: Remove version check in GSNPSID

From: Gevorg Sahakyan Only check the ID portion of the GSNPSID register and don’t check the version. This will allow the driver to work with version 4.00a and later of the DWC_hsotg IP. Signed-off-by: Gevorg Sahakyan Signed-off-by: Minas

[PATCH 6/6] usb: dwc2: Force mode optimizations

From: Vardan Mikayelyan If the dr_mode is USB_DR_MODE_OTG, forcing the mode is needed during driver probe to get the host and device specific HW parameters. Then we clear the force mode bits so that the core operates in OTG mode. The force mode bits should not be touched

[PATCH 5/6] usb: dwc2: eliminate irq parameter from dwc2_gadget_init

From: Vardan Mikayelyan The irq is available in hsotg already, so there's no need to pass it as separate function parameter. Signed-off-by: Vardan Mikayelyan Signed-off-by: Grigor Tovmasyan --- drivers/usb/dwc2/core.h | 4

[PATCH 4/6] usb: dwc2: Fix dwc2_hsotg_core_init_disconnected()

From: Vardan Mikayelyan We should call dwc2_hsotg_enqueue_setup() after properly setting lx_state. Because it may cause error-out from dwc2_hsotg_enqueue_setup() due to wrong value in lx_state. Issue can be reproduced by loading driver while connected A-Connector (start in

[PATCH 3/6] usb: dwc2: Add safety check for STSPHSERCVD intr

From: Minas Harutyunyan STSPHSERCVD (status phase received) interrupt should be handled when EP0 is in DWC2_EP0_DATA_OUT state. Sometimes STSPHSERCVD interrupt asserted , when EP0 is not in DATA_OUT state. Spurios interrupt. Signed-off-by: Minas Harutyunyan

[PATCH 2/6] usb: dwc2: Add safety check in setting of descriptor chain pointers

From: Minas Harutyunyan In some cases device sending ZLP IN on non EP0 which reassigning EP0 OUT descriptor pointer to that EP. Dedicated for EP0 OUT descriptor multiple time re-used by other EP while that descriptor already in use by EP0 OUT for SETUP transaction. As result

[PATCH 0/6] usb: dwc2: minor fixes

This series contains patches which are already have been sent in "usb: dwc2: fixes, enhancements and new features" series. That patch series was too large, and based on community feedbacks decided to split that series into small pieces. This is a first one. In this series we included only minor

[PATCH v5 01/17] phy: qcom-qmp: Fix phy pipe clock gating

From: Vivek Gautam Pipe clock comes out of the phy and is available as long as the phy is turned on. Clock controller fails to gate this clock after the phy is turned off and generates a warning. / # [ 33.048561] gcc_usb3_phy_pipe_clk status stuck at 'on' [

[PATCH v5 03/17] phy: qcom-qmp: Power-on PHY before initialization

PHY regulators which are enabled from power_on() must be ON before turning-on clocks and initializing it as part of init(). As most of the core drivers perform power_on() after init(), move PHY regulators enable to com_init() and use power_on() to only enable pipe_clk. This pipe_clk is output from

[PATCH v5 05/17] phy: qcom-qmp: Fix PHY block reset sequence

PHY block or asynchronous reset requires signal to be asserted before de-asserting. Driver is only de-asserting signal which is already low, hence reset operation is a no-op. Fix this by asserting signal first. Also, resetting requires PHY clocks to be turned ON only after reset is finished. Fix

[PATCH v5 06/17] phy: qcom-qmp: Move SERDES/PCS START after PHY reset

Driver is currently performing PHY reset after starting SERDES/PCS. As per hardware datasheet reset must be done before starting PHY. Hence, update the sequence. Signed-off-by: Manu Gautam --- drivers/phy/qualcomm/phy-qcom-qmp.c | 6 +++--- 1 file changed, 3

[PATCH v5 10/17] phy: qcom-qmp: Move register offsets to header file

New revision (v3) of QMP PHY uses different offsets for almost all of the registers. Hence, move these definitions to header file so that updated offsets can be added for QMP v3. Signed-off-by: Manu Gautam Reviewed-by: Vivek Gautam ---

[PATCH v5 07/17] phy: qcom-qusb2: Add support for different register layouts

New version of QUSB2 PHY has some registers offset changed. Add support to have register layout for a target and update the same in phy_configuration. Signed-off-by: Manu Gautam Reviewed-by: Vivek Gautam ---

[PATCH v5 09/17] phy: qcom-qusb2: Add support for QUSB2 V2 version

Use register layout to add additional registers present on QUSB2 PHY V2 version for PHY initialization. Other than new registers on V2, following two register's offset and bit definitions are different: POWERDOWN control and PLL_STATUS. Signed-off-by: Manu Gautam

[PATCH v5 12/17] dt-bindings: phy-qcom-qmp: Update bindings for QMP V3 USB PHY

Update compatible string and clock names for QMP version V3 USB PHY. Acked-by: Rob Herring Signed-off-by: Manu Gautam --- Documentation/devicetree/bindings/phy/qcom-qmp-phy.txt | 6 +- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git

[PATCH v5 14/17] phy: Add USB speed related PHY modes

Add following USB speed related PHY modes: LS (Low Speed), FS (Full Speed), HS (High Speed), SS (Super Speed) Speed related information is required by some QCOM PHY drivers to program PHY monitor resume/remote-wakeup events in suspended state. Speed is needed in order to set correct polarity of

[PATCH v5 13/17] phy: qcom-qmp: Add support for QMP V3 USB3 PHY

QMP V3 USB3 PHY is a DisplayPort (DP) and USB combo PHY with dual RX/TX lanes to support type-c. There is a separate block DP_COM for configuration related to type-c or DP. Add support for dp_com region and secondary rx/tx lanes initialization. Signed-off-by: Manu Gautam

[PATCH v5 17/17] phy: add SPDX identifier to QMP and QUSB2 PHY drivers

The SPDX identifier is a legally binding shorthand, which can be used instead of the full boiler plate text. Signed-off-by: Manu Gautam --- drivers/phy/qualcomm/phy-qcom-qmp.c | 11 +-- drivers/phy/qualcomm/phy-qcom-qusb2.c | 10 +- 2 files changed, 2

[PATCH v5 16/17] phy: qcom-qmp: Add support for runtime PM

Disable clocks and enable PHY autonomous mode to detect wakeup events when PHY is suspended. Core driver should notify speed to PHY driver to enable LFPS and/or RX_DET interrupts. Signed-off-by: Manu Gautam --- drivers/phy/qualcomm/phy-qcom-qmp.c | 177

[PATCH v5 15/17] phy: qcom-qusb2: Add support for runtime PM

Disable clocks and enable DP/DM wakeup interrupts when suspending PHY. Core driver should notify speed to PHY driver to enable appropriate DP/DM wakeup interrupts polarity in suspend state. Signed-off-by: Manu Gautam --- drivers/phy/qualcomm/phy-qcom-qusb2.c | 176

[PATCH v5 11/17] phy: qcom-qmp: Add register offsets for QMP V3 PHY

Registers offsets for QMP V3 PHY are changed from previous versions (1/2), update same in header file. Signed-off-by: Manu Gautam --- drivers/phy/qualcomm/phy-qcom-qmp.h | 149 1 file changed, 149 insertions(+) diff --git

[PATCH v5 08/17] dt-bindings: phy-qcom-qusb2: Update binding for QUSB2 V2 version

Update generic compatible string for QUSB2 V2 PHY. This will allow all targets using QUSB2 V2 use same string. Acked-by: Rob Herring Signed-off-by: Manu Gautam Reviewed-by: Vivek Gautam ---

[PATCH v5 04/17] phy: qcom-qusb2: Power-on PHY before initialization

PHY must be powered on before turning ON clocks and attempting to initialize it. Driver is exposing separate init and power_on routines for this. Apparently USB dwc3 core driver performs power-on after init. Also, poweron and init for QUSB2 PHY need to be executed together always, hence remove

[PATCH v5 02/17] phy: qcom-qmp: Adapt to clk_bulk_* APIs

From: Vivek Gautam Move from using array of clocks to clk_bulk_* APIs that are available now. Signed-off-by: Vivek Gautam Signed-off-by: Manu Gautam --- drivers/phy/qualcomm/phy-qcom-qmp.c | 50

[PATCH v5 00/17] Support for Qualcomm QUSBv2 and QMPv3 USB PHYs

QUSB-v2 and QMP-v3 USB PHYs are present on Qualcomm's 14nm and 10nm SOCs. This patch series adds support for runtime PM for these USB PHYs and adds fixes in drivers to follow PHY reset and initialization sequence as per hardware programming manual. Changes since v4: - Use SPDX License identifier.

Re: race condition between shutdown() and post_reset() resulting in deadlock

Hi, On 16-01-18 10:57, Oliver Neukum wrote: Hi, looking at your last patch I noticed something. I think it fails to work if we hit a peculiar race condition. It looks to me like we can get the following: task A pre_reset()   --> calling scsi_block_requests()

race condition between shutdown() and post_reset() resulting in deadlock

Hi, looking at your last patch I noticed something. I think it fails to work if we hit a peculiar race condition. It looks to me like we can get the following: task A pre_reset()   --> calling scsi_block_requests() task B

[PATCH v5] usb: uhci: Add clk support to uhci-platform

The Aspeed SoCs use uhci-platform. With the new dynamic clock control framework, the corresponding IP block clock must be properly enabled. This is a simplified variant of what ehci-platform does, it looks for *one* clock attached to the device, and if it's there, enables it. Signed-off-by:

[PATCH] usb: option: Add support for FS040U modem

FS040U modem is manufactured by omega, and sold by Fujisoft. This patch adds ID of the modem to use option1 driver. Interface 3 is used as qmi_wwan, so the interface is ignored. Signed-off-by: Yoshiaki Okamoto Signed-off-by: Hiroyuki Yamamoto

Re: [PATCH v4] usb: uhci: Add clk support to uhci-platform

On Tue, 2018-01-16 at 11:36 +0300, Sergei Shtylyov wrote: > Hello! > > On 1/16/2018 12:53 AM, Benjamin Herrenschmidt wrote: > > > > > The Aspeed SoCs use uhci-platform. With the new dynamic clock > > > > control framework, the corresponding IP block clock must be > > > > properly enabled. > > >

[PATCH v2] r8152: disable RX aggregation on Dell TB16 dock

r8153 on Dell TB15/16 dock corrupts rx packets. This change is suggested by Realtek. They guess that the XHCI controller doesn't have enough buffer, and their guesswork is correct, once the RX aggregation gets disabled, the issue is gone. ASMedia is currently working on a real sulotion for this

Re: [PATCH v4] usb: uhci: Add clk support to uhci-platform

Hello! On 1/16/2018 12:53 AM, Benjamin Herrenschmidt wrote: The Aspeed SoCs use uhci-platform. With the new dynamic clock control framework, the corresponding IP block clock must be properly enabled. This is a simplified variant of what ehci-platform does, it looks for *one* clock attached to