add a DT binding doc for MediaTek USB3 DRD driver
Signed-off-by: Chunfeng Yun
Acked-by: Rob Herring
---
.../devicetree/bindings/usb/mt8173-mtu3.txt| 87
1 file changed, 87 insertions(+)
create mode 100644 Documentation/devicetree/bindings/usb/mt8173-mtu3.txt
USB3 DRD driver is added for MT8173-EVB, and xHCI driver
becomes its subnode
Signed-off-by: Chunfeng Yun
---
arch/arm64/boot/dts/mediatek/mt8173-evb.dts | 46 +--
arch/arm64/boot/dts/mediatek/mt8173.dtsi| 29 +
2 files changed, 66 insertions(+), 9
This patch adds support for the MediaTek USB3 controller
integrated into MT8173. It can be configured as Dual-Role
Device (DRD), Peripheral Only and Host Only (xHCI) modes.
Signed-off-by: Chunfeng Yun
---
drivers/usb/Kconfig|2 +
drivers/usb/Makefile |1
of dual-role mode.
Additionally add optional properties of pinctrl for host only mode
Signed-off-by: Chunfeng Yun
Acked-by: Rob Herring
---
.../devicetree/bindings/usb/mt8173-xhci.txt| 54 +++-
1 file changed, 52 insertions(+), 2 deletions(-)
diff --git a
>From e60d29d748a4e9f412c9bb08458083e97d3f523d Mon Sep 17 00:00:00 2001
From: Chunfeng Yun
Date: Tue, 9 Aug 2016 16:12:31 +0800
Subject: [PATCH V5, 0/5] Add MediaTek USB3 DRD Driver
These patches introduce the MediaTek USB3 dual-role controller
driver.
The driver can be configured as Dual-R
Make IPPC register optional to support host side of dual-role mode,
due to it is moved into common glue layer for simplification.
Signed-off-by: Chunfeng Yun
---
drivers/usb/host/xhci-mtk.c | 36 +---
1 file changed, 29 insertions(+), 7 deletions(-)
diff --git
Hi,
On Thu, 2016-08-25 at 10:32 +0200, Oliver Neukum wrote:
> On Thu, 2016-08-25 at 11:05 +0800, Chunfeng Yun wrote:
> > This patch adds support for the MediaTek USB3 controller
> > integrated into MT8173. It can be configured as Dual-Role
> > Device (DRD), Peripheral Onl
On Tue, 2016-08-30 at 19:20 +0200, Greg Kroah-Hartman wrote:
> On Fri, Aug 26, 2016 at 05:38:27PM +0800, chunfeng yun wrote:
> > Hi,
> >
> > On Thu, 2016-08-25 at 10:32 +0200, Oliver Neukum wrote:
> > > On Thu, 2016-08-25 at 11:05 +0800, Chunfeng Yun wrote:
> >
of dual-role mode.
Additionally add optional properties of pinctrl for host only mode
Signed-off-by: Chunfeng Yun
Acked-by: Rob Herring
---
.../devicetree/bindings/usb/mt8173-xhci.txt| 54 +++-
1 file changed, 52 insertions(+), 2 deletions(-)
diff --git a
This patch adds support for the MediaTek USB3 controller
integrated into MT8173. It can be configured as Dual-Role
Device (DRD), Peripheral Only and Host Only (xHCI) modes.
Signed-off-by: Chunfeng Yun
---
drivers/usb/Kconfig|2 +
drivers/usb/Makefile |1
add a DT binding doc for MediaTek USB3 DRD driver
Signed-off-by: Chunfeng Yun
Acked-by: Rob Herring
---
.../devicetree/bindings/usb/mt8173-mtu3.txt| 87
1 file changed, 87 insertions(+)
create mode 100644 Documentation/devicetree/bindings/usb/mt8173-mtu3.txt
Make IPPC register optional to support host side of dual-role mode,
due to it is moved into common glue layer for simplification.
Signed-off-by: Chunfeng Yun
---
drivers/usb/host/xhci-mtk.c | 36 +---
1 file changed, 29 insertions(+), 7 deletions(-)
diff --git
USB3 DRD driver is added for MT8173-EVB, and xHCI driver
becomes its subnode
Signed-off-by: Chunfeng Yun
---
arch/arm64/boot/dts/mediatek/mt8173-evb.dts | 46 +--
arch/arm64/boot/dts/mediatek/mt8173.dtsi| 29 +
2 files changed, 66 insertions(+), 9
>From 99e428a1808c8ca91ff473d487b52ca5d355d875 Mon Sep 17 00:00:00 2001
From: Chunfeng Yun
Date: Mon, 5 Sep 2016 10:27:07 +0800
Subject: [PATCH, v6 0/5] Add MediaTek USB3 DRD Driver
These patches introduce the MediaTek USB3 dual-role controller
driver.
The driver can be configured as Dual-R
NULL pointer dereferrence will happen when class driver
wants to allocate zero length buffer and pool_max[0]
can't be used, so skip reserved pool in this case.
Signed-off-by: Chunfeng Yun
---
drivers/usb/core/buffer.c |4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --
A new compatible string, "mediatek,mt2701-u3phy", is added.
Some register settings to avoid RX sensitivity level degradation
which may arise on mt8173 platform are separated from other
platforms.
Signed-off-by: Chunfeng Yun
---
.../devicetree/bindings/phy/phy-mt65xx-usb.txt
On Fri, 2016-04-08 at 15:57 +0200, Matthias Brugger wrote:
>
> On 08/04/16 11:13, Chunfeng Yun wrote:
> > A new compatible string, "mediatek,mt2701-u3phy", is added.
> >
> > Some register settings to avoid RX sensitivity level degradation
> > which may ari
On Fri, 2016-04-08 at 07:07 -0700, Greg Kroah-Hartman wrote:
> On Fri, Apr 08, 2016 at 05:08:03PM +0800, Chunfeng Yun wrote:
> > NULL pointer dereferrence will happen when class driver
> > wants to allocate zero length buffer and pool_max[0]
> > can't be used, so skip
On Mon, 2016-04-11 at 08:07 +0300, Felipe Balbi wrote:
> Hi,
>
> chunfeng yun writes:
> > On Fri, 2016-04-08 at 07:07 -0700, Greg Kroah-Hartman wrote:
> >> On Fri, Apr 08, 2016 at 05:08:03PM +0800, Chunfeng Yun wrote:
> >> > NULL pointer dereferrence will happ
A new compatible string, "mediatek,mt2701-u3phy", is added.
Signed-off-by: Chunfeng Yun
---
.../devicetree/bindings/phy/phy-mt65xx-usb.txt |4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/phy/phy-mt65xx-usb.txt
b/Doc
A new compatible string, "mediatek,mt2701-u3phy", is added.
Some register settings to avoid RX sensitivity level degradation
which may arise on mt8173 platform are separated from other
platforms.
Signed-off-by: Chunfeng Yun
---
drivers/phy/Kconfig |5 ++-
drivers/phy/
add Matthias
sorry
On Mon, 2016-04-11 at 15:41 +0800, Chunfeng Yun wrote:
> A new compatible string, "mediatek,mt2701-u3phy", is added.
>
> Signed-off-by: Chunfeng Yun
> ---
> .../devicetree/bindings/phy/phy-mt65xx-usb.txt |4 +++-
> 1 file changed,
Hi,
On Wed, 2016-04-13 at 12:00 +0200, Matthias Brugger wrote:
>
> On 11/04/16 09:41, Chunfeng Yun wrote:
> > A new compatible string, "mediatek,mt2701-u3phy", is added.
> >
> > Signed-off-by: Chunfeng Yun
> > ---
> > .../devicetree/bindings/phy/p
Hi,
On Wed, 2016-04-13 at 18:56 +0530, Kishon Vijay Abraham I wrote:
> Hi,
>
> On Monday 11 April 2016 01:11 PM, Chunfeng Yun wrote:
> > A new compatible string, "mediatek,mt2701-u3phy", is added.
>
> how about changing the commit log to something like below?
&g
Hi,
On Wed, 2016-04-13 at 19:01 +0530, Kishon Vijay Abraham I wrote:
> Hi,
>
> On Monday 11 April 2016 01:11 PM, Chunfeng Yun wrote:
> > A new compatible string, "mediatek,mt2701-u3phy", is added.
> >
> > Some register settings to avoid RX sensitivity lev
Add a new compatible string for "mt2701"
Signed-off-by: Chunfeng Yun
Reviewed-by: Matthias Brugger
---
.../devicetree/bindings/phy/phy-mt65xx-usb.txt |4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/phy/phy-mt65xx-
Add a new OF device ID for mt2701
Some register settings to avoid RX sensitivity level degradation
which may arise on mt8173 platform are separated from other
platforms.
Signed-off-by: Chunfeng Yun
---
drivers/phy/Kconfig |5 ++-
drivers/phy/phy-mt65xx-usb3.c | 77
score's suspend completion to SPM working is always less than 20ms.
Because the syscore runs on irq disabled context, and xhci's
suspend/resume calls some sleeping functions, enable local irq
and then disable it during suspend/resume. This may be not a problem,
since only boot CPU is runing.
Si
Hi,
On Tue, 2016-04-26 at 16:11 -0700, Greg Kroah-Hartman wrote:
> On Fri, Apr 08, 2016 at 11:21:05AM -0400, Alan Stern wrote:
> > On Fri, 8 Apr 2016, Greg Kroah-Hartman wrote:
> >
> > > On Fri, Apr 08, 2016 at 05:08:03PM +0800, Chunfeng Yun wrote:
> > > > N
NULL pointer dereferrence will happen when class driver
wants to allocate zero length buffer and pool_max[0]
can't be used, so simply returns NULL in the case.
Signed-off-by: Chunfeng Yun
---
drivers/usb/core/buffer.c |3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/usb
urb allocation will fail when usbtest_alloc_urb() tries to
allocate zero length buffer, but it doesn't need it in fact,
so just skips buffer allocation in the case.
Signed-off-by: Chunfeng Yun
---
drivers/usb/misc/usbtest.c |3 +++
1 file changed, 3 insertions(+)
diff --git a/driver
Hi Mathias,
On Thu, 2016-04-21 at 10:04 +0800, Chunfeng Yun wrote:
> Click mouse after xhci suspend completion but before system suspend
> completion, system will not be waken up by mouse if the duration of
> them is larger than 20ms which is the device UFP's resume signaling
>
On Tue, 2016-05-03 at 10:51 +0300, Felipe Balbi wrote:
> Hi,
>
> chunfeng yun writes:
> > On Thu, 2016-04-21 at 10:04 +0800, Chunfeng Yun wrote:
> >> Click mouse after xhci suspend completion but before system suspend
> >> completion, system will not be wak
On Mon, 2017-01-23 at 08:02 -0600, Rob Herring wrote:
> On Sat, Jan 21, 2017 at 7:49 PM, Chunfeng Yun
> wrote:
> > Hi,
> >
> > On Sat, 2017-01-21 at 14:11 -0600, Rob Herring wrote:
> >> On Wed, Jan 18, 2017 at 02:08:27PM +0800, Chunfeng Yun wrote:
> >>
On Wed, 2017-01-25 at 00:23 +0100, Matthias Brugger wrote:
>
> On 01/20/2017 03:20 AM, Chunfeng Yun wrote:
> > On Thu, 2017-01-19 at 13:22 +0100, Matthias Brugger wrote:
> >>
> >> On 18/01/17 07:08, Chunfeng Yun wrote:
> >>> usually, the referenc
Due to the reference clock comes from 26M oscillator directly
on mt8173, and it is a fixed-clock in DTS which always turned
on, we ignore it before. But on some platforms, it comes
from PLL, and need be controlled, so here add it, no matter
it is a fixed-clock or not.
Signed-off-by: Chunfeng Yun
Some resources such as regulator, clock usually cause deferred
probe, get them earlier to avoid more ineffective processing.
Signed-off-by: Chunfeng Yun
---
drivers/usb/mtu3/mtu3_plat.c | 24
1 file changed, 12 insertions(+), 12 deletions(-)
diff --git a/drivers/usb
add 26M reference clock for ssusb and xhci nodes
Signed-off-by: Chunfeng Yun
---
arch/arm64/boot/dts/mediatek/mt8173.dtsi |6 --
1 file changed, 4 insertions(+), 2 deletions(-)
diff --git a/arch/arm64/boot/dts/mediatek/mt8173.dtsi
b/arch/arm64/boot/dts/mediatek/mt8173.dtsi
index
usually, the reference clock comes from 26M oscillator directly,
but some SoCs are not, add it for compatibility.
Signed-off-by: Chunfeng Yun
---
drivers/usb/host/xhci-mtk.c | 22 ++
drivers/usb/host/xhci-mtk.h |1 +
2 files changed, 23 insertions(+)
diff --git a
Due to the reference clock comes from 26M oscillator directly
on mt8173, and it is a fixed-clock in DTS which always turned
on, we ignore it before. But on some platforms, it comes
from PLL, and need be controlled, so here add it, no matter
it is a fixed-clock or not.
Signed-off-by: Chunfeng Yun
usually, the reference clock comes from 26M oscillator directly,
but some SoCs are not, add it for compatibility.
Signed-off-by: Chunfeng Yun
---
drivers/usb/mtu3/mtu3.h |1 +
drivers/usb/mtu3/mtu3_plat.c | 28 ++--
2 files changed, 27 insertions(+), 2
Please ignore this series of patches, due to the first version have been
merged into usb-next branch except DTS's one[PACH 4/6].
This will cause mtu3 probe failure, so I will send new patches based on
usb-next branch.
sorry
On Mon, 2017-02-06 at 17:29 +0800, Chunfeng Yun wrote:
> Du
Due to the reference clock comes from 26M oscillator directly
on mt8173, and it is a fixed-clock in DTS which always turned
on, we ignore it before. But on some platforms, it comes
from PLL, and need be controlled, so here add it, no matter
it is a fixed-clock or not.
Signed-off-by: Chunfeng Yun
Make the reference clock optional for DTS backward compatibility
and ignore the error if it does not exist.
Signed-off-by: Chunfeng Yun
---
drivers/usb/mtu3/mtu3_plat.c | 11 +--
1 file changed, 9 insertions(+), 2 deletions(-)
diff --git a/drivers/usb/mtu3/mtu3_plat.c b/drivers/usb
Make the reference clock optional for DTS backward compatibility
and ignore the error if it does not exist.
Signed-off-by: Chunfeng Yun
---
drivers/usb/host/xhci-mtk.c | 11 +--
1 file changed, 9 insertions(+), 2 deletions(-)
diff --git a/drivers/usb/host/xhci-mtk.c b/drivers/usb
On Fri, 2017-01-27 at 14:07 -0600, Rob Herring wrote:
> On Fri, Jan 20, 2017 at 04:18:41PM +0800, Chunfeng Yun wrote:
> > add a new compatible string for "mt2712", and move reference clock
> > into each port node;
> >
> > Signed-off-by: Chunfeng Yun
> &g
Increase LFPS filter threshold to avoid some fake remote wakeup
signal which cause U3 link fail and link to U2 only at about
0.01% probability.
Signed-off-by: Chunfeng Yun
---
drivers/phy/phy-mt65xx-usb3.c |9 +
1 file changed, 9 insertions(+)
diff --git a/drivers/phy/phy-mt65xx
wants to support SS, we can compound u2port0 and u3port0,
or u2port1 and u3port0, if select latter one, u2port0 is not needed.
So it's more flexible to split usb3 port into two ones and also try
best to save power by disabling unnecessary ports.
Signed-off-by: Chunfeng Yun
---
drivers/ph
the reference clock of HighSpeed port is 48M which comes from PLL;
the reference clock of SuperSpeed port is 26M which usually comes
from 26M oscillator directly, but some SoCs are not, add it for
compatibility, and put them into port node for flexibility.
Signed-off-by: Chunfeng Yun
add a new compatible string for "mt2712", and move reference clock
into each port node;
Signed-off-by: Chunfeng Yun
---
.../devicetree/bindings/phy/phy-mt65xx-usb.txt | 93 +---
1 file changed, 80 insertions(+), 13 deletions(-)
diff --git a/Documentation/
there is a reference clock for each port, HighSpeed port is 48M,
and SuperSpeed port is 26M which usually comes from 26M oscillator
directly, but some SoCs is not. it is flexible to move it into port
node.
Signed-off-by: Chunfeng Yun
---
arch/arm64/boot/dts/mediatek/mt8173.dtsi |8
There are some variations from mt2701 to mt2712:
1. banks shared by multiple ports are put back into each port,
such as SPLLC and U2FREQ;
2. add a new bank MISC for u2port, and CHIP for u3port;
3. bank's offset in each port are also rearranged;
Signed-off-by: Chunfeng Yun
---
driver
split the old SuperSpeed port node into a HighSpeed one and a new
SuperSpeed one.
Signed-off-by: Chunfeng Yun
---
arch/arm64/boot/dts/mediatek/mt8173.dtsi | 19 +--
1 file changed, 13 insertions(+), 6 deletions(-)
diff --git a/arch/arm64/boot/dts/mediatek/mt8173.dtsi
b/arch
The default value of RX detection stable time is 10us, and this
margin is too big for some critical cases which cause U3 link fail
and link to U2(probability is about 1%). So change it to 5us.
Signed-off-by: Chunfeng Yun
---
drivers/phy/phy-mt65xx-usb3.c | 18 ++
1 file
Hi,
On Wed, 2017-02-22 at 12:36 +0300, Sergei Shtylyov wrote:
> On 2/22/2017 11:55 AM, Chunfeng Yun wrote:
>
> > there is a reference clock for each port, HighSpeed port is 48M,
> > and SuperSpeed port is 26M which usually comes from 26M oscillator
> > directly, but
the reference clock of HighSpeed port is 48M which comes from PLL;
the reference clock of SuperSpeed port is 26M which usually comes
from 26M oscillator directly, but some SoCs are not, add it for
compatibility, and put them into port node for flexibility.
Signed-off-by: Chunfeng Yun
add a new compatible string for "mt2712", and move reference clock
into each port node;
Signed-off-by: Chunfeng Yun
Acked-by: Rob Herring
---
.../devicetree/bindings/phy/phy-mt65xx-usb.txt | 93 +---
1 file changed, 80 insertions(+), 13 deletions(-)
di
there is a reference clock for each port, HighSpeed port is 48M,
and SuperSpeed port is 26M which usually comes from 26M oscillator
directly, but some SoCs is not. it is flexible to move it into port
node.
Signed-off-by: Chunfeng Yun
---
arch/arm64/boot/dts/mediatek/mt8173.dtsi |8
split the old SuperSpeed port node into a HighSpeed one and a new
SuperSpeed one.
Signed-off-by: Chunfeng Yun
---
arch/arm64/boot/dts/mediatek/mt8173.dtsi | 19 +--
1 file changed, 13 insertions(+), 6 deletions(-)
diff --git a/arch/arm64/boot/dts/mediatek/mt8173.dtsi
b/arch
Increase LFPS filter threshold to avoid some fake remote wakeup
signal which cause U3 link fail and link to U2 only at about
0.01% probability.
Signed-off-by: Chunfeng Yun
---
drivers/phy/phy-mt65xx-usb3.c |9 +
1 file changed, 9 insertions(+)
diff --git a/drivers/phy/phy-mt65xx
wants to support SS, we can compound u2port0 and u3port0,
or u2port1 and u3port0, if select latter one, u2port0 is not needed.
So it's more flexible to split usb3 port into two ones and also try
best to save power by disabling unnecessary ports.
Signed-off-by: Chunfeng Yun
---
drivers/ph
The default value of RX detection stable time is 10us, and this
margin is too big for some critical cases which cause U3 link fail
and link to U2(probability is about 1%). So change it to 5us.
Signed-off-by: Chunfeng Yun
---
drivers/phy/phy-mt65xx-usb3.c | 18 ++
1 file
There are some variations from mt2701 to mt2712:
1. banks shared by multiple ports are put back into each port,
such as SPLLC and U2FREQ;
2. add a new bank MISC for u2port, and CHIP for u3port;
3. bank's offset in each port are also rearranged;
Signed-off-by: Chunfeng Yun
---
driver
hcc_params is set in xhci_gen_setup() called from usb_add_hcd(),
so checks the Maximum Primary Stream Array Size in the hcc_params
register after adding primary hcd.
Signed-off-by: Chunfeng Yun
---
drivers/usb/host/xhci-mtk.c |6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff
because hcd_priv_size is already size of xhci_hcd struct,
extra_priv_size is not needed anymore for MTK and tegra drivers.
Signed-off-by: Chunfeng Yun
---
drivers/usb/host/xhci-mtk.c |1 -
drivers/usb/host/xhci-tegra.c |1 -
2 files changed, 2 deletions(-)
diff --git a/drivers/usb
there are two warnings and a erorr when checked by checkpatch.pl
as following:
WARNING:BLOCK_COMMENT_STYLE: Block comments should align
the * on each line
ERROR:COMPLEX_MACRO: Macros with complex values should be
enclosed in parentheses
Signed-off-by: Chunfeng Yun
---
drivers/usb/host/xhci
simplify xhci_mtk_setup() and add xhci_mtk_start() for
xhci_driver_overrides struct
Signed-off-by: Chunfeng Yun
---
drivers/usb/host/xhci-mtk.c | 16 +++-
1 file changed, 11 insertions(+), 5 deletions(-)
diff --git a/drivers/usb/host/xhci-mtk.c b/drivers/usb/host/xhci-mtk.c
index
On Tue, 2017-03-07 at 17:10 +0200, Mathias Nyman wrote:
> On 07.03.2017 05:32, Chunfeng Yun wrote:
> > hcc_params is set in xhci_gen_setup() called from usb_add_hcd(),
> > so checks the Maximum Primary Stream Array Size in the hcc_params
> > register after adding primary hcd.
On Tue, 2017-03-07 at 16:57 +0200, Mathias Nyman wrote:
> On 07.03.2017 08:57, Chunfeng Yun wrote:
> > simplify xhci_mtk_setup() and add xhci_mtk_start() for
> > xhci_driver_overrides struct
> >
>
> Code itself looks fine, but it's bit unclear for me what the bene
On Thu, 2017-03-09 at 13:51 +0530, Kishon Vijay Abraham I wrote:
> Hi,
>
> On Monday 06 March 2017 07:19 PM, Chunfeng Yun wrote:
> > the reference clock of HighSpeed port is 48M which comes from PLL;
> > the reference clock of SuperSpeed port is 26M which usually comes
&g
each port has its own reference clock, the HighSpeed port is 48M,
and the SuperSpeed port is usually 26M, put them into port node for
flexibility, this can close clock if the port is not used.
Signed-off-by: Chunfeng Yun
---
drivers/phy/phy-mt65xx-usb3.c | 29 ++---
1
The default value of RX detection stable time is 10us, and this
margin is too big for some critical cases which cause U3 link fail
and link to U2(probability is about 1%). So change it to 5us.
Signed-off-by: Chunfeng Yun
---
drivers/phy/phy-mt65xx-usb3.c | 18 ++
1 file
Increase LFPS filter threshold to avoid some fake remote wakeup
signal which cause U3 link fail and link to U2 only at about
0.01% probability.
Signed-off-by: Chunfeng Yun
---
drivers/phy/phy-mt65xx-usb3.c |9 +
1 file changed, 9 insertions(+)
diff --git a/drivers/phy/phy-mt65xx
add a new compatible string for "mt2712", and move reference clock
into each port node;
Signed-off-by: Chunfeng Yun
Acked-by: Rob Herring
---
.../devicetree/bindings/phy/phy-mt65xx-usb.txt | 93 +---
1 file changed, 80 insertions(+), 13 deletions(-)
di
There are some variations from mt2701 to mt2712:
1. banks shared by multiple ports are put back into each port,
such as SPLLC and U2FREQ;
2. add a new bank MISC for u2port, and CHIP for u3port;
3. bank's offset in each port are also rearranged;
Signed-off-by: Chunfeng Yun
---
driver
split the old SuperSpeed port node into a HighSpeed one and a new
SuperSpeed one.
Signed-off-by: Chunfeng Yun
---
arch/arm64/boot/dts/mediatek/mt8173.dtsi | 19 +--
1 file changed, 13 insertions(+), 6 deletions(-)
diff --git a/arch/arm64/boot/dts/mediatek/mt8173.dtsi
b/arch
there is a reference clock for each port, HighSpeed port is 48M,
and SuperSpeed port is usually 26M. it is flexible to move it
into port node, then unused clock can be disabled.
Signed-off-by: Chunfeng Yun
---
arch/arm64/boot/dts/mediatek/mt8173.dtsi |8 ++--
1 file changed, 6
wants to support SS, we can compound u2port0 and u3port0,
or u2port1 and u3port0, if select latter one, u2port0 is not needed.
So it's more flexible to split usb3 port into two ones and also try
best to save power by disabling unnecessary ports.
Signed-off-by: Chunfeng Yun
---
drivers/ph
Hi Kishon,
Do you have any comments or suggestions on the series of patches?
Thanks a lot
On Sat, 2017-03-11 at 14:22 +0800, Chunfeng Yun wrote:
> The default value of RX detection stable time is 10us, and this
> margin is too big for some critical cases which cause U3 link fail
>
Hi,
On Tue, 2017-03-28 at 13:42 +0900, Chanwoo Choi wrote:
> This patch uses the resource-managed extcon API for extcon_register_notifier()
> and replaces the deprecated extcon API as following:
> - extcon_get_cable_state_() -> extcon_get_state()
>
> Cc: Greg Kroah-Hartman
Increase LFPS filter threshold to avoid some fake remote wakeup
signal which cause U3 link fail and link to U2 only at about
0.01% probability.
Signed-off-by: Chunfeng Yun
---
drivers/phy/phy-mt65xx-usb3.c |9 +
1 file changed, 9 insertions(+)
diff --git a/drivers/phy/phy-mt65xx
There will be a problem if SS port is diasbled and HS port extracts
100uA from SS port, so disable extract 100uA from SS port in the case,
when disable it, PA0_RG_USB20_INTR_EN should be set, otherwise HS port
only works on LS.
Signed-off-by: Chunfeng Yun
---
drivers/phy/phy-mt65xx-usb3.c
there is a reference clock for each port, HighSpeed port is 48M,
and SuperSpeed port is usually 26M. it is flexible to move it
into port node, then unused clock can be disabled.
Signed-off-by: Chunfeng Yun
---
arch/arm64/boot/dts/mediatek/mt8173.dtsi |8 ++--
1 file changed, 6
split the old SuperSpeed port node into a HighSpeed one and a new
SuperSpeed one.
Signed-off-by: Chunfeng Yun
---
arch/arm64/boot/dts/mediatek/mt8173.dtsi | 19 +--
1 file changed, 13 insertions(+), 6 deletions(-)
diff --git a/arch/arm64/boot/dts/mediatek/mt8173.dtsi
b/arch
add a new compatible string for "mt2712", and move reference clock
into each port node;
Signed-off-by: Chunfeng Yun
Acked-by: Rob Herring
---
.../devicetree/bindings/phy/phy-mt65xx-usb.txt | 93 +---
1 file changed, 80 insertions(+), 13 deletions(-)
di
each port has its own reference clock, the HighSpeed port is 48M,
and the SuperSpeed port is usually 26M, put them into port node for
flexibility, this can close clock if the port is not used.
Signed-off-by: Chunfeng Yun
---
drivers/phy/phy-mt65xx-usb3.c | 27 +--
1
There are some variations from mt2701 to mt2712:
1. banks shared by multiple ports are put back into each port,
such as SPLLC and U2FREQ;
2. add a new bank MISC for u2port, and CHIP for u3port;
3. bank's offset in each port are also rearranged;
Signed-off-by: Chunfeng Yun
---
driver
The default value of RX detection stable time is 10us, and this
margin is too big for some critical cases which cause U3 link fail
and link to U2(probability is about 1%). So change it to 5us.
Signed-off-by: Chunfeng Yun
---
drivers/phy/phy-mt65xx-usb3.c | 18 ++
1 file
wants to support SS, we can compound u2port0 and u3port0,
or u2port1 and u3port0, if select latter one, u2port0 is not needed.
So it's more flexible to split usb3 port into two ones and also try
best to save power by disabling unnecessary ports.
Signed-off-by: Chunfeng Yun
---
drivers/ph
ove probe phy before add usb_hcd patch from this series due to 4.2-rc1
already fix this issue
3. add xhci mac clocks
4. add suspend/resume
5. support remote wakeup
Chunfeng Yun (5):
dt-bindings: Add usb3.0 phy binding for MT65xx SoCs
dt-bindings: Add a binding for Mediatek xHCI host contro
add a DT binding documentation of usb3.0 phy for MT65xx
SoCs from Mediatek.
Signed-off-by: Chunfeng Yun
---
.../devicetree/bindings/usb/mt65xx-u3phy.txt | 34 ++
1 file changed, 34 insertions(+)
create mode 100644 Documentation/devicetree/bindings/usb/mt65xx-u3phy.txt
Signed-off-by: Chunfeng Yun
---
arch/arm64/boot/dts/mediatek/mt8173-evb.dts | 15 +++
arch/arm64/boot/dts/mediatek/mt8173.dtsi| 27 +++
2 files changed, 42 insertions(+)
diff --git a/arch/arm64/boot/dts/mediatek/mt8173-evb.dts
b/arch/arm64/boot/dts
MTK xhci host controller defines some extra SW scheduling
parameters for HW to minimize the scheduling effort for
synchronous and interrupt endpoints. The parameters are
put into reseved DWs of slot context and endpoint context
Signed-off-by: Chunfeng Yun
---
drivers/usb/host/Kconfig | 9
Signed-off-by: Chunfeng Yun
---
drivers/usb/phy/Kconfig | 10 +
drivers/usb/phy/Makefile | 1 +
drivers/usb/phy/phy-mt65xx-usb3.c | 856 ++
3 files changed, 867 insertions(+)
create mode 100644 drivers/usb/phy/phy-mt65xx-usb3.c
diff
add a DT binding documentation of xHCI host controller for the
MT8173 SoC from Mediatek.
Signed-off-by: Chunfeng Yun
---
.../devicetree/bindings/usb/mt8173-xhci.txt| 27 ++
1 file changed, 27 insertions(+)
create mode 100644 Documentation/devicetree/bindings/usb
hi Roger,
On Fri, 2015-07-10 at 11:31 +0300, Roger Quadros wrote:
> Hi,
>
> On 08/07/15 12:41, Chunfeng Yun wrote:
> > add a DT binding documentation of xHCI host controller for the
> > MT8173 SoC from Mediatek.
> >
> > Signed-off-by: Chunfeng Yun
> &g
hi Roger,
On Fri, 2015-07-10 at 11:31 +0300, Roger Quadros wrote:
> Hi,
>
> On 08/07/15 12:41, Chunfeng Yun wrote:
> > add a DT binding documentation of xHCI host controller for the
> > MT8173 SoC from Mediatek.
> >
> > Signed-off-by: Chunfeng Yun
> &g
hi,
On Fri, 2015-07-10 at 07:10 +0200, Sascha Hauer wrote:
> On Wed, Jul 08, 2015 at 05:41:03PM +0800, Chunfeng Yun wrote:
> > add a DT binding documentation of usb3.0 phy for MT65xx
> > SoCs from Mediatek.
> >
> > Signed-off-by: Chunfeng Yun
> > ---
> &
On Tue, 2015-07-14 at 09:45 +0200, Sascha Hauer wrote:
> On Tue, Jul 14, 2015 at 02:19:51PM +0800, chunfeng yun wrote:
> > hi,
> > On Fri, 2015-07-10 at 07:10 +0200, Sascha Hauer wrote:
> > > On Wed, Jul 08, 2015 at 05:41:03PM +0800, Chunfeng Yun wrote:
> > > &g
On Fri, 2015-07-10 at 11:31 +0300, Roger Quadros wrote:
> Hi,
>
> On 08/07/15 12:41, Chunfeng Yun wrote:
> > add a DT binding documentation of xHCI host controller for the
> > MT8173 SoC from Mediatek.
> >
> > Signed-off-by: Chunfeng Yun
> > ---
> >
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