[PATCH v2 2/2] clk: at91: Fix for PLL set_rate changes not being actually written to PLL peripheral bits

2018-04-09 Thread Marcin Ziemianowicz
ally being adjusted. Writing the multiplier and divider values to the peripheral fixes the bus running at half speed. Signed-off-by: Marcin Ziemianowicz <mar...@ziemianowicz.com> --- drivers/clk/at91/clk-pll.c | 8 1 file changed, 8 insertions(+) diff --git a/drivers/clk/at91/clk

[PATCH v2 1/2] clk: at91: Added more information logging.

2018-04-09 Thread Marcin Ziemianowicz
I noticed that when debugging some USB clocking issue that there weren't many ways to tell what the state of the USB clocking system was. This adds a few logging statements to see what the relevant code is trying to do. Signed-off-by: Marcin Ziemianowicz <mar...@ziemianowicz.com> --- drive

[PATCH v2 0/2] clk: at91: Added more information logging

2018-04-09 Thread Marcin Ziemianowicz
This is a series of patches which resolves set_rate() for the PLL not having any effect and therefore the USB Host port not working. Also, a few messages were added which may be helpful in the future when others are working with USB clocking. Changes since V1: Added patch set cover letter

Re: [PATCH 1/2] clk: at91: Added more information logging.

2018-04-08 Thread Marcin Ziemianowicz
> > adds a few logging statements to see what the relevant code is trying to > > do. > > > > Signed-off-by: Marcin Ziemianowicz <mar...@ziemianowicz.com> > > Your "From:" line doesn't match this name :( Ah drat, I knew I did something wrong. You suggested