Hi,
On 6/11/2018 12:06 PM, Julien Massot wrote:
Hi,
On 5/31/2018 4:17 PM, Manu Gautam wrote:
Move from dwc3-of-simple to dwc3-qcom glue driver to
support peripheral mode which requires qscratch wrapper
programming on VBUS event.
I would like to test usb otg as peripheral role, but that's
s since v1:
- Update unit address of DT node as per Doug's comment
arch/arm64/boot/dts/qcom/apq8096-db820c.dtsi | 6 --
arch/arm64/boot/dts/qcom/msm8996.dtsi| 10 ++
2 files changed, 10 insertions(+), 6 deletions(-)
Tested on DB820c. Works fine.
Tested-by: Vivek Gautam
On 4/3/2018 3:49 PM, Masahiro Yamada wrote:
2018-04-03 17:46 GMT+09:00 Philipp Zabel :
On Tue, 2018-04-03 at 17:30 +0900, Masahiro Yamada wrote:
2018-04-03 17:00 GMT+09:00 Philipp Zabel :
On Thu, 2018-03-29 at 15:07 +0900, Masahiro Yamada
0x220
> +#defineQUSB2PHY_IMP_CTRL2 0x224
> +#defineQUSB2PHY_CHG_CTRL2 0x23c
nit: Replace these tabs with simple spaces.
Rest all look good.
Reviewed-by: Vivek Gautam <vivek.gau...@codeaurora.or
t;mgau...@codeaurora.org>
> ---
LGTM.
Reviewed-by: Vivek Gautam <vivek.gau...@codeaurora.org>
> drivers/phy/qualcomm/phy-qcom-qusb2.c | 149
> +-
> 1 file changed, 109 insertions(+), 40 deletions(-)
>
> diff --git a/drivers/phy/qualcomm/phy-qcom
On Fri, Jan 12, 2018 at 2:16 PM, Manu Gautam <mgau...@codeaurora.org> wrote:
> Hi Vivek,
>
>
> On 1/12/2018 2:14 PM, Vivek Gautam wrote:
>> On Wed, Jan 3, 2018 at 4:58 PM, Manu Gautam <mgau...@codeaurora.org> wrote:
>>> PHY block or asynchronous reset requi
dev, "%s reset assert failed\n",
> + cfg->reset_list[i]);
> + goto err_rst_assert;
> + }
> }
>
> - for (i = 0; i < cfg->num_resets; i++) {
> + for (i = cfg->num_resets - 1; i >= 0; i--) {
Do we a dependency o
> after init. Also, poweron and init for QUSB2 PHY
> need to be executed together always, hence remove
> poweron callback from phy_ops and explicitly perform
> this from init, similar changes needed for poweroff.
>
> Signed-off-by: Manu Gautam <mgau...@codeaurora.org>
>
On Wed, Jan 3, 2018 at 4:58 PM, Manu Gautam wrote:
> PHY regulators which are enabled from power_on() must be ON
> before turning-on clocks and initializing it as part of init().
> As most of the core drivers perform power_on() after init(), move
> PHY regulators enable to
Hi Manu,
On Wed, Jan 3, 2018 at 4:58 PM, Manu Gautam wrote:
> New revision (v3) of QMP PHY uses different offsets
> for almost all of the registers. Hence, move these
> definitions to header file so that updated offsets
> can be added for QMP v3.
>
> Signed-off-by: Manu
Hi Manu,
On Tue, Nov 21, 2017 at 2:53 PM, Manu Gautam <mgau...@codeaurora.org> wrote:
> From: Vivek Gautam <vivek.gau...@codeaurora.org>
>
> Move from using array of clocks to clk_bulk_* APIs that
> are available now.
>
> Signed-off-by: Vivek Gautam <vivek.ga
On 11/21/2017 02:53 PM, Manu Gautam wrote:
New version of QUSB2 PHY has some registers offset changed.
Add support to have register layout for a target and update
the same in phy_configuration.
Signed-off-by: Manu Gautam
---
drivers/phy/qualcomm/phy-qcom-qusb2.c |
Hi Adam,
On Mon, Aug 28, 2017 at 10:05 PM, Adam Wallis wrote:
> The dma ops from the parent DWC device are not getting passed to the
> child xhci-hcd device. This patch makes use of
> platform_device_register_full to set the DMA ops. For the DT/OF case,
> dma_ops were
On Wed, Aug 2, 2017 at 10:39 AM, Kishon Vijay Abraham I <kis...@ti.com> wrote:
> Vivek,
>
> On Monday 31 July 2017 10:58 AM, Vivek Gautam wrote:
>> Hi Kishon,
>>
>>
>> On Tue, Jun 20, 2017 at 11:27 AM, Vivek Gautam
>> <vivek.gau...@codeaurora.or
Hi Kishon,
On Tue, Jun 20, 2017 at 11:27 AM, Vivek Gautam
<vivek.gau...@codeaurora.org> wrote:
> Fixing the clk enable failure path in qcom_qmp_phy_init()
> and cleanup the reset control deassertion failure path in
> qcom_qmp_phy_com_init().
>
> Fixes: e78f3d15e115 ("
Fixing the clk enable failure path in qcom_qmp_phy_init()
and cleanup the reset control deassertion failure path in
qcom_qmp_phy_com_init().
Fixes: e78f3d15e115 ("phy: qcom-qmp: new qmp phy driver for qcom-chipsets")
Cc: Kishon Vijay Abraham I <kis...@ti.com>
Signed-off-
Hi Philipp,
On 06/19/2017 05:48 PM, Philipp Zabel wrote:
Hi Vivek,
On Tue, 2017-06-13 at 12:16 +0530, Vivek Gautam wrote:
[...]
@@ -102,18 +94,6 @@ static inline struct reset_control
*__devm_reset_control_get(
return optional ? NULL : ERR_PTR(-ENOTSUPP);
}
-static inline
pmc driver to use the new set of
reset control array APIs.
Philipp Zabel (2):
reset: use kref for reference counting
reset: hide reset control arrays behind struct reset_control
Vivek Gautam (4):
reset: Add APIs to manage array of resets
usb: dwc3: of-simple: Re-order resource handl
struct reset_control to
avoid having to introduce new API functions for array (de)assert/reset.
Cc: Vivek Gautam <vivek.gau...@codeaurora.org>
Cc: Jon Hunter <jonath...@nvidia.com>
Signed-off-by: Philipp Zabel <p.za...@pengutronix.de>
---
drivers/r
Hi,
On Wed, May 31, 2017 at 7:53 PM, Jon Hunter <jonath...@nvidia.com> wrote:
>
> On 22/05/17 12:23, Vivek Gautam wrote:
>> Make use of reset_control_array_*() set of APIs to manage
>> an array of reset controllers available with the device.
>>
>> Cc: Jon
use the new set of
reset control array APIs.
Vivek Gautam (4):
usb: dwc3: of-simple: Re-order resource handling in remove
reset: Add APIs to manage array of resets
usb: dwc3: of-simple: Add support to get resets for the device
soc/tegra: pmc: Use the new reset APIs to manage re
order.
Cc: Felipe Balbi <ba...@kernel.org>
Cc: Jon Hunter <jonath...@nvidia.com>
Cc: Philipp Zabel <p.za...@pengutronix.de>
Signed-off-by: Vivek Gautam <vivek.gau...@codeaurora.org>
---
drivers/reset/core.c | 204 ++
inc
Add support to get a list of resets available for the device.
These resets must be kept de-asserted until the device is
in use.
Cc: Felipe Balbi <ba...@kernel.org>
Cc: Philipp Zabel <p.za...@pengutronix.de>
Signed-off-by: Vivek Gautam <vivek.gau...@codeaurora.org>
---
dri
Move clock handling after of_platform_depopulate to achieve
a sequence that is reverse of the probe sequence.
Cc: Felipe Balbi <ba...@kernel.org>
Signed-off-by: Vivek Gautam <vivek.gau...@codeaurora.org>
---
- new patch in this series.
drivers/usb/dwc3/dwc3-of-simple.c | 4
Make use of reset_control_array_*() set of APIs to manage
an array of reset controllers available with the device.
Cc: Jon Hunter <jonath...@nvidia.com>
Cc: Thierry Reding <tred...@nvidia.com>
Cc: Philipp Zabel <p.za...@pengutronix.de>
Signed-off-by: Vivek Gautam <vivek.
On 05/16/2017 03:40 PM, Kishon Vijay Abraham I wrote:
Hi Vivek,
On Thursday 11 May 2017 12:17 PM, Vivek Gautam wrote:
Adding vendor specific directories in phy to group
phy drivers under their respective vendor umbrella.
Also updated the MAINTAINERS file to reflect the correct
directory
On 05/12/2017 02:15 PM, Kishon Vijay Abraham I wrote:
Hi Vivek,
On Thursday 11 May 2017 12:17 PM, Vivek Gautam wrote:
Adding vendor specific directories in phy to group
phy drivers under their respective vendor umbrella.
Also updated the MAINTAINERS file to reflect the correct
directory
Ulpi phy header is not used for anything. Remove the same
from qcom-hs and qcom-hsic phy drivers.
Signed-off-by: Vivek Gautam <vivek.gau...@codeaurora.org>
Suggested-by: Stephen Boyd <stephen.b...@linaro.org>
Cc: Kishon Vijay Abraham I <kis...@ti.com>
Cc: linux-arm-ker...@list
Although ULPI phy is currently being used by tusb1210,
there can be other consumers too in future. So move this
to the includes path for phy.
Signed-off-by: Vivek Gautam <vivek.gau...@codeaurora.org>
Cc: Stephen Boyd <stephen.b...@linaro.org>
Cc: Heikki Krogerus <heikki.kroge...@
Adding vendor specific directories in phy to group
phy drivers under their respective vendor umbrella.
Also updated the MAINTAINERS file to reflect the correct
directory structure for phy drivers.
Signed-off-by: Vivek Gautam <vivek.gau...@codeaurora.org>
Acked-by: Heiko Stuebner <he...@
On Tue, Apr 25, 2017 at 4:41 PM, Jon Hunter <jonath...@nvidia.com> wrote:
>
> On 25/04/17 12:06, Vivek Gautam wrote:
>> On 04/25/2017 04:24 PM, Jon Hunter wrote:
>>> On 25/04/17 11:33, Philipp Zabel wrote:
>>>> On Tue, 2017-04-25 at 11:05 +0100, Jon Hunte
On 04/25/2017 04:24 PM, Jon Hunter wrote:
On 25/04/17 11:33, Philipp Zabel wrote:
On Tue, 2017-04-25 at 11:05 +0100, Jon Hunter wrote:
On 25/04/17 05:15, Vivek Gautam wrote:
On 04/24/2017 06:15 PM, Jon Hunter wrote:
On 18/04/17 12:21, Vivek Gautam wrote:
Make use of reset_control_array_
On 04/24/2017 06:15 PM, Jon Hunter wrote:
On 18/04/17 12:21, Vivek Gautam wrote:
Make use of reset_control_array_*() set of APIs to manage
an array of reset controllers available with the device.
Before we apply this patch, I need to check to see if the order of the
resets managed by the PMC
On 04/19/2017 04:02 PM, Philipp Zabel wrote:
On Tue, 2017-04-18 at 16:51 +0530, Vivek Gautam wrote:
Add support to get a list of resets available for the device.
These resets must be kept de-asserted until the device is
in use.
Cc: Felipe Balbi <ba...@kernel.org>
Cc: Philipp Zabel
Hi Philipp,
On 04/19/2017 04:01 PM, Philipp Zabel wrote:
On Tue, 2017-04-18 at 16:51 +0530, Vivek Gautam wrote:
Many devices may want to request a bunch of resets
and control them. So it's better to manage them as an
array. Add APIs to _get(), _assert(), and _deassert()
an array
On 04/19/2017 03:55 PM, Philipp Zabel wrote:
On Tue, 2017-04-18 at 16:51 +0530, Vivek Gautam wrote:
Count number of reset phandles available with the device node
to know the resets a given device has.
Cc: Philipp Zabel <p.za...@pengutronix.de>
Signed-off-by: Vivek Gautam <
Many devices may want to request a bunch of resets
and control them. So it's better to manage them as an
array. Add APIs to _get(), _assert(), and _deassert()
an array of reset_control.
Cc: Philipp Zabel <p.za...@pengutronix.de>
Signed-off-by: Vivek Gautam <vivek.gau...@codea
Make use of reset_control_array_*() set of APIs to manage
an array of reset controllers available with the device.
Cc: Thierry Reding <tred...@nvidia.com>
Cc: Philipp Zabel <p.za...@pengutronix.de>
Signed-off-by: Vivek Gautam <vivek.gau...@codeaurora.org>
---
drivers/so
Count number of reset phandles available with the device node
to know the resets a given device has.
Cc: Philipp Zabel <p.za...@pengutronix.de>
Signed-off-by: Vivek Gautam <vivek.gau...@codeaurora.org>
---
drivers/reset/core.c | 23 +++
include/linux/reset.h |
the new set of
reset control array APIs.
Vivek Gautam (4):
reset: Add API to count number of reset available with device
reset: Add APIs to manage array of resets
usb: dwc3: of-simple: Add support to get resets for the device
soc/tegra: pmc: Use the new reset APIs to manage reset controllers
Add support to get a list of resets available for the device.
These resets must be kept de-asserted until the device is
in use.
Cc: Felipe Balbi <ba...@kernel.org>
Cc: Philipp Zabel <p.za...@pengutronix.de>
Signed-off-by: Vivek Gautam <vivek.gau...@codeaurora.org>
---
dri
On 2017-04-10 10:52, Kishon Vijay Abraham I wrote:
On Friday 07 April 2017 01:37 AM, Vivek Gautam wrote:
The driver uses clock provider interface, and therefore
it fails to build when enabled for COMPILE_TEST, since
COMMON_CLK is not enabled at that time.
So, make PHY_QCOM_QMP depend
m>
Signed-off-by: Vivek Gautam <vivek.gau...@codeaurora.org>
---
Hi Kishon,
This patch is fixing the build failures for architectures
such as, tile, and ia64, that don't enable COMMON_CLK by default.
You can either squash this into the qmp phy driver patch,
or put it as a separate patch with
On 04/06/2017 03:41 PM, Kishon Vijay Abraham I wrote:
On Thursday 06 April 2017 11:21 AM, Vivek Gautam wrote:
Hi Kishon,
Here's the series with fixed checkpatch warnings/checks.
Please pick it for phy/next.
This patch series adds couple of PHY drivers for Qualcomm chipsets.
a) qcom-qusb2
Qualcomm chipsets have QUSB2 phy controller that provides
HighSpeed functionality for DWC3 controller.
Adding dt binding information for the same.
Signed-off-by: Vivek Gautam <vivek.gau...@codeaurora.org>
Reviewed-by: Stephen Boyd <sb...@codeaurora.org>
Acked-by: Rob Herring <
://patchwork.kernel.org/patch/9567767/
[2] https://patchwork.kernel.org/patch/9567779/
[3] https://github.com/vivekgautam1/linux/tree/linux-v4.11-rc5-qmp-phy-db820c
[4] https://lkml.org/lkml/2017/3/20/407
Vivek Gautam (4):
dt-bindings: phy: Add support for QUSB2 phy
phy: qcom-qusb2: New driver
Qualcomm SOCs have QMP phy controller that provides support
to a number of controller, viz. PCIe, UFS, and USB.
Add a new driver, based on generic phy framework, for this
phy controller.
Signed-off-by: Vivek Gautam <vivek.gau...@codeaurora.org>
Tested-by: Srinivas Kandagatla <sriniva
Qualcomm chipsets have QMP phy controller that provides
support to a number of controller, viz. PCIe, UFS, and USB.
Adding dt binding information for the same.
Signed-off-by: Vivek Gautam <vivek.gau...@codeaurora.org>
Reviewed-by: Stephen Boyd <sb...@codeaurora.org>
Acked-by: Ro
PHY transceiver driver for QUSB2 phy controller that provides
HighSpeed functionality for DWC3 controller present on
Qualcomm chipsets.
Signed-off-by: Vivek Gautam <vivek.gau...@codeaurora.org>
Reviewed-by: Stephen Boyd <sb...@codeaurora.org>
---
Changes since v7:
- Fixed 'checkpa
Hi Kishon,
On Wed, Apr 5, 2017 at 7:08 PM, Kishon Vijay Abraham I <kis...@ti.com> wrote:
> Hi Vivek,
>
> On Wednesday 05 April 2017 06:02 PM, Vivek Gautam wrote:
>> This patch series adds couple of PHY drivers for Qualcomm chipsets.
>> a) qcom-qusb2 phy driver: t
Qualcomm SOCs have QMP phy controller that provides support
to a number of controller, viz. PCIe, UFS, and USB.
Add a new driver, based on generic phy framework, for this
phy controller.
Signed-off-by: Vivek Gautam <vivek.gau...@codeaurora.org>
Tested-by: Srinivas Kandagatla <sriniva
Qualcomm chipsets have QMP phy controller that provides
support to a number of controller, viz. PCIe, UFS, and USB.
Adding dt binding information for the same.
Signed-off-by: Vivek Gautam <vivek.gau...@codeaurora.org>
Acked-by: Rob Herring <r...@kernel.org>
---
Changes since
Qualcomm chipsets have QUSB2 phy controller that provides
HighSpeed functionality for DWC3 controller.
Adding dt binding information for the same.
Signed-off-by: Vivek Gautam <vivek.gau...@codeaurora.org>
Acked-by: Rob Herring <r...@kernel.org>
---
Changes since v6:
- Dropped 'vd
PHY transceiver driver for QUSB2 phy controller that provides
HighSpeed functionality for DWC3 controller present on
Qualcomm chipsets.
Signed-off-by: Vivek Gautam <vivek.gau...@codeaurora.org>
Reviewed-by: Stephen Boyd <sb...@codeaurora.org>
---
Changes since v6:
- Dropped 'vdd-ph
://lkml.org/lkml/2017/3/20/407
Vivek Gautam (4):
dt-bindings: phy: Add support for QUSB2 phy
phy: qcom-qusb2: New driver for QUSB2 PHY on Qcom chips
dt-bindings: phy: Add support for QMP phy
phy: qcom-qmp: new qmp phy driver for qcom-chipsets
.../devicetree/bindings/phy/qcom-qmp-phy.txt
On 04/04/2017 11:58 PM, Stephen Boyd wrote:
On 03/20, Vivek Gautam wrote:
diff --git a/Documentation/devicetree/bindings/phy/qcom-qusb2-phy.txt
b/Documentation/devicetree/bindings/phy/qcom-qusb2-phy.txt
new file mode 100644
index ..a6d19acde9e0
--- /dev/null
+++ b/Documentation
Hi Philipp,
On 04/04/2017 06:17 PM, Philipp Zabel wrote:
Hi Vivek,
On Tue, 2017-04-04 at 16:09 +0530, Vivek Gautam wrote:
[...]
I'd prefer to mirror the gpiod API a little, and to have the number
contained in the array structure, similar to struct gpio_descs:
[...]
Alright, i can update
my comments inline.
On Mon, 2017-04-03 at 19:12 +0530, Vivek Gautam wrote:
Many devices may want to request a bunch of resets
and control them. So it's better to manage them as an
array. Add APIs to _get(), _assert(), and _deassert()
an array of reset_control.
Cc: Philipp Zabel <p
:
https://github.com/0day-ci/linux/commits/Vivek-Gautam/reset-APIs-to-manage-a-list-of-resets/20170404-111639
base: https://git.kernel.org/pub/scm/linux/kernel/git/balbi/usb.git next
config: x86_64-randconfig-x004-201714 (attached as .config)
compiler: gcc-6 (Debian 6.2.0-3) 6.2.0 20160901
Many devices may want to request a bunch of resets
and control them. So it's better to manage them as an
array. Add APIs to _get(), _assert(), and _deassert()
an array of reset_control.
Cc: Philipp Zabel <p.za...@pengutronix.de>
Signed-off-by: Vivek Gautam <vivek.gau...@codea
Count number of reset phandles available with the device node
to know the resets a given device has.
Cc: Philipp Zabel <p.za...@pengutronix.de>
Signed-off-by: Vivek Gautam <vivek.gau...@codeaurora.org>
---
Changes since v1:
- Handling the error path by returning error code
Add support to get a list of resets available for the device.
These resets must be kept de-asserted until the device is
in use.
Cc: Felipe Balbi <ba...@kernel.org>
Cc: Philipp Zabel <p.za...@pengutronix.de>
Signed-off-by: Vivek Gautam <vivek.gau...@codeaurora.org>
---
Changes
target for dwc3-of-simple driver.
-- Build tested for tegra/pmc driver. Needs testing.
[1] https://lkml.org/lkml/2017/2/22/12
[2] https://lkml.org/lkml/2017/2/22/11
Vivek Gautam (4):
reset: Add API to count number of reset available with device
reset: Add APIs to manage array of resets
usb
Make use of reset_control_array_*() set of APIs to manage
an array of reset controllers available with the device.
Cc: Thierry Reding <tred...@nvidia.com>
Cc: Philipp Zabel <p.za...@pengutronix.de>
Signed-off-by: Vivek Gautam <vivek.gau...@codeaurora.org>
---
Changes since v1:
On 03/20/2017 07:24 PM, Vivek Gautam wrote:
This patch series adds couple of PHY drivers for Qualcomm chipsets.
a) qcom-qusb2 phy driver: that provides High Speed USB functionality.
b) qcom-qmp phy driver: that is a combo phy providing support for
USB3, PCIe, UFS and few other controllers
/lists/arm-kernel/msg569990.html
[2] https://patchwork.kernel.org/patch/9567767/
[3] https://patchwork.kernel.org/patch/9567779/
[4] https://github.com/vivekgautam1/linux/tree/linux-phy-next-qcom-phy-db820c
Vivek Gautam (4):
dt-bindings: phy: Add support for QUSB2 phy
phy: qcom-qusb2: New driver
Qualcomm chipsets have QUSB2 phy controller that provides
HighSpeed functionality for DWC3 controller.
Adding dt binding information for the same.
Signed-off-by: Vivek Gautam <vivek.gau...@codeaurora.org>
Acked-by: Rob Herring <r...@kernel.org>
---
Changes since v5:
- Removed le
PHY transceiver driver for QUSB2 phy controller that provides
HighSpeed functionality for DWC3 controller present on
Qualcomm chipsets.
Signed-off-by: Vivek Gautam <vivek.gau...@codeaurora.org>
Reviewed-by: Stephen Boyd <sb...@codeaurora.org>
---
Changes since v5:
- Rebased o
Qualcomm chipsets have QMP phy controller that provides
support to a number of controller, viz. PCIe, UFS, and USB.
Adding dt binding information for the same.
Signed-off-by: Vivek Gautam <vivek.gau...@codeaurora.org>
Acked-by: Rob Herring <r...@kernel.org>
---
Changes since v5:
-
Qualcomm SOCs have QMP phy controller that provides support
to a number of controller, viz. PCIe, UFS, and USB.
Add a new driver, based on generic phy framework, for this
phy controller.
Signed-off-by: Vivek Gautam <vivek.gau...@codeaurora.org>
Tested-by: Srinivas Kandagatla <sriniva
Ulpi phy header is not used for anything. Remove the same
from qcom-hs and qcom-hsic phy drivers.
Signed-off-by: Vivek Gautam <vivek.gau...@codeaurora.org>
Suggested-by: Stephen Boyd <stephen.b...@linaro.org>
Cc: Kishon Vijay Abraham I <kis...@ti.com>
Cc: linux-arm-ker...@list
] https://www.spinics.net/lists/arm-kernel/msg568370.html
Signed-off-by: Vivek Gautam <vivek.gau...@codeaurora.org>
Cc: Kishon Vijay Abraham I <kis...@ti.com>
Cc: linux-arm-ker...@lists.infradead.org
Cc: linux-arm-...@vger.kernel.org
Cc: linux-ker...@vger.kernel.org
Cc: linux-usb@vge
Adding vendor specific directories in phy to group
phy drivers under their respective vendor umbrella.
Also updated the MAINTAINERS file to reflect the correct
directory structure for phy drivers.
Signed-off-by: Vivek Gautam <vivek.gau...@codeaurora.org>
Acked-by: Heiko Stuebner <he...@
Although ULPI phy is currently being used by tusb1210,
there can be other consumers too in future. So move this
to the includes path for phy.
Signed-off-by: Vivek Gautam <vivek.gau...@codeaurora.org>
Cc: Stephen Boyd <stephen.b...@linaro.org>
Cc: Heikki Krogerus <heikki.kroge...@
On Tue, Jan 31, 2017 at 12:55 AM, Shuah Khan wrote:
> Change goto labels to meaningful names from a series of errNs.
>
> Signed-off-by: Shuah Khan
> ---
>
> Rebased to usb-next
>
> drivers/usb/dwc3/dwc3-exynos.c | 22 +++---
> 1
Hi,
On 03/15/2017 04:15 PM, Philipp Zabel wrote:
On Wed, 2017-02-22 at 10:54 +0530, Vivek Gautam wrote:
Add support to get a list of resets available for the device.
These resets must be kept de-asserted until the device is
in use.
Cc: Felipe Balbi <ba...@kernel.org>
Signed-off-by:
Hi Philipp,
On Wed, Mar 15, 2017 at 4:10 PM, Philipp Zabel <p.za...@pengutronix.de> wrote:
> Hi Vivek,
>
> On Fri, 2017-03-10 at 20:10 +0530, Vivek Gautam wrote:
>> Hi Philipp,
>>
>>
>> On Wed, Feb 22, 2017 at 10:54 AM, Vivek Gautam
>> <vivek
On Wed, Mar 15, 2017 at 1:38 PM, Heiko Stübner <he...@sntech.de> wrote:
> Am Dienstag, 14. März 2017, 11:52:50 CET schrieb Vivek Gautam:
>> Adding vendor specific directories in phy to group
>> phy drivers under their respective vendor umbrella.
>>
>> Also update
Hi Krzysztof,
On 03/14/2017 12:14 PM, Krzysztof Kozlowski wrote:
On Tue, Mar 14, 2017 at 8:22 AM, Vivek Gautam
<vivek.gau...@codeaurora.org> wrote:
Adding vendor specific directories in phy to group
phy drivers under their respective vendor umbrella.
Also updated the MAINTAINER
Adding vendor specific directories in phy to group
phy drivers under their respective vendor umbrella.
Also updated the MAINTAINERS file to reflect the correct
directory structure for phy drivers.
Signed-off-by: Vivek Gautam <vivek.gau...@codeaurora.org>
Acked-by: Heiko Stuebner <he...@
Adding vendor specific directories in phy to group
phy drivers under their respective vendor umbrella.
Also updated the MAINTAINERS file to reflect the correct
directory structure for phy drivers.
Signed-off-by: Vivek Gautam <vivek.gau...@codeaurora.org>
Acked-by: Heiko Stuebner <he...@
Hi Philipp,
On Wed, Feb 22, 2017 at 10:54 AM, Vivek Gautam
<vivek.gau...@codeaurora.org> wrote:
> Count number of reset phandles available with the device node
> to know the resets a given device has.
>
> Cc: Philipp Zabel <p.za...@pengutronix.de>
> Signed-off-
On Fri, Mar 10, 2017 at 4:54 PM, Felipe Balbi <ba...@kernel.org> wrote:
> Vivek Gautam <vivek.gau...@codeaurora.org> writes:
>
>> Add support to get a list of resets available for the device.
>> These resets must be kept de-asserted until the device is
>>
On Sat, Feb 25, 2017 at 9:20 AM, Chanwoo Choi <cwcho...@gmail.com> wrote:
> 2017-02-25 12:46 GMT+09:00 Chanwoo Choi <cwcho...@gmail.com>:
>> Hi,
>>
>> 2017-02-24 21:02 GMT+09:00 Roger Quadros <rog...@ti.com>:
>>> +Chanwoo
>>>
&g
On 02/24/2017 06:27 AM, Peter Chen wrote:
On Thu, Feb 23, 2017 at 02:04:50PM +0530, Vivek Gautam wrote:
On 02/16/2017 06:36 PM, Roger Quadros wrote:
dra7 OTG core limits the host controller to USB2.0 (high-speed) mode
when we're operating in dual-role.
We work around that by bypassing
On 02/16/2017 06:36 PM, Roger Quadros wrote:
dra7 OTG core limits the host controller to USB2.0 (high-speed) mode
when we're operating in dual-role.
We work around that by bypassing the OTG core and reading the
extcon framework directly for ID/VBUS events.
Signed-off-by: Roger Quadros
Count number of reset phandles available with the device node
to know the resets a given device has.
Cc: Philipp Zabel <p.za...@pengutronix.de>
Signed-off-by: Vivek Gautam <vivek.gau...@codeaurora.org>
---
Based on torvald's master branch.
include/linux/reset.h | 16
Add support to get a list of resets available for the device.
These resets must be kept de-asserted until the device is
in use.
Cc: Felipe Balbi <ba...@kernel.org>
Signed-off-by: Vivek Gautam <vivek.gau...@codeaurora.org>
---
Based on torvald's master branch.
drivers/usb/dwc3/dwc3
system firmware or hardware.
Cc: Baolin Wang <baolin.w...@linaro.org>
Cc: Vivek Gautam <vivek.gau...@codeaurora.org>
Cc: Alexander Sverdlin <alexander.sverd...@nokia.com>
Cc: Mathias Nyman <mathias.ny...@linux.intel.com>
Signed-off-by: Arnd Bergmann <a...@arndb.de>
ev. sysdev is pointing to device that
>>>> is known to the system firmware or hardware.
>>>>
>>>> Signed-off-by: Arnd Bergmann <a...@arndb.de>
>>>> Signed-off-by: Sriram Dash <sriram.d...@nxp.com>
>>>> Tested-by: Baolin Wa
>>>
>>> Signed-off-by: Arnd Bergmann <a...@arndb.de>
>>> Signed-off-by: Sriram Dash <sriram.d...@nxp.com>
>>> Tested-by: Baolin Wang <baolin.w...@linaro.org>
>>> Tested-by: Vivek Gautam <vivek.gau...@codeaurora.org>
>>> Tested-by:
On Thu, Feb 9, 2017 at 1:19 PM, Roger Quadros <rog...@ti.com> wrote:
> Vivek,
>
> On 09/02/17 08:42, Vivek Gautam wrote:
>> Hi Roger,
>>
>> On Mon, Jan 23, 2017 at 4:49 PM, Roger Quadros <rog...@ti.com> wrote:
>>> Hi,
>>>
>>> We r
Hi Roger,
On Mon, Jan 23, 2017 at 4:49 PM, Roger Quadros wrote:
> Hi,
>
> We rely on the OTG controller block to provide us with
> VBUS and ID line status via an interrupt.
>
> This is then used to switch the controller between host, peripheral
> and idle roles based on the
Arnd Bergmann <a...@arndb.de>
> Signed-off-by: Sriram Dash <sriram.d...@nxp.com>
> Tested-by: Baolin Wang <baolin.w...@linaro.org>
> Tested-by: Brian Norris <briannor...@chromium.org>
> Tested-by: Alexander Sverdlin <alexander.sverd...@nokia.com>
> Tested-
are or hardware.
>> >
>> > Signed-off-by: Arnd Bergmann <a...@arndb.de>
>> > Signed-off-by: Sriram Dash <sriram.d...@nxp.com>
>> > Tested-by: Baolin Wang <baolin.w...@linaro.org>
>> > Tested-by: Vivek Gautam <vivek.gau...@codeaurora.or
sysdev. sysdev is pointing to device that
> is known to the system firmware or hardware.
>
> Signed-off-by: Arnd Bergmann <a...@arndb.de>
> Signed-off-by: Sriram Dash <sriram.d...@nxp.com>
> Tested-by: Baolin Wang <baolin.w...@linaro.org>
> Tested-by: Vivek Gauta
On 01/20/2017 02:00 PM, Roger Quadros wrote:
Vivek,
On 19/01/17 17:15, vivek.gau...@codeaurora.org wrote:
Hi Roger,
On 2017-01-19 17:45, Roger Quadros wrote:
Vivek,
On 19/01/17 13:56, Vivek Gautam wrote:
Hi,
On Wed, Jun 22, 2016 at 2:00 PM, Roger Quadros <rog...@ti.com> wrote:
L
Hi Roger,
On 2017-01-19 17:45, Roger Quadros wrote:
Vivek,
On 19/01/17 13:56, Vivek Gautam wrote:
Hi,
On Wed, Jun 22, 2016 at 2:00 PM, Roger Quadros <rog...@ti.com> wrote:
Luckily hit this thread while checking about DRD role functionality
for DWC3.
On 22/06/16 11:14, Felipe
Hi,
On Wed, Jun 22, 2016 at 2:00 PM, Roger Quadros wrote:
Luckily hit this thread while checking about DRD role functionality for DWC3.
> On 22/06/16 11:14, Felipe Balbi wrote:
>>
>> Hi,
>>
>> Roger Quadros writes:
>>> For the real use case, some Carplay
e so extra
> calls are not a problem. No extra checks means less code.
>
> Also the current code seems to be more in line with the rest
> of the kernel.
What functionality is missing without the suspend clock? Would
it make sense to change the info. message to include what it
means. At the mo
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