Re: [PATCH v3 4/4] usb: roles: intel_xhci: Enable runtime PM

[sathyanarayanan kuppuswamy]

Hi,


On 05/24/2018 01:18 AM, Heikki Krogerus wrote:

This fixes an issue where the mux does not get configured
when the parent device is suspended. The registers for this
mux are mapped to the parent device MMIO (usually xHCI PCI
device), so in order for the driver to be able to program
the registers, the parent device must be resumed.

Reported-by: Sathyanarayanan Kuppuswamy <sathyanarayanan.kuppusw...@intel.com>
Fixes: f6fb9ec02be1 ("usb: roles: Add Intel xHCI USB role switch driver")
Signed-off-by: Heikki Krogerus <heikki.kroge...@linux.intel.com>
Tested-by: Kuppuswamy Sathyanarayanan 
<sathyanarayanan.kuppusw...@linux.intel.com>

---
  drivers/usb/roles/intel-xhci-usb-role-switch.c | 14 +-
  1 file changed, 13 insertions(+), 1 deletion(-)

diff --git a/drivers/usb/roles/intel-xhci-usb-role-switch.c 
b/drivers/usb/roles/intel-xhci-usb-role-switch.c
index 6e922b50b674..1fb3dd0f1dfa 100644
--- a/drivers/usb/roles/intel-xhci-usb-role-switch.c
+++ b/drivers/usb/roles/intel-xhci-usb-role-switch.c
@@ -18,6 +18,7 @@
  #include 
  #include 
  #include 
+#include 
  #include 
  
  /* register definition */

@@ -56,6 +57,8 @@ static int intel_xhci_usb_set_role(struct device *dev, enum 
usb_role role)
return -EIO;
}
  
+	pm_runtime_get_sync(dev);

+
/* Set idpin value as requested */
val = readl(data->base + DUAL_ROLE_CFG0);
switch (role) {
@@ -84,13 +87,17 @@ static int intel_xhci_usb_set_role(struct device *dev, enum 
usb_role role)
/* Polling on CFG1 register to confirm mode switch.*/
do {
val = readl(data->base + DUAL_ROLE_CFG1);
-   if (!!(val & HOST_MODE) == (role == USB_ROLE_HOST))
+   if (!!(val & HOST_MODE) == (role == USB_ROLE_HOST)) {
+   pm_runtime_put(dev);
return 0;
+   }
  
  		/* Interval for polling is set to about 5 - 10 ms */

usleep_range(5000, 1);
} while (time_before(jiffies, timeout));
  
+	pm_runtime_put(dev);

+
dev_warn(dev, "Timeout waiting for role-switch\n");
return -ETIMEDOUT;
  }
@@ -101,7 +108,9 @@ static enum usb_role intel_xhci_usb_get_role(struct device 
*dev)
enum usb_role role;
u32 val;
  
+	pm_runtime_get_sync(dev);

val = readl(data->base + DUAL_ROLE_CFG0);
+   pm_runtime_put(dev);
  
  	if (!(val & SW_IDPIN))

role = USB_ROLE_HOST;
@@ -142,6 +151,9 @@ static int intel_xhci_usb_probe(struct platform_device 
*pdev)
if (IS_ERR(data->role_sw))
return PTR_ERR(data->role_sw);
  
+	pm_runtime_set_active(dev);

+   pm_runtime_enable(dev);
+
return 0;
  }
  


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[PATCH v2 1/1] usb: core: Add quirk for HP v222w 16GB Mini

[sathyanarayanan . kuppuswamy]

From: Kamil Lulko 

Add DELAY_INIT quirk to fix the following problem with HP
v222w 16GB Mini:

usb 1-3: unable to read config index 0 descriptor/start: -110
usb 1-3: can't read configurations, error -110
usb 1-3: can't set config #1, error -110

Signed-off-by: Kamil Lulko 
Signed-off-by: Kuppuswamy Sathyanarayanan 

---

Changes since v1:
 * Fixed indentation.

 drivers/usb/core/quirks.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/drivers/usb/core/quirks.c b/drivers/usb/core/quirks.c
index 920f48a..c55def2 100644
--- a/drivers/usb/core/quirks.c
+++ b/drivers/usb/core/quirks.c
@@ -186,6 +186,9 @@ static const struct usb_device_id usb_quirk_list[] = {
{ USB_DEVICE(0x03f0, 0x0701), .driver_info =
USB_QUIRK_STRING_FETCH_255 },
 
+   /* HP v222w 16GB Mini USB Drive */
+   { USB_DEVICE(0x03f0, 0x3f40), .driver_info = USB_QUIRK_DELAY_INIT },
+
/* Creative SB Audigy 2 NX */
{ USB_DEVICE(0x041e, 0x3020), .driver_info = USB_QUIRK_RESET_RESUME },
 
-- 
2.7.4

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Re: [PATCH v1 1/1] usb: core: Add quirk for HP v222w 16GB Mini

[sathyanarayanan kuppuswamy]

Hi Segei,


On 04/14/2018 01:35 AM, Sergei Shtylyov wrote:
Please indent with tabs (as above and below), not spaces. 

Thanks for the comments. I will fix it in v2.

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[PATCH v1 1/1] usb: hub: Don't wait for connect state at resume for powered-off ports

[sathyanarayanan . kuppuswamy]

From: Dominik Bozek 

wait_for_connected() wait till a port change status to
USB_PORT_STAT_CONNECTION, but this is not possible if
the port is unpowered. The loop will only exit at timeout.

Such case take place if an over-current incident happen
while system is in S3. Then during resume wait_for_connected()
will wait 2s, which may be noticeable by the user.

Signed-off-by: Dominik Bozek 
Signed-off-by: Kuppuswamy Sathyanarayanan 

---
 drivers/usb/core/hub.c | 4 
 1 file changed, 4 insertions(+)

diff --git a/drivers/usb/core/hub.c b/drivers/usb/core/hub.c
index c5c1f6c..bd2b136 100644
--- a/drivers/usb/core/hub.c
+++ b/drivers/usb/core/hub.c
@@ -3367,6 +3367,10 @@ static int wait_for_connected(struct usb_device *udev,
while (delay_ms < 2000) {
if (status || *portstatus & USB_PORT_STAT_CONNECTION)
break;
+   if (!port_is_power_on(hub, *portstatus)) {
+   status = -ENODEV;
+   break;
+   }
msleep(20);
delay_ms += 20;
status = hub_port_status(hub, *port1, portstatus, portchange);
-- 
2.7.4

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[PATCH v1 1/1] usb: core: Add quirk for HP v222w 16GB Mini

[sathyanarayanan . kuppuswamy]

From: Kamil Lulko 

Add DELAY_INIT quirk to fix the following problem with HP
v222w 16GB Mini:

usb 1-3: unable to read config index 0 descriptor/start: -110
usb 1-3: can't read configurations, error -110
usb 1-3: can't set config #1, error -110

Signed-off-by: Kamil Lulko 
Signed-off-by: Kuppuswamy Sathyanarayanan 

---
 drivers/usb/core/quirks.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/drivers/usb/core/quirks.c b/drivers/usb/core/quirks.c
index 54b019e..f2ef913 100644
--- a/drivers/usb/core/quirks.c
+++ b/drivers/usb/core/quirks.c
@@ -40,6 +40,9 @@ static const struct usb_device_id usb_quirk_list[] = {
{ USB_DEVICE(0x03f0, 0x0701), .driver_info =
USB_QUIRK_STRING_FETCH_255 },
 
+/* HP v222w 16GB Mini USB Drive */
+{ USB_DEVICE(0x03f0, 0x3f40), .driver_info = USB_QUIRK_DELAY_INIT },
+
/* Creative SB Audigy 2 NX */
{ USB_DEVICE(0x041e, 0x3020), .driver_info = USB_QUIRK_RESET_RESUME },
 
-- 
2.7.4

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Re: [PATCH v1 1/1] USB: serial: Add boundry check for read_urbs array access

[sathyanarayanan kuppuswamy]

On 03/08/2018 03:43 PM, Greg KH wrote:

On Thu, Mar 08, 2018 at 03:29:48PM -0800, sathyanarayanan kuppuswamy wrote:


On 03/08/2018 12:54 AM, Oliver Neukum wrote:

Am Mittwoch, den 07.03.2018, 13:41 -0800 schrieb sathyanarayanan
kuppuswamy   :

On 03/07/2018 12:58 PM, Greg KH wrote:

So I don't see why your check is needed, what other code path would ever
call this function in a way that the bounds check would be needed?

void usb_serial_generic_read_bulk_callback(struct urb *urb)

385 for (i = 0; i < ARRAY_SIZE(port->read_urbs); ++i) {
386 if (urb == port->read_urbs[i])
387 break;
388 }

In here, after this for loop is done (without any matching urb), i value
will be equal to ARRAY_SIZE(port->read_urbs). So there is a possibility
of usb_serial_generic_submit_read_urb() getting called with this invalid
index.

If this happens the function was called for a stray URB.
Your check comes to late. We have called set_bit with an invalid index
and other shit.
We definitely do not just want to return an error in that case.

In that case do you think we should use some WARN_ON() for invalid index in
usb_serial_generic_read_bulk_callback()?

No, again, how could that ever happen?

Don't add pointless error checking for things that are impossible to
ever hit :)

Thanks Greg.


thanks,

greg k-h
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Re: [PATCH v1 1/1] USB: serial: Add boundry check for read_urbs array access

[sathyanarayanan kuppuswamy]

On 03/08/2018 12:54 AM, Oliver Neukum wrote:

Am Mittwoch, den 07.03.2018, 13:41 -0800 schrieb sathyanarayanan
kuppuswamy   :

On 03/07/2018 12:58 PM, Greg KH wrote:

So I don't see why your check is needed, what other code path would ever
call this function in a way that the bounds check would be needed?

void usb_serial_generic_read_bulk_callback(struct urb *urb)

385 for (i = 0; i < ARRAY_SIZE(port->read_urbs); ++i) {
386 if (urb == port->read_urbs[i])
387 break;
388 }

In here, after this for loop is done (without any matching urb), i value
will be equal to ARRAY_SIZE(port->read_urbs). So there is a possibility
of usb_serial_generic_submit_read_urb() getting called with this invalid
index.

If this happens the function was called for a stray URB.
Your check comes to late. We have called set_bit with an invalid index
and other shit.
We definitely do not just want to return an error in that case.
In that case do you think we should use some WARN_ON() for invalid index 
in usb_serial_generic_read_bulk_callback()?


Regards
Oliver

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Re: [PATCH v1 1/1] USB: serial: Add boundry check for read_urbs array access

[sathyanarayanan kuppuswamy]

On 03/07/2018 12:58 PM, Greg KH wrote:

On Wed, Mar 07, 2018 at 12:23:56PM -0800, 
sathyanarayanan.kuppusw...@linux.intel.com wrote:

From: Kuppuswamy Sathyanarayanan <sathyanarayanan.kuppusw...@linux.intel.com>

In usb_serial_generic_submit_read_urb() function we are accessing the
port->read_urbs array without any boundry checks. This might lead to
kernel panic when index value goes above array length.

One posible call path for this issue is,

usb_serial_generic_read_bulk_callback()
{
  ...
  if (!port->throttled) {
usb_serial_generic_submit_read_urb(port, i, GFP_ATOMIC);
  ...
}

How does i ever get to be greater than the array size here in this
function?  It directly came from looking in that array in the first
place :)

So I don't see why your check is needed, what other code path would ever
call this function in a way that the bounds check would be needed?

void usb_serial_generic_read_bulk_callback(struct urb *urb)

385 for (i = 0; i < ARRAY_SIZE(port->read_urbs); ++i) {
386 if (urb == port->read_urbs[i])
387 break;
388 }

In here, after this for loop is done (without any matching urb), i value 
will be equal to ARRAY_SIZE(port->read_urbs). So there is a possibility 
of usb_serial_generic_submit_read_urb() getting called with this invalid 
index.




thanks,

greg k-h
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[PATCH v1 1/1] USB: serial: Add boundry check for read_urbs array access

[sathyanarayanan . kuppuswamy]

From: Kuppuswamy Sathyanarayanan 

In usb_serial_generic_submit_read_urb() function we are accessing the
port->read_urbs array without any boundry checks. This might lead to
kernel panic when index value goes above array length.

One posible call path for this issue is,

usb_serial_generic_read_bulk_callback()
{
 ...
 if (!port->throttled) {
usb_serial_generic_submit_read_urb(port, i, GFP_ATOMIC);
 ...
}

This patch fixes this issue.

Signed-off-by: Kuppuswamy Sathyanarayanan 

---
 drivers/usb/serial/generic.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/drivers/usb/serial/generic.c b/drivers/usb/serial/generic.c
index 2274d96..72ebdde 100644
--- a/drivers/usb/serial/generic.c
+++ b/drivers/usb/serial/generic.c
@@ -306,6 +306,9 @@ static int usb_serial_generic_submit_read_urb(struct 
usb_serial_port *port,
 {
int res;
 
+   if (index >= ARRAY_SIZE(port->read_urbs))
+   return -EINVAL;
+
if (!test_and_clear_bit(index, >read_urbs_free))
return 0;
 
-- 
2.7.4

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[PATCH v2 1/1] usb: cdc_acm: prevent race at write to acm while system resumes

[sathyanarayanan . kuppuswamy]

From: Dominik Bozek 

ACM driver may accept data to transmit while system is not fully
resumed. In this case ACM driver buffers data and prepare URBs
on usb anchor list.
There is a little chance that two tasks put a char and initiate
acm_tty_flush_chars(). In such a case, driver will put one URB
twice on usb anchor list.
This patch also reset length of data before resue of a buffer.
This not only prevent sending rubbish, but also lower risc of race.

Without this patch we hit following kernel panic in one of our
stabilty/stress tests.

[   46.884442] *list_add double add*: new=9b2ab7289330, 
prev=9b2ab7289330, next=9b2ab81e28e0.
[   46.884476] Modules linked in: hci_uart btbcm bluetooth rfkill_gpio 
igb_avb(O) cfg80211 snd_soc_sst_bxt_tdf8532 snd_soc_skl snd_soc_skl_ipc 
snd_soc_sst_ipc snd_soc_sst_dsp snd_soc_sst_acpi snd_soc_sst_match 
snd_hda_ext_core snd_hda_core trusty_timer trusty_wall trusty_log trusty_virtio 
trusty_ipc trusty_mem trusty_irq trusty virtio_ring virtio intel_ipu4_mmu_bxtB0 
lib2600_mod_bxtB0 intel_ipu4_isys_mod_bxtB0 lib2600psys_mod_bxtB0 
intel_ipu4_psys_mod_bxtB0 intel_ipu4_mod_bxtB0 intel_ipu4_wrapper_bxtB0 
intel_ipu4_acpi videobuf2_dma_contig as3638 dw9714 lm3643 crlmodule smiapp 
smiapp_pll
[   46.884480] CPU: 1 PID: 33 Comm: kworker/u8:1 Tainted: G U  W  O
4.9.56-quilt-2e5dc0ac-g618ed69ced6e-dirty #4
[   46.884489] Workqueue: events_unbound flush_to_ldisc
[   46.884494]  b98ac012bb08 ad3e82e5 b98ac012bb58 

[   46.884497]  b98ac012bb48 ad0a23d1 0024ad6374dd 
9b2ab7289330
[   46.884500]  9b2ab81e28e0 9b2ab7289330 0002 

[   46.884501] Call Trace:
[   46.884507]  [] dump_stack+0x67/0x92
[   46.884511]  [] __warn+0xd1/0xf0
[   46.884513]  [] warn_slowpath_fmt+0x5f/0x80
[   46.884516]  [] __list_add+0xb3/0xc0
[   46.884521]  [] *usb_anchor_urb*+0x4c/0xa0
[   46.884524]  [] *acm_tty_flush_chars*+0x8f/0xb0
[   46.884527]  [] *acm_tty_put_char*+0x41/0x100
[   46.884530]  [] tty_put_char+0x24/0x40
[   46.884533]  [] do_output_char+0xa5/0x200
[   46.884535]  [] __process_echoes+0x148/0x290
[   46.884538]  [] n_tty_receive_buf_common+0x57c/0xb00
[   46.884541]  [] n_tty_receive_buf2+0x14/0x20
[   46.884543]  [] tty_ldisc_receive_buf+0x22/0x50
[   46.884545]  [] flush_to_ldisc+0xc5/0xe0
[   46.884549]  [] process_one_work+0x148/0x440
[   46.884551]  [] worker_thread+0x69/0x4a0
[   46.884554]  [] ? max_active_store+0x80/0x80
[   46.884556]  [] kthread+0x110/0x130
[   46.884559]  [] ? kthread_park+0x60/0x60
[   46.884563]  [] ret_from_fork+0x27/0x40
[   46.884566] ---[ end trace 3bd599058b8a9eb3 ]---

Signed-off-by: Dominik Bozek 
Signed-off-by: Kuppuswamy Sathyanarayanan 

Acked-by: Oliver Neukum 
---
 drivers/usb/class/cdc-acm.c | 9 ++---
 1 file changed, 6 insertions(+), 3 deletions(-)

diff --git a/drivers/usb/class/cdc-acm.c b/drivers/usb/class/cdc-acm.c
index 06b3b54..7b366a6 100644
--- a/drivers/usb/class/cdc-acm.c
+++ b/drivers/usb/class/cdc-acm.c
@@ -174,6 +174,7 @@ static int acm_wb_alloc(struct acm *acm)
wb = >wb[wbn];
if (!wb->use) {
wb->use = 1;
+   wb->len = 0;
return wbn;
}
wbn = (wbn + 1) % ACM_NW;
@@ -805,16 +806,18 @@ static int acm_tty_write(struct tty_struct *tty,
 static void acm_tty_flush_chars(struct tty_struct *tty)
 {
struct acm *acm = tty->driver_data;
-   struct acm_wb *cur = acm->putbuffer;
+   struct acm_wb *cur;
int err;
unsigned long flags;
 
+   spin_lock_irqsave(>write_lock, flags);
+
+   cur = acm->putbuffer;
if (!cur) /* nothing to do */
-   return;
+   goto out;
 
acm->putbuffer = NULL;
err = usb_autopm_get_interface_async(acm->control);
-   spin_lock_irqsave(>write_lock, flags);
if (err < 0) {
cur->use = 0;
acm->putbuffer = cur;
-- 
2.7.4

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Re: [PATCH v1 1/1] usb: cdc_acm: prevent race at write to acm while system resumes

[sathyanarayanan kuppuswamy]

Hi Greg,


On 02/15/2018 09:37 AM, Greg KH wrote:

Why hasn't the author of this patch signed off on it?
This patch has been initially submitted with Gerrit-ID and some custom 
tags. During the scrubbing process of this unrelated details, I think 
the automated script accidentally deleted the signed-off tag. Let me 
confirm it with author and get back to you. Mostly I will submit a v2 
with proper sign-off info.


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Re: [PATCH] usb: core: message: remember to reset 'ret' to 0 when necessary

[sathyanarayanan kuppuswamy]

Works in APL platform.

Tested-by: Kuppuswamy Sathyanarayanan 
<sathyanarayanan.kupusw...@linux.intel.com>



On 11/09/2017 02:59 AM, Felipe Balbi wrote:

usb_control_msg() will return the amount of bytes transferred, if that
amount matches what we wanted to transfer, we need to reset 'ret' to 0
from usb_get_status().

Fixes: 2e43f0fe379c ("usb: core: add a 'type' parameter to usb_get_status()")
Reported-by: Tony Lindgren <t...@atomide.com>
Signed-off-by: Felipe Balbi <felipe.ba...@linux.intel.com>
---
  drivers/usb/core/message.c | 2 ++
  1 file changed, 2 insertions(+)

diff --git a/drivers/usb/core/message.c b/drivers/usb/core/message.c
index 0cdc463c9509..c15fbf76f8f7 100644
--- a/drivers/usb/core/message.c
+++ b/drivers/usb/core/message.c
@@ -975,6 +975,7 @@ int usb_get_status(struct usb_device *dev, int recip, int 
type, int target,
}
  
  		*(u32 *) data = le32_to_cpu(*(__le32 *) status);

+   ret = 0;
break;
case 2:
if (type != USB_STATUS_TYPE_STANDARD) {
@@ -983,6 +984,7 @@ int usb_get_status(struct usb_device *dev, int recip, int 
type, int target,
}
  
  		*(u16 *) data = le16_to_cpu(*(__le16 *) status);

+   ret = 0;
break;
default:
    ret = -EIO;


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[PATCH v6 6/6] platform/x86: intel_bxtwc_tmu: Remove first level IRQ unmask

[sathyanarayanan . kuppuswamy]

From: Kuppuswamy Sathyanarayanan 

Currently in WCOVE PMIC MFD driver, all second level IRQ chips
are chained to the respective first level IRQs. So there is no
need for explicitly unmasking the first level IRQ in this
driver. This patches removes this level 1 IRQ unmask support.

Signed-off-by: Kuppuswamy Sathyanarayanan 

Reviewed-by: Darren Hart (VMware) 
Reviewed-by: Andy Shevchenko 
---
 drivers/platform/x86/intel_bxtwc_tmu.c | 4 
 1 file changed, 4 deletions(-)

Changes since v1:
 * None

Changes since v2:
 * Rebased on top of latest release.

Changes since v3:
 * None

Changes since v4:
 * Changed commit subject from "platform: x86:" "to platform/x86:"

Changes since v5:
 * Changed irq->IRQ, mfd->MFD.

diff --git a/drivers/platform/x86/intel_bxtwc_tmu.c 
b/drivers/platform/x86/intel_bxtwc_tmu.c
index e202abd..ea865d4 100644
--- a/drivers/platform/x86/intel_bxtwc_tmu.c
+++ b/drivers/platform/x86/intel_bxtwc_tmu.c
@@ -92,10 +92,6 @@ static int bxt_wcove_tmu_probe(struct platform_device *pdev)
}
wctmu->irq = virq;
 
-   /* Enable TMU interrupts */
-   regmap_update_bits(wctmu->regmap, BXTWC_MIRQLVL1,
- BXTWC_MIRQLVL1_MTMU, 0);
-
/* Unmask TMU second level Wake & System alarm */
regmap_update_bits(wctmu->regmap, BXTWC_MTMUIRQ_REG,
  BXTWC_TMU_ALRM_MASK, 0);
-- 
2.7.4

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[PATCH v6 1/6] mfd: intel_soc_pmic_bxtwc: Fix TMU interrupt index

[sathyanarayanan . kuppuswamy]

From: Kuppuswamy Sathyanarayanan 

TMU interrupts are registered as a separate interrupt chip, and
hence it should start its interrupt index(BXTWC_TMU_IRQ) number
from 0. But currently, BXTWC_TMU_IRQ is defined as part of enum
bxtwc_irqs_level2 and its index value is 11. Since this index
value is used when calculating .num_irqs of regmap_irq_chip_tmu,
it incorrectly reports number of IRQs as 12 instead of actual
value of 1.

This patch fixes this issue by creating new enum of tmu IRQs and
resetting its starting index to 0.

Signed-off-by: Kuppuswamy Sathyanarayanan 

Acked-for-MFD-by: Lee Jones 
---
 drivers/mfd/intel_soc_pmic_bxtwc.c | 5 -
 1 file changed, 4 insertions(+), 1 deletion(-)

Changes since v1: 
 * Removed code from commit message.

Changes since v2: 
 * Rebased on top of latest release.

Changes sinve v3:
 * Rebased on top of latest release.

Changes sinve v5:
 * Changed irq to IRQ.

diff --git a/drivers/mfd/intel_soc_pmic_bxtwc.c 
b/drivers/mfd/intel_soc_pmic_bxtwc.c
index 8c3cbf6..7cbaf1e 100644
--- a/drivers/mfd/intel_soc_pmic_bxtwc.c
+++ b/drivers/mfd/intel_soc_pmic_bxtwc.c
@@ -95,7 +95,10 @@ enum bxtwc_irqs_level2 {
BXTWC_GPIO0_IRQ,
BXTWC_GPIO1_IRQ,
BXTWC_CRIT_IRQ,
-   BXTWC_TMU_IRQ,
+};
+
+enum bxtwc_irqs_tmu {
+   BXTWC_TMU_IRQ = 0,
 };
 
 static const struct regmap_irq bxtwc_regmap_irqs[] = {
-- 
2.7.4

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[PATCH v6 3/6] mfd: intel_soc_pmic_bxtwc: Remove second level IRQ for gpio device

[sathyanarayanan . kuppuswamy]

From: Kuppuswamy Sathyanarayanan 

Currently all PMIC GPIO domain IRQs are consumed by the same
device(bxt_wcove_gpio), so there is no need to export them as
separate interrupts. We can just export only the first level
GPIO IRQ(BXTWC_GPIO_LVL1_IRQ) as an IRQ resource and let the
GPIO device driver(bxt_wcove_gpio) handle the GPIO sub domain
IRQs based on status value of GPIO level2 interrupt status
register. Also, just using only the first level IRQ will eliminate
the bug involved in requesting only the second level IRQ and not
explicitly enable the first level IRQ. For more info on this
issue please read the details at,

https://lkml.org/lkml/2017/2/27/148

This patch also makes relevant change in Whiskey cove GPIO driver to
use only first level PMIC GPIO IRQ.

Signed-off-by: Kuppuswamy Sathyanarayanan 

Acked-for-MFD-by: Lee Jones 
Acked-by: Linus Walleij 
---
 drivers/gpio/gpio-wcove.c  | 14 +-
 drivers/mfd/intel_soc_pmic_bxtwc.c |  7 +--
 2 files changed, 14 insertions(+), 7 deletions(-)

Changes since v1:
 * None

Changes since v2: 
 * Rebased on top of latest release.

Changes since v3:
 * None

Changes since v5:
 * Squashed gpio driver patch.
 * Changes irq -> IRQ.

diff --git a/drivers/gpio/gpio-wcove.c b/drivers/gpio/gpio-wcove.c
index 7b1bc20..bba7704 100644
--- a/drivers/gpio/gpio-wcove.c
+++ b/drivers/gpio/gpio-wcove.c
@@ -401,7 +401,7 @@ static int wcove_gpio_probe(struct platform_device *pdev)
if (!wg)
return -ENOMEM;
 
-   wg->regmap_irq_chip = pmic->irq_chip_data_level2;
+   wg->regmap_irq_chip = pmic->irq_chip_data;
 
platform_set_drvdata(pdev, wg);
 
@@ -449,6 +449,18 @@ static int wcove_gpio_probe(struct platform_device *pdev)
 
gpiochip_set_nested_irqchip(>chip, _irqchip, virq);
 
+   /* Enable GPIO0 interrupts */
+   ret = regmap_update_bits(wg->regmap, IRQ_MASK_BASE, GPIO_IRQ0_MASK,
+0x00);
+   if (ret)
+   return ret;
+
+   /* Enable GPIO1 interrupts */
+   ret = regmap_update_bits(wg->regmap, IRQ_MASK_BASE + 1, GPIO_IRQ1_MASK,
+0x00);
+   if (ret)
+   return ret;
+
return 0;
 }
 
diff --git a/drivers/mfd/intel_soc_pmic_bxtwc.c 
b/drivers/mfd/intel_soc_pmic_bxtwc.c
index 7c1ed27..af11c43 100644
--- a/drivers/mfd/intel_soc_pmic_bxtwc.c
+++ b/drivers/mfd/intel_soc_pmic_bxtwc.c
@@ -89,8 +89,6 @@ enum bxtwc_irqs_level2 {
BXTWC_USBC_IRQ,
BXTWC_CHGR0_IRQ,
BXTWC_CHGR1_IRQ,
-   BXTWC_GPIO0_IRQ,
-   BXTWC_GPIO1_IRQ,
BXTWC_CRIT_IRQ,
 };
 
@@ -116,8 +114,6 @@ static const struct regmap_irq bxtwc_regmap_irqs_level2[] = 
{
REGMAP_IRQ_REG(BXTWC_USBC_IRQ, 2, BIT(5)),
REGMAP_IRQ_REG(BXTWC_CHGR0_IRQ, 2, 0x1f),
REGMAP_IRQ_REG(BXTWC_CHGR1_IRQ, 3, 0x1f),
-   REGMAP_IRQ_REG(BXTWC_GPIO0_IRQ, 4, 0xff),
-   REGMAP_IRQ_REG(BXTWC_GPIO1_IRQ, 5, 0x3f),
REGMAP_IRQ_REG(BXTWC_CRIT_IRQ, 6, 0x03),
 };
 
@@ -153,8 +149,7 @@ static struct regmap_irq_chip bxtwc_regmap_irq_chip_tmu = {
 };
 
 static struct resource gpio_resources[] = {
-   DEFINE_RES_IRQ_NAMED(BXTWC_GPIO0_IRQ, "GPIO0"),
-   DEFINE_RES_IRQ_NAMED(BXTWC_GPIO1_IRQ, "GPIO1"),
+   DEFINE_RES_IRQ_NAMED(BXTWC_GPIO_LVL1_IRQ, "GPIO"),
 };
 
 static struct resource adc_resources[] = {
-- 
2.7.4

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[PATCH v6 2/6] mfd: intel_soc_pmic_bxtwc: Remove thermal second level IRQs

[sathyanarayanan . kuppuswamy]

From: Kuppuswamy Sathyanarayanan 

Since all second level thermal IRQs are consumed by the same
device(bxt_wcove_thermal), there is no need to expose them as separate
interrupts. We can just export only the first level IRQs for thermal and
let the device(bxt_wcove_thermal) driver handle the second level IRQs
based on thermal interrupt status register. Also, just using only the
first level IRQ will eliminate the bug involved in requesting only the
second level IRQ and not explicitly enable the first level IRQ. For
more info on this issue please read the details at,

https://lkml.org/lkml/2017/2/27/148

This patch also makes relevant change in bxt_wcove_thermal driver to use
only first level PMIC thermal IRQ.

Signed-off-by: Kuppuswamy Sathyanarayanan 

Acked-for-MFD-by: Lee Jones 
Acked-by: Zhang Rui 
---
 drivers/mfd/intel_soc_pmic_bxtwc.c   | 32 
 drivers/thermal/intel_bxt_pmic_thermal.c |  2 +-
 2 files changed, 13 insertions(+), 21 deletions(-)

Changes since v1:
 * None

Changes since v2: 
 * Rebased on top of latest release.

Changes since v3:
 * Rebased on top of latest release.

Changes since v5:
 * Squashed intel_bxt_pmic_thermal driver patch.
 * Changed irq -> IRQ


diff --git a/drivers/mfd/intel_soc_pmic_bxtwc.c 
b/drivers/mfd/intel_soc_pmic_bxtwc.c
index 7cbaf1e..7c1ed27 100644
--- a/drivers/mfd/intel_soc_pmic_bxtwc.c
+++ b/drivers/mfd/intel_soc_pmic_bxtwc.c
@@ -84,10 +84,7 @@ enum bxtwc_irqs {
 
 enum bxtwc_irqs_level2 {
/* Level 2 */
-   BXTWC_THRM0_IRQ = 0,
-   BXTWC_THRM1_IRQ,
-   BXTWC_THRM2_IRQ,
-   BXTWC_BCU_IRQ,
+   BXTWC_BCU_IRQ = 0,
BXTWC_ADC_IRQ,
BXTWC_USBC_IRQ,
BXTWC_CHGR0_IRQ,
@@ -114,17 +111,14 @@ static const struct regmap_irq bxtwc_regmap_irqs[] = {
 };
 
 static const struct regmap_irq bxtwc_regmap_irqs_level2[] = {
-   REGMAP_IRQ_REG(BXTWC_THRM0_IRQ, 0, 0xff),
-   REGMAP_IRQ_REG(BXTWC_THRM1_IRQ, 1, 0xbf),
-   REGMAP_IRQ_REG(BXTWC_THRM2_IRQ, 2, 0xff),
-   REGMAP_IRQ_REG(BXTWC_BCU_IRQ, 3, 0x1f),
-   REGMAP_IRQ_REG(BXTWC_ADC_IRQ, 4, 0xff),
-   REGMAP_IRQ_REG(BXTWC_USBC_IRQ, 5, BIT(5)),
-   REGMAP_IRQ_REG(BXTWC_CHGR0_IRQ, 5, 0x1f),
-   REGMAP_IRQ_REG(BXTWC_CHGR1_IRQ, 6, 0x1f),
-   REGMAP_IRQ_REG(BXTWC_GPIO0_IRQ, 7, 0xff),
-   REGMAP_IRQ_REG(BXTWC_GPIO1_IRQ, 8, 0x3f),
-   REGMAP_IRQ_REG(BXTWC_CRIT_IRQ, 9, 0x03),
+   REGMAP_IRQ_REG(BXTWC_BCU_IRQ, 0, 0x1f),
+   REGMAP_IRQ_REG(BXTWC_ADC_IRQ, 1, 0xff),
+   REGMAP_IRQ_REG(BXTWC_USBC_IRQ, 2, BIT(5)),
+   REGMAP_IRQ_REG(BXTWC_CHGR0_IRQ, 2, 0x1f),
+   REGMAP_IRQ_REG(BXTWC_CHGR1_IRQ, 3, 0x1f),
+   REGMAP_IRQ_REG(BXTWC_GPIO0_IRQ, 4, 0xff),
+   REGMAP_IRQ_REG(BXTWC_GPIO1_IRQ, 5, 0x3f),
+   REGMAP_IRQ_REG(BXTWC_CRIT_IRQ, 6, 0x03),
 };
 
 static const struct regmap_irq bxtwc_regmap_irqs_tmu[] = {
@@ -142,8 +136,8 @@ static struct regmap_irq_chip bxtwc_regmap_irq_chip = {
 
 static struct regmap_irq_chip bxtwc_regmap_irq_chip_level2 = {
.name = "bxtwc_irq_chip_level2",
-   .status_base = BXTWC_THRM0IRQ,
-   .mask_base = BXTWC_MTHRM0IRQ,
+   .status_base = BXTWC_BCUIRQ,
+   .mask_base = BXTWC_MBCUIRQ,
.irqs = bxtwc_regmap_irqs_level2,
.num_irqs = ARRAY_SIZE(bxtwc_regmap_irqs_level2),
.num_regs = 10,
@@ -177,9 +171,7 @@ static struct resource charger_resources[] = {
 };
 
 static struct resource thermal_resources[] = {
-   DEFINE_RES_IRQ(BXTWC_THRM0_IRQ),
-   DEFINE_RES_IRQ(BXTWC_THRM1_IRQ),
-   DEFINE_RES_IRQ(BXTWC_THRM2_IRQ),
+   DEFINE_RES_IRQ(BXTWC_THRM_LVL1_IRQ),
 };
 
 static struct resource bcu_resources[] = {
diff --git a/drivers/thermal/intel_bxt_pmic_thermal.c 
b/drivers/thermal/intel_bxt_pmic_thermal.c
index 0f19a39..ef6b322 100644
--- a/drivers/thermal/intel_bxt_pmic_thermal.c
+++ b/drivers/thermal/intel_bxt_pmic_thermal.c
@@ -241,7 +241,7 @@ static int pmic_thermal_probe(struct platform_device *pdev)
}
 
regmap = pmic->regmap;
-   regmap_irq_chip = pmic->irq_chip_data_level2;
+   regmap_irq_chip = pmic->irq_chip_data;
 
pmic_irq_count = 0;
while ((irq = platform_get_irq(pdev, pmic_irq_count)) != -ENXIO) {
-- 
2.7.4

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[PATCH v6 4/6] mfd: intel_soc_pmic_bxtwc: Utilize devm_* functions in driver probe

[sathyanarayanan . kuppuswamy]

From: Kuppuswamy Sathyanarayanan 

Cleanup the resource allocation/free code in probe function by using
devm_* calls.

Signed-off-by: Kuppuswamy Sathyanarayanan 

Acked-for-MFD-by: Lee Jones 
Reviewed-by: Andy Shevchenko 
---
 drivers/mfd/intel_soc_pmic_bxtwc.c | 54 +-
 1 file changed, 18 insertions(+), 36 deletions(-)

Changes since v1:
 * None

Changes since v2:
 * Rebased on top of latest release.

Changes since v3:
 * None

Changes since v5:
 * None

diff --git a/drivers/mfd/intel_soc_pmic_bxtwc.c 
b/drivers/mfd/intel_soc_pmic_bxtwc.c
index af11c43..feeda6e 100644
--- a/drivers/mfd/intel_soc_pmic_bxtwc.c
+++ b/drivers/mfd/intel_soc_pmic_bxtwc.c
@@ -399,45 +399,44 @@ static int bxtwc_probe(struct platform_device *pdev)
return ret;
}
 
-   ret = regmap_add_irq_chip(pmic->regmap, pmic->irq,
- IRQF_ONESHOT | IRQF_SHARED,
- 0, _regmap_irq_chip,
- >irq_chip_data);
+   ret = devm_regmap_add_irq_chip(>dev, pmic->regmap, pmic->irq,
+  IRQF_ONESHOT | IRQF_SHARED,
+  0, _regmap_irq_chip,
+  >irq_chip_data);
if (ret) {
dev_err(>dev, "Failed to add IRQ chip\n");
return ret;
}
 
-   ret = regmap_add_irq_chip(pmic->regmap, pmic->irq,
- IRQF_ONESHOT | IRQF_SHARED,
- 0, _regmap_irq_chip_level2,
- >irq_chip_data_level2);
+   ret = devm_regmap_add_irq_chip(>dev, pmic->regmap, pmic->irq,
+  IRQF_ONESHOT | IRQF_SHARED,
+  0, _regmap_irq_chip_level2,
+  >irq_chip_data_level2);
if (ret) {
dev_err(>dev, "Failed to add secondary IRQ chip\n");
-   goto err_irq_chip_level2;
+   return ret;
}
 
-   ret = regmap_add_irq_chip(pmic->regmap, pmic->irq,
- IRQF_ONESHOT | IRQF_SHARED,
- 0, _regmap_irq_chip_tmu,
- >irq_chip_data_tmu);
+   ret = devm_regmap_add_irq_chip(>dev, pmic->regmap, pmic->irq,
+  IRQF_ONESHOT | IRQF_SHARED,
+  0, _regmap_irq_chip_tmu,
+  >irq_chip_data_tmu);
if (ret) {
dev_err(>dev, "Failed to add TMU IRQ chip\n");
-   goto err_irq_chip_tmu;
+   return ret;
}
 
-   ret = mfd_add_devices(>dev, PLATFORM_DEVID_NONE, bxt_wc_dev,
- ARRAY_SIZE(bxt_wc_dev), NULL, 0,
- NULL);
+   ret = devm_mfd_add_devices(>dev, PLATFORM_DEVID_NONE, bxt_wc_dev,
+  ARRAY_SIZE(bxt_wc_dev), NULL, 0, NULL);
if (ret) {
dev_err(>dev, "Failed to add devices\n");
-   goto err_mfd;
+   return ret;
}
 
ret = sysfs_create_group(>dev.kobj, _group);
if (ret) {
dev_err(>dev, "Failed to create sysfs group %d\n", ret);
-   goto err_sysfs;
+   return ret;
}
 
/*
@@ -451,28 +450,11 @@ static int bxtwc_probe(struct platform_device *pdev)
BXTWC_MIRQLVL1_MCHGR, 0);
 
return 0;
-
-err_sysfs:
-   mfd_remove_devices(>dev);
-err_mfd:
-   regmap_del_irq_chip(pmic->irq, pmic->irq_chip_data_tmu);
-err_irq_chip_tmu:
-   regmap_del_irq_chip(pmic->irq, pmic->irq_chip_data_level2);
-err_irq_chip_level2:
-   regmap_del_irq_chip(pmic->irq, pmic->irq_chip_data);
-
-   return ret;
 }
 
 static int bxtwc_remove(struct platform_device *pdev)
 {
-   struct intel_soc_pmic *pmic = dev_get_drvdata(>dev);
-
sysfs_remove_group(>dev.kobj, _group);
-   mfd_remove_devices(>dev);
-   regmap_del_irq_chip(pmic->irq, pmic->irq_chip_data);
-   regmap_del_irq_chip(pmic->irq, pmic->irq_chip_data_level2);
-   regmap_del_irq_chip(pmic->irq, pmic->irq_chip_data_tmu);
 
return 0;
 }
-- 
2.7.4

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[PATCH v6 0/6] mfd: intel_soc_pmic_bxtwc: Add chained IRQ support

[sathyanarayanan . kuppuswamy]

From: Kuppuswamy Sathyanarayanan 

Following patch set adds chained IRQ support to WCOVE PMIC driver.

Changes since v3:
 * Added fix for typec wcove driver.

Changes since v4:
 * Squashed following two commits, to keep the patch set bisectable.
   usb: typec: typec_wcove: Use charger irq chip to get usbc virq
   mfd: intel_soc_pmic_bxtwc: use chained irqs for second level irq chips

Changes since v5:
* Changed irq->IRQ, pmic->PMIC in all commit messages.
* Squashed following two thermal driver related commits.
  mfd: intel_soc_pmic_bxtwc: Remove thermal second level irqs
  thermal: intel_bxt_pmic_thermal: Use first level PMIC thermal irq
* Squashed following two GPIO driver related commits.
  mfd: intel_soc_pmic_bxtwc: Remove second level irq for gpio device
  gpio: gpio-wcove: Use first level PMIC GPIO irq

Kuppuswamy Sathyanarayanan (6):
  mfd: intel_soc_pmic_bxtwc: Fix TMU interrupt index
  mfd: intel_soc_pmic_bxtwc: Remove thermal second level IRQs
  mfd: intel_soc_pmic_bxtwc: Remove second level IRQ for gpio device
  mfd: intel_soc_pmic_bxtwc: Utilize devm_* functions in driver probe
  mfd: intel_soc_pmic_bxtwc: Use chained IRQs for second level IRQ chips
  platform/x86: intel_bxtwc_tmu: Remove first level IRQ unmask

 drivers/gpio/gpio-wcove.c|  14 +-
 drivers/mfd/intel_soc_pmic_bxtwc.c   | 232 +--
 drivers/platform/x86/intel_bxtwc_tmu.c   |   4 -
 drivers/thermal/intel_bxt_pmic_thermal.c |   2 +-
 drivers/usb/typec/typec_wcove.c  |   2 +-
 include/linux/mfd/intel_soc_pmic.h   |   5 +-
 6 files changed, 175 insertions(+), 84 deletions(-)

-- 
2.7.4

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[PATCH v6 5/6] mfd: intel_soc_pmic_bxtwc: Use chained IRQs for second level IRQ chips

[sathyanarayanan . kuppuswamy]

From: Kuppuswamy Sathyanarayanan 

Whishkey cove PMIC has support to mask/unmask interrupts at two levels.
At first level we can mask/unmask interrupt domains like TMU, GPIO, ADC,
CHGR, BCU THERMAL and PWRBTN and at second level, it provides facility
to mask/unmask individual interrupts belong each of this domain. For
example, in case of TMU, at first level we have TMU interrupt domain,
and at second level we have two interrupts, wake alarm, system alarm that
belong to the TMU interrupt domain.

Currently, in this driver all first level IRQs are registered as part of
IRQ chip(bxtwc_regmap_irq_chip). By default, after you register the IRQ
chip from your driver, all IRQs in that chip will masked and can only be
enabled if that IRQ is requested using request_irq() call. This is the
default Linux IRQ behavior model. And whenever a dependent device that
belongs to PMIC requests only the second level IRQ and not explicitly
unmask the first level IRQ, then in essence the second level IRQ will
still be disabled. For example, if TMU device driver request wake_alarm
IRQ and not explicitly unmask TMU level 1 IRQ then according to the default
Linux IRQ model,  wake_alarm IRQ will still be disabled. So the proper
solution to fix this issue is to use the chained IRQ chip concept. We
should chain all the second level chip IRQs to the corresponding first
level IRQ. To do this, we need to create separate IRQ chips for every
group of second level IRQs.

In case of TMU, when adding second level IRQ chip, instead of using PMIC
IRQ we should use the corresponding first level IRQ. So the following
code will change from

ret = regmap_add_irq_chip(pmic->regmap, pmic->irq, ...)

to,

virq = regmap_irq_get_virq(>irq_chip_data, BXTWC_TMU_LVL1_IRQ);

ret = regmap_add_irq_chip(pmic->regmap, virq, ...)

In case of Whiskey Cove Type-C driver, Since USBC IRQ is moved under
charger level2 IRQ chip. We should use charger IRQ chip(irq_chip_data_chgr)
to get the USBC virtual IRQ number.

Signed-off-by: Kuppuswamy Sathyanarayanan 

Acked-for-MFD-by: Lee Jones 
---
 drivers/mfd/intel_soc_pmic_bxtwc.c | 168 ++---
 drivers/usb/typec/typec_wcove.c|   2 +-
 include/linux/mfd/intel_soc_pmic.h |   5 +-
 3 files changed, 143 insertions(+), 32 deletions(-)

Changes since v1:
 * Rebased on top of dev_* cleanup patch.
 * Fixed style & grammer issues reported by Lee Jones

Changes since v2:
 * Rebased on top of latest release.

Changes since v3:
 * None

Changes since v4:
 * Merged typec driver fix to this patch to prevent branch bisect issue.

Changes since v5:
 * Changed irq->IRQ and pmic -> PMIC.
 * Rearranged tmu related changes to make the patch more readable.
 * Modfied the virq request failure message to include chip name and pirq.

diff --git a/drivers/mfd/intel_soc_pmic_bxtwc.c 
b/drivers/mfd/intel_soc_pmic_bxtwc.c
index feeda6e..15bc052 100644
--- a/drivers/mfd/intel_soc_pmic_bxtwc.c
+++ b/drivers/mfd/intel_soc_pmic_bxtwc.c
@@ -82,20 +82,28 @@ enum bxtwc_irqs {
BXTWC_PWRBTN_IRQ,
 };
 
-enum bxtwc_irqs_level2 {
-   /* Level 2 */
+enum bxtwc_irqs_bcu {
BXTWC_BCU_IRQ = 0,
-   BXTWC_ADC_IRQ,
-   BXTWC_USBC_IRQ,
+};
+
+enum bxtwc_irqs_adc {
+   BXTWC_ADC_IRQ = 0,
+};
+
+enum bxtwc_irqs_chgr {
+   BXTWC_USBC_IRQ = 0,
BXTWC_CHGR0_IRQ,
BXTWC_CHGR1_IRQ,
-   BXTWC_CRIT_IRQ,
 };
 
 enum bxtwc_irqs_tmu {
BXTWC_TMU_IRQ = 0,
 };
 
+enum bxtwc_irqs_crit {
+   BXTWC_CRIT_IRQ = 0,
+};
+
 static const struct regmap_irq bxtwc_regmap_irqs[] = {
REGMAP_IRQ_REG(BXTWC_PWRBTN_LVL1_IRQ, 0, BIT(0)),
REGMAP_IRQ_REG(BXTWC_TMU_LVL1_IRQ, 0, BIT(1)),
@@ -108,19 +116,28 @@ static const struct regmap_irq bxtwc_regmap_irqs[] = {
REGMAP_IRQ_REG(BXTWC_PWRBTN_IRQ, 1, 0x03),
 };
 
-static const struct regmap_irq bxtwc_regmap_irqs_level2[] = {
+static const struct regmap_irq bxtwc_regmap_irqs_bcu[] = {
REGMAP_IRQ_REG(BXTWC_BCU_IRQ, 0, 0x1f),
-   REGMAP_IRQ_REG(BXTWC_ADC_IRQ, 1, 0xff),
-   REGMAP_IRQ_REG(BXTWC_USBC_IRQ, 2, BIT(5)),
-   REGMAP_IRQ_REG(BXTWC_CHGR0_IRQ, 2, 0x1f),
-   REGMAP_IRQ_REG(BXTWC_CHGR1_IRQ, 3, 0x1f),
-   REGMAP_IRQ_REG(BXTWC_CRIT_IRQ, 6, 0x03),
+};
+
+static const struct regmap_irq bxtwc_regmap_irqs_adc[] = {
+   REGMAP_IRQ_REG(BXTWC_ADC_IRQ, 0, 0xff),
+};
+
+static const struct regmap_irq bxtwc_regmap_irqs_chgr[] = {
+   REGMAP_IRQ_REG(BXTWC_USBC_IRQ, 0, BIT(5)),
+   REGMAP_IRQ_REG(BXTWC_CHGR0_IRQ, 0, 0x1f),
+   REGMAP_IRQ_REG(BXTWC_CHGR1_IRQ, 1, 0x1f),
 };
 
 static const struct regmap_irq bxtwc_regmap_irqs_tmu[] = {
REGMAP_IRQ_REG(BXTWC_TMU_IRQ, 0, 0x06),
 };
 
+static const struct regmap_irq bxtwc_regmap_irqs_crit[] = {
+   REGMAP_IRQ_REG(BXTWC_CRIT_IRQ, 0, 0x03),
+};
+
 static struct regmap_irq_chip bxtwc_regmap_irq_chip = {
.name = "bxtwc_irq_chip",

Re: [PATCH v5 3/8] thermal: intel_bxt_pmic_thermal: Use first level PMIC thermal irq

[Sathyanarayanan Kuppuswamy Natarajan]

Hi,

On Sat, Jun 3, 2017 at 10:32 AM, Andy Shevchenko
<andy.shevche...@gmail.com> wrote:
> On Sat, Jun 3, 2017 at 8:28 PM, Sathyanarayanan Kuppuswamy Natarajan
> <sathyao...@gmail.com> wrote:
>> Hi,
>>
>> On Sat, Jun 3, 2017 at 6:00 AM, Andy Shevchenko
>> <andy.shevche...@gmail.com> wrote:
>>> On Thu, Jun 1, 2017 at 1:37 AM,
>>> <sathyanarayanan.kuppusw...@linux.intel.com> wrote:
>>>> From: Kuppuswamy Sathyanarayanan 
>>>> <sathyanarayanan.kuppusw...@linux.intel.com>
>>>>
>>>> PMIC mfd driver only exports first level irq for thermal device.
>>>> But currently we are reading the irqs from the second level irq
>>>> chip, So this patch fixes this issue by adding support to use
>>>> first level PMIC thermal irq.
>>>>
>>>
>>> Shouldn't be this squashed to patch 2?
>>
>> There is no compilation dependency between patch 2 and 3. But they are
>> functionally dependent.
>>
>> Should we squash functionally dependent patches too ?
>
> Let's assume we applied patches 1 and 2, does it mean the regression
> to the existing behaviour?

Yes, Just applying patch 1 & 2 and not apply patch 3 will create
regression in thermal driver.

Since there is no compilation dependency between patch 2 & 3 and they
are from two different domains, I submitted them separately to make it
easier for review.



>
> (For example, device worked improperly in some cases -> stopped
> working completely)
>
> --
> With Best Regards,
> Andy Shevchenko



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Re: [PATCH v5 3/8] thermal: intel_bxt_pmic_thermal: Use first level PMIC thermal irq

[Sathyanarayanan Kuppuswamy Natarajan]

Hi,

On Sat, Jun 3, 2017 at 6:00 AM, Andy Shevchenko
 wrote:
> On Thu, Jun 1, 2017 at 1:37 AM,
>  wrote:
>> From: Kuppuswamy Sathyanarayanan 
>>
>> PMIC mfd driver only exports first level irq for thermal device.
>> But currently we are reading the irqs from the second level irq
>> chip, So this patch fixes this issue by adding support to use
>> first level PMIC thermal irq.
>>
>
> Shouldn't be this squashed to patch 2?

There is no compilation dependency between patch 2 and 3. But they are
functionally dependent.

Should we squash functionally dependent patches too ?

>
>> Signed-off-by: Kuppuswamy Sathyanarayanan 
>> 
>> Acked-by: Zhang Rui 
>> ---
>>  drivers/thermal/intel_bxt_pmic_thermal.c | 2 +-
>>  1 file changed, 1 insertion(+), 1 deletion(-)
>>
>> Changes since v1:
>>  * None
>>
>> Changes since v2:
>>  * Rebased on top of latest release.
>>
>> Changes since v3:
>>  * Rebased on top of latest release.
>>
>> diff --git a/drivers/thermal/intel_bxt_pmic_thermal.c 
>> b/drivers/thermal/intel_bxt_pmic_thermal.c
>> index 0f19a39..ef6b322 100644
>> --- a/drivers/thermal/intel_bxt_pmic_thermal.c
>> +++ b/drivers/thermal/intel_bxt_pmic_thermal.c
>> @@ -241,7 +241,7 @@ static int pmic_thermal_probe(struct platform_device 
>> *pdev)
>> }
>>
>> regmap = pmic->regmap;
>> -   regmap_irq_chip = pmic->irq_chip_data_level2;
>> +   regmap_irq_chip = pmic->irq_chip_data;
>>
>> pmic_irq_count = 0;
>> while ((irq = platform_get_irq(pdev, pmic_irq_count)) != -ENXIO) {
>> --
>> 2.7.4
>>
>
>
>
> --
> With Best Regards,
> Andy Shevchenko



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[PATCH v5 0/8] mfd: intel_soc_pmic_bxtwc: Add chained IRQ support

[sathyanarayanan . kuppuswamy]

From: Kuppuswamy Sathyanarayanan 

Following patch set adds chained IRQ support to WCOVE PMIC driver.

Changes since v3:
 * Added fix for typec wcove driver.

Changes since v4:
 * Squashed following two commits, to keep the patch set bisectable.
   usb: typec: typec_wcove: Use charger irq chip to get usbc virq
   mfd: intel_soc_pmic_bxtwc: use chained irqs for second level irq chips

Kuppuswamy Sathyanarayanan (8):
  mfd: intel_soc_pmic_bxtwc: Fix TMU interrupt index
  mfd: intel_soc_pmic_bxtwc: Remove thermal second level irqs
  thermal: intel_bxt_pmic_thermal: Use first level PMIC thermal irq
  mfd: intel_soc_pmic_bxtwc: Remove second level irq for gpio device
  gpio: gpio-wcove: Use first level PMIC GPIO irq
  mfd: intel_soc_pmic_bxtwc: Utilize devm_* functions in driver probe
  mfd: intel_soc_pmic_bxtwc: Use chained irqs for second level irq chips
  platform/x86: intel_bxtwc_tmu: Remove first level irq unmask

 drivers/gpio/gpio-wcove.c|  14 +-
 drivers/mfd/intel_soc_pmic_bxtwc.c   | 234 ---
 drivers/platform/x86/intel_bxtwc_tmu.c   |   4 -
 drivers/thermal/intel_bxt_pmic_thermal.c |   2 +-
 drivers/usb/typec/typec_wcove.c  |   2 +-
 include/linux/mfd/intel_soc_pmic.h   |   5 +-
 6 files changed, 175 insertions(+), 86 deletions(-)

-- 
2.7.4

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[PATCH v5 1/8] mfd: intel_soc_pmic_bxtwc: Fix TMU interrupt index

[sathyanarayanan . kuppuswamy]

From: Kuppuswamy Sathyanarayanan 

TMU interrupts are registered as a separate interrupt chip, and
hence it should start its interrupt index(BXTWC_TMU_IRQ) number
from 0. But currently, BXTWC_TMU_IRQ is defined as part of enum
bxtwc_irqs_level2 and its index value is 11. Since this index
value is used when calculating .num_irqs of regmap_irq_chip_tmu,
it incorrectly reports number of irqs as 12 instead of actual
value of 1.

This patch fixes this issue by creating new enum of tmu irqs and
resetting its starting index to 0.

Signed-off-by: Kuppuswamy Sathyanarayanan 

Acked-for-MFD-by: Lee Jones 
---
 drivers/mfd/intel_soc_pmic_bxtwc.c | 5 -
 1 file changed, 4 insertions(+), 1 deletion(-)

Changes since v1: 
 * Removed code from commit message.

Changes since v2: 
 * Rebased on top of latest release.

Changes sinve v3:
 * Rebased on top of latest release.

diff --git a/drivers/mfd/intel_soc_pmic_bxtwc.c 
b/drivers/mfd/intel_soc_pmic_bxtwc.c
index 8c3cbf6..7cbaf1e 100644
--- a/drivers/mfd/intel_soc_pmic_bxtwc.c
+++ b/drivers/mfd/intel_soc_pmic_bxtwc.c
@@ -95,7 +95,10 @@ enum bxtwc_irqs_level2 {
BXTWC_GPIO0_IRQ,
BXTWC_GPIO1_IRQ,
BXTWC_CRIT_IRQ,
-   BXTWC_TMU_IRQ,
+};
+
+enum bxtwc_irqs_tmu {
+   BXTWC_TMU_IRQ = 0,
 };
 
 static const struct regmap_irq bxtwc_regmap_irqs[] = {
-- 
2.7.4

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[PATCH v5 3/8] thermal: intel_bxt_pmic_thermal: Use first level PMIC thermal irq

[sathyanarayanan . kuppuswamy]

From: Kuppuswamy Sathyanarayanan 

PMIC mfd driver only exports first level irq for thermal device.
But currently we are reading the irqs from the second level irq
chip, So this patch fixes this issue by adding support to use
first level PMIC thermal irq.

Signed-off-by: Kuppuswamy Sathyanarayanan 

Acked-by: Zhang Rui 
---
 drivers/thermal/intel_bxt_pmic_thermal.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

Changes since v1:
 * None

Changes since v2: 
 * Rebased on top of latest release.

Changes since v3: 
 * Rebased on top of latest release.

diff --git a/drivers/thermal/intel_bxt_pmic_thermal.c 
b/drivers/thermal/intel_bxt_pmic_thermal.c
index 0f19a39..ef6b322 100644
--- a/drivers/thermal/intel_bxt_pmic_thermal.c
+++ b/drivers/thermal/intel_bxt_pmic_thermal.c
@@ -241,7 +241,7 @@ static int pmic_thermal_probe(struct platform_device *pdev)
}
 
regmap = pmic->regmap;
-   regmap_irq_chip = pmic->irq_chip_data_level2;
+   regmap_irq_chip = pmic->irq_chip_data;
 
pmic_irq_count = 0;
while ((irq = platform_get_irq(pdev, pmic_irq_count)) != -ENXIO) {
-- 
2.7.4

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[PATCH v5 2/8] mfd: intel_soc_pmic_bxtwc: Remove thermal second level irqs

[sathyanarayanan . kuppuswamy]

From: Kuppuswamy Sathyanarayanan 

Since all second level thermal irqs are consumed by the same
device(bxt_wcove_thermal), there is no need to expose them as separate
interrupts. We can just export only the first level irqs for thermal and
let the device(bxt_wcove_thermal) driver handle the second level irqs
based on thermal interrupt status register. Also, just using only the
first level irq will eliminate the bug involved in requesting only the
second level irq and not explicitly enable the first level irq. For
more info on this issue please read the details at,

https://lkml.org/lkml/2017/2/27/148

Signed-off-by: Kuppuswamy Sathyanarayanan 

Acked-for-MFD-by: Lee Jones 
---
 drivers/mfd/intel_soc_pmic_bxtwc.c | 32 
 1 file changed, 12 insertions(+), 20 deletions(-)

Changes since v1:
 * None

Changes since v2: 
 * Rebased on top of latest release.

Changes since v3:
 * Rebased on top of latest release.

diff --git a/drivers/mfd/intel_soc_pmic_bxtwc.c 
b/drivers/mfd/intel_soc_pmic_bxtwc.c
index 7cbaf1e..7c1ed27 100644
--- a/drivers/mfd/intel_soc_pmic_bxtwc.c
+++ b/drivers/mfd/intel_soc_pmic_bxtwc.c
@@ -84,10 +84,7 @@ enum bxtwc_irqs {
 
 enum bxtwc_irqs_level2 {
/* Level 2 */
-   BXTWC_THRM0_IRQ = 0,
-   BXTWC_THRM1_IRQ,
-   BXTWC_THRM2_IRQ,
-   BXTWC_BCU_IRQ,
+   BXTWC_BCU_IRQ = 0,
BXTWC_ADC_IRQ,
BXTWC_USBC_IRQ,
BXTWC_CHGR0_IRQ,
@@ -114,17 +111,14 @@ static const struct regmap_irq bxtwc_regmap_irqs[] = {
 };
 
 static const struct regmap_irq bxtwc_regmap_irqs_level2[] = {
-   REGMAP_IRQ_REG(BXTWC_THRM0_IRQ, 0, 0xff),
-   REGMAP_IRQ_REG(BXTWC_THRM1_IRQ, 1, 0xbf),
-   REGMAP_IRQ_REG(BXTWC_THRM2_IRQ, 2, 0xff),
-   REGMAP_IRQ_REG(BXTWC_BCU_IRQ, 3, 0x1f),
-   REGMAP_IRQ_REG(BXTWC_ADC_IRQ, 4, 0xff),
-   REGMAP_IRQ_REG(BXTWC_USBC_IRQ, 5, BIT(5)),
-   REGMAP_IRQ_REG(BXTWC_CHGR0_IRQ, 5, 0x1f),
-   REGMAP_IRQ_REG(BXTWC_CHGR1_IRQ, 6, 0x1f),
-   REGMAP_IRQ_REG(BXTWC_GPIO0_IRQ, 7, 0xff),
-   REGMAP_IRQ_REG(BXTWC_GPIO1_IRQ, 8, 0x3f),
-   REGMAP_IRQ_REG(BXTWC_CRIT_IRQ, 9, 0x03),
+   REGMAP_IRQ_REG(BXTWC_BCU_IRQ, 0, 0x1f),
+   REGMAP_IRQ_REG(BXTWC_ADC_IRQ, 1, 0xff),
+   REGMAP_IRQ_REG(BXTWC_USBC_IRQ, 2, BIT(5)),
+   REGMAP_IRQ_REG(BXTWC_CHGR0_IRQ, 2, 0x1f),
+   REGMAP_IRQ_REG(BXTWC_CHGR1_IRQ, 3, 0x1f),
+   REGMAP_IRQ_REG(BXTWC_GPIO0_IRQ, 4, 0xff),
+   REGMAP_IRQ_REG(BXTWC_GPIO1_IRQ, 5, 0x3f),
+   REGMAP_IRQ_REG(BXTWC_CRIT_IRQ, 6, 0x03),
 };
 
 static const struct regmap_irq bxtwc_regmap_irqs_tmu[] = {
@@ -142,8 +136,8 @@ static struct regmap_irq_chip bxtwc_regmap_irq_chip = {
 
 static struct regmap_irq_chip bxtwc_regmap_irq_chip_level2 = {
.name = "bxtwc_irq_chip_level2",
-   .status_base = BXTWC_THRM0IRQ,
-   .mask_base = BXTWC_MTHRM0IRQ,
+   .status_base = BXTWC_BCUIRQ,
+   .mask_base = BXTWC_MBCUIRQ,
.irqs = bxtwc_regmap_irqs_level2,
.num_irqs = ARRAY_SIZE(bxtwc_regmap_irqs_level2),
.num_regs = 10,
@@ -177,9 +171,7 @@ static struct resource charger_resources[] = {
 };
 
 static struct resource thermal_resources[] = {
-   DEFINE_RES_IRQ(BXTWC_THRM0_IRQ),
-   DEFINE_RES_IRQ(BXTWC_THRM1_IRQ),
-   DEFINE_RES_IRQ(BXTWC_THRM2_IRQ),
+   DEFINE_RES_IRQ(BXTWC_THRM_LVL1_IRQ),
 };
 
 static struct resource bcu_resources[] = {
-- 
2.7.4

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[PATCH v5 6/8] mfd: intel_soc_pmic_bxtwc: Utilize devm_* functions in driver probe

[sathyanarayanan . kuppuswamy]

From: Kuppuswamy Sathyanarayanan 

Cleanup the resource allocation/free code in probe function by using
devm_* calls.

Signed-off-by: Kuppuswamy Sathyanarayanan 

Acked-for-MFD-by: Lee Jones 
---
 drivers/mfd/intel_soc_pmic_bxtwc.c | 54 +-
 1 file changed, 18 insertions(+), 36 deletions(-)

Changes since v1:
 * None

Changes since v2:
 * Rebased on top of latest release.

Changes since v3:
 * None

diff --git a/drivers/mfd/intel_soc_pmic_bxtwc.c 
b/drivers/mfd/intel_soc_pmic_bxtwc.c
index af11c43..feeda6e 100644
--- a/drivers/mfd/intel_soc_pmic_bxtwc.c
+++ b/drivers/mfd/intel_soc_pmic_bxtwc.c
@@ -399,45 +399,44 @@ static int bxtwc_probe(struct platform_device *pdev)
return ret;
}
 
-   ret = regmap_add_irq_chip(pmic->regmap, pmic->irq,
- IRQF_ONESHOT | IRQF_SHARED,
- 0, _regmap_irq_chip,
- >irq_chip_data);
+   ret = devm_regmap_add_irq_chip(>dev, pmic->regmap, pmic->irq,
+  IRQF_ONESHOT | IRQF_SHARED,
+  0, _regmap_irq_chip,
+  >irq_chip_data);
if (ret) {
dev_err(>dev, "Failed to add IRQ chip\n");
return ret;
}
 
-   ret = regmap_add_irq_chip(pmic->regmap, pmic->irq,
- IRQF_ONESHOT | IRQF_SHARED,
- 0, _regmap_irq_chip_level2,
- >irq_chip_data_level2);
+   ret = devm_regmap_add_irq_chip(>dev, pmic->regmap, pmic->irq,
+  IRQF_ONESHOT | IRQF_SHARED,
+  0, _regmap_irq_chip_level2,
+  >irq_chip_data_level2);
if (ret) {
dev_err(>dev, "Failed to add secondary IRQ chip\n");
-   goto err_irq_chip_level2;
+   return ret;
}
 
-   ret = regmap_add_irq_chip(pmic->regmap, pmic->irq,
- IRQF_ONESHOT | IRQF_SHARED,
- 0, _regmap_irq_chip_tmu,
- >irq_chip_data_tmu);
+   ret = devm_regmap_add_irq_chip(>dev, pmic->regmap, pmic->irq,
+  IRQF_ONESHOT | IRQF_SHARED,
+  0, _regmap_irq_chip_tmu,
+  >irq_chip_data_tmu);
if (ret) {
dev_err(>dev, "Failed to add TMU IRQ chip\n");
-   goto err_irq_chip_tmu;
+   return ret;
}
 
-   ret = mfd_add_devices(>dev, PLATFORM_DEVID_NONE, bxt_wc_dev,
- ARRAY_SIZE(bxt_wc_dev), NULL, 0,
- NULL);
+   ret = devm_mfd_add_devices(>dev, PLATFORM_DEVID_NONE, bxt_wc_dev,
+  ARRAY_SIZE(bxt_wc_dev), NULL, 0, NULL);
if (ret) {
dev_err(>dev, "Failed to add devices\n");
-   goto err_mfd;
+   return ret;
}
 
ret = sysfs_create_group(>dev.kobj, _group);
if (ret) {
dev_err(>dev, "Failed to create sysfs group %d\n", ret);
-   goto err_sysfs;
+   return ret;
}
 
/*
@@ -451,28 +450,11 @@ static int bxtwc_probe(struct platform_device *pdev)
BXTWC_MIRQLVL1_MCHGR, 0);
 
return 0;
-
-err_sysfs:
-   mfd_remove_devices(>dev);
-err_mfd:
-   regmap_del_irq_chip(pmic->irq, pmic->irq_chip_data_tmu);
-err_irq_chip_tmu:
-   regmap_del_irq_chip(pmic->irq, pmic->irq_chip_data_level2);
-err_irq_chip_level2:
-   regmap_del_irq_chip(pmic->irq, pmic->irq_chip_data);
-
-   return ret;
 }
 
 static int bxtwc_remove(struct platform_device *pdev)
 {
-   struct intel_soc_pmic *pmic = dev_get_drvdata(>dev);
-
sysfs_remove_group(>dev.kobj, _group);
-   mfd_remove_devices(>dev);
-   regmap_del_irq_chip(pmic->irq, pmic->irq_chip_data);
-   regmap_del_irq_chip(pmic->irq, pmic->irq_chip_data_level2);
-   regmap_del_irq_chip(pmic->irq, pmic->irq_chip_data_tmu);
 
return 0;
 }
-- 
2.7.4

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[PATCH v5 7/8] mfd: intel_soc_pmic_bxtwc: Use chained irqs for second level irq chips

[sathyanarayanan . kuppuswamy]

From: Kuppuswamy Sathyanarayanan 

Whishkey cove PMIC has support to mask/unmask interrupts at two levels.
At first level we can mask/unmask interrupt domains like TMU, GPIO, ADC,
CHGR, BCU THERMAL and PWRBTN and at second level, it provides facility
to mask/unmask individual interrupts belong each of this domain. For
example, in case of TMU, at first level we have TMU interrupt domain,
and at second level we have two interrupts, wake alarm, system alarm that
belong to the TMU interrupt domain.

Currently, in this driver all first level irqs are registered as part of
irq chip(bxtwc_regmap_irq_chip). By default, after you register the irq
chip from your driver, all irqs in that chip will masked and can only be
enabled if that irq is requested using request_irq call. This is the
default Linux irq behavior model. And whenever a dependent device that
belongs to PMIC requests only the second level irq and not explicitly
unmask the first level irq, then in essence the second level irq will
still be disabled. For example, if TMU device driver request wake_alarm
irq and not explicitly unmask TMU level 1 irq then according to the default
Linux irq model,  wake_alarm irq will still be disabled. So the proper
solution to fix this issue is to use the chained irq chip concept. We
should chain all the second level chip irqs to the corresponding first
level irq. To do this, we need to create separate irq chips for every
group of second level irqs.

In case of TMU, when adding second level irq chip, instead of using pmic
irq we should use the corresponding first level irq. So the following
code will change from

ret = regmap_add_irq_chip(pmic->regmap, pmic->irq, ...)

to,

virq = regmap_irq_get_virq(>irq_chip_data, BXTWC_TMU_LVL1_IRQ);

ret = regmap_add_irq_chip(pmic->regmap, virq, ...)

In case of typec wcove driver, Since USBC IRQ is moved under charger level2
irq chip. We should use charger irq chip(irq_chip_data_chgr) to get the USBC
virtual IRQ number.

Signed-off-by: Kuppuswamy Sathyanarayanan 

Acked-for-MFD-by: Lee Jones 
---
 drivers/mfd/intel_soc_pmic_bxtwc.c | 174 +
 drivers/usb/typec/typec_wcove.c|   2 +-
 include/linux/mfd/intel_soc_pmic.h |   5 +-
 3 files changed, 145 insertions(+), 36 deletions(-)

Changes since v1:
 * Rebased on top of dev_* cleanup patch.
 * Fixed style & grammer issues reported by Lee Jones

Changes since v2:
 * Rebased on top of latest release.

Changes since v3:
 * None

Changes since v4:
 * Merged typec driver fix to this patch to prevent branch bisect issue.

diff --git a/drivers/mfd/intel_soc_pmic_bxtwc.c 
b/drivers/mfd/intel_soc_pmic_bxtwc.c
index feeda6e..bd78bef 100644
--- a/drivers/mfd/intel_soc_pmic_bxtwc.c
+++ b/drivers/mfd/intel_soc_pmic_bxtwc.c
@@ -82,18 +82,26 @@ enum bxtwc_irqs {
BXTWC_PWRBTN_IRQ,
 };
 
-enum bxtwc_irqs_level2 {
-   /* Level 2 */
+enum bxtwc_irqs_tmu {
+   BXTWC_TMU_IRQ = 0,
+};
+
+enum bxtwc_irqs_bcu {
BXTWC_BCU_IRQ = 0,
-   BXTWC_ADC_IRQ,
-   BXTWC_USBC_IRQ,
+};
+
+enum bxtwc_irqs_adc {
+   BXTWC_ADC_IRQ = 0,
+};
+
+enum bxtwc_irqs_chgr {
+   BXTWC_USBC_IRQ = 0,
BXTWC_CHGR0_IRQ,
BXTWC_CHGR1_IRQ,
-   BXTWC_CRIT_IRQ,
 };
 
-enum bxtwc_irqs_tmu {
-   BXTWC_TMU_IRQ = 0,
+enum bxtwc_irqs_crit {
+   BXTWC_CRIT_IRQ = 0,
 };
 
 static const struct regmap_irq bxtwc_regmap_irqs[] = {
@@ -108,17 +116,26 @@ static const struct regmap_irq bxtwc_regmap_irqs[] = {
REGMAP_IRQ_REG(BXTWC_PWRBTN_IRQ, 1, 0x03),
 };
 
-static const struct regmap_irq bxtwc_regmap_irqs_level2[] = {
+static const struct regmap_irq bxtwc_regmap_irqs_tmu[] = {
+   REGMAP_IRQ_REG(BXTWC_TMU_IRQ, 0, 0x06),
+};
+
+static const struct regmap_irq bxtwc_regmap_irqs_bcu[] = {
REGMAP_IRQ_REG(BXTWC_BCU_IRQ, 0, 0x1f),
-   REGMAP_IRQ_REG(BXTWC_ADC_IRQ, 1, 0xff),
-   REGMAP_IRQ_REG(BXTWC_USBC_IRQ, 2, BIT(5)),
-   REGMAP_IRQ_REG(BXTWC_CHGR0_IRQ, 2, 0x1f),
-   REGMAP_IRQ_REG(BXTWC_CHGR1_IRQ, 3, 0x1f),
-   REGMAP_IRQ_REG(BXTWC_CRIT_IRQ, 6, 0x03),
 };
 
-static const struct regmap_irq bxtwc_regmap_irqs_tmu[] = {
-   REGMAP_IRQ_REG(BXTWC_TMU_IRQ, 0, 0x06),
+static const struct regmap_irq bxtwc_regmap_irqs_adc[] = {
+   REGMAP_IRQ_REG(BXTWC_ADC_IRQ, 0, 0xff),
+};
+
+static const struct regmap_irq bxtwc_regmap_irqs_chgr[] = {
+   REGMAP_IRQ_REG(BXTWC_USBC_IRQ, 0, BIT(5)),
+   REGMAP_IRQ_REG(BXTWC_CHGR0_IRQ, 0, 0x1f),
+   REGMAP_IRQ_REG(BXTWC_CHGR1_IRQ, 1, 0x1f),
+};
+
+static const struct regmap_irq bxtwc_regmap_irqs_crit[] = {
+   REGMAP_IRQ_REG(BXTWC_CRIT_IRQ, 0, 0x03),
 };
 
 static struct regmap_irq_chip bxtwc_regmap_irq_chip = {
@@ -130,15 +147,6 @@ static struct regmap_irq_chip bxtwc_regmap_irq_chip = {
.num_regs = 2,
 };
 
-static struct regmap_irq_chip bxtwc_regmap_irq_chip_level2 = {
-   .name = 

[PATCH v5 4/8] mfd: intel_soc_pmic_bxtwc: Remove second level irq for gpio device

[sathyanarayanan . kuppuswamy]

From: Kuppuswamy Sathyanarayanan 

Currently all PMIC GPIO domain irqs are consumed by the same
device(bxt_wcove_gpio), so there is no need to export them as
separate interrupts. We can just export only the first level
GPIO irq(BXTWC_GPIO_LVL1_IRQ) as an irq resource and let the
GPIO device driver(bxt_wcove_gpio) handle the GPIO sub domain
irqs based on status value of GPIO level2 interrupt status
register. Also, just using only the first level irq will eliminate
the bug involved in requesting only the second level irq and not
explicitly enable the first level irq. For more info on this
issue please read the details at,

https://lkml.org/lkml/2017/2/27/148

Signed-off-by: Kuppuswamy Sathyanarayanan 

Acked-for-MFD-by: Lee Jones 
---
 drivers/mfd/intel_soc_pmic_bxtwc.c | 7 +--
 1 file changed, 1 insertion(+), 6 deletions(-)

Changes since v1:
 * None

Changes since v2: 
 * Rebased on top of latest release.

Changes since v3:
 * None

diff --git a/drivers/mfd/intel_soc_pmic_bxtwc.c 
b/drivers/mfd/intel_soc_pmic_bxtwc.c
index 7c1ed27..af11c43 100644
--- a/drivers/mfd/intel_soc_pmic_bxtwc.c
+++ b/drivers/mfd/intel_soc_pmic_bxtwc.c
@@ -89,8 +89,6 @@ enum bxtwc_irqs_level2 {
BXTWC_USBC_IRQ,
BXTWC_CHGR0_IRQ,
BXTWC_CHGR1_IRQ,
-   BXTWC_GPIO0_IRQ,
-   BXTWC_GPIO1_IRQ,
BXTWC_CRIT_IRQ,
 };
 
@@ -116,8 +114,6 @@ static const struct regmap_irq bxtwc_regmap_irqs_level2[] = 
{
REGMAP_IRQ_REG(BXTWC_USBC_IRQ, 2, BIT(5)),
REGMAP_IRQ_REG(BXTWC_CHGR0_IRQ, 2, 0x1f),
REGMAP_IRQ_REG(BXTWC_CHGR1_IRQ, 3, 0x1f),
-   REGMAP_IRQ_REG(BXTWC_GPIO0_IRQ, 4, 0xff),
-   REGMAP_IRQ_REG(BXTWC_GPIO1_IRQ, 5, 0x3f),
REGMAP_IRQ_REG(BXTWC_CRIT_IRQ, 6, 0x03),
 };
 
@@ -153,8 +149,7 @@ static struct regmap_irq_chip bxtwc_regmap_irq_chip_tmu = {
 };
 
 static struct resource gpio_resources[] = {
-   DEFINE_RES_IRQ_NAMED(BXTWC_GPIO0_IRQ, "GPIO0"),
-   DEFINE_RES_IRQ_NAMED(BXTWC_GPIO1_IRQ, "GPIO1"),
+   DEFINE_RES_IRQ_NAMED(BXTWC_GPIO_LVL1_IRQ, "GPIO"),
 };
 
 static struct resource adc_resources[] = {
-- 
2.7.4

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[PATCH v5 5/8] gpio: gpio-wcove: Use first level PMIC GPIO irq

[sathyanarayanan . kuppuswamy]

From: Kuppuswamy Sathyanarayanan 

PMIC mfd driver only exports first level irq for GPIO device.
But currently we are reading the irqs from the second level irq
chip, So this patch fixes this issue by adding support to use
first level PMIC GPIO irq.

Signed-off-by: Kuppuswamy Sathyanarayanan 

Acked-by: Linus Walleij 
---
 drivers/gpio/gpio-wcove.c | 14 +-
 1 file changed, 13 insertions(+), 1 deletion(-)

Changes since v1:
 * used correct mask for GPIO0 and GPIO1 interrupts

Changes since v2: 
 * Rebased on top of latest release.
 * Removed IRQ0 and IRQ1 mask defines.

Changes since v3:
 * None

diff --git a/drivers/gpio/gpio-wcove.c b/drivers/gpio/gpio-wcove.c
index 7b1bc20..bba7704 100644
--- a/drivers/gpio/gpio-wcove.c
+++ b/drivers/gpio/gpio-wcove.c
@@ -401,7 +401,7 @@ static int wcove_gpio_probe(struct platform_device *pdev)
if (!wg)
return -ENOMEM;
 
-   wg->regmap_irq_chip = pmic->irq_chip_data_level2;
+   wg->regmap_irq_chip = pmic->irq_chip_data;
 
platform_set_drvdata(pdev, wg);
 
@@ -449,6 +449,18 @@ static int wcove_gpio_probe(struct platform_device *pdev)
 
gpiochip_set_nested_irqchip(>chip, _irqchip, virq);
 
+   /* Enable GPIO0 interrupts */
+   ret = regmap_update_bits(wg->regmap, IRQ_MASK_BASE, GPIO_IRQ0_MASK,
+0x00);
+   if (ret)
+   return ret;
+
+   /* Enable GPIO1 interrupts */
+   ret = regmap_update_bits(wg->regmap, IRQ_MASK_BASE + 1, GPIO_IRQ1_MASK,
+0x00);
+   if (ret)
+   return ret;
+
return 0;
 }
 
-- 
2.7.4

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[PATCH v5 8/8] platform/x86: intel_bxtwc_tmu: Remove first level irq unmask

[sathyanarayanan . kuppuswamy]

From: Kuppuswamy Sathyanarayanan 

Currently in WCOVE PMIC mfd driver, all second level irq chips
are chained to the respective first level irqs. So there is no
need for explicitly unmasking the first level irq in this
driver. This patches removes this level 1 irq unmask support.

Signed-off-by: Kuppuswamy Sathyanarayanan 

Reviewed-by: Darren Hart (VMware) 
Reviewed-by: Andy Shevchenko 
---
 drivers/platform/x86/intel_bxtwc_tmu.c | 4 
 1 file changed, 4 deletions(-)

Changes since v1:
 * None

Changes since v2:
 * Rebased on top of latest release.

Changes since v3:
 * None

Changes since v4:
 * Changed commit subject from "platform: x86:" "to platform/x86:"

diff --git a/drivers/platform/x86/intel_bxtwc_tmu.c 
b/drivers/platform/x86/intel_bxtwc_tmu.c
index e202abd..ea865d4 100644
--- a/drivers/platform/x86/intel_bxtwc_tmu.c
+++ b/drivers/platform/x86/intel_bxtwc_tmu.c
@@ -92,10 +92,6 @@ static int bxt_wcove_tmu_probe(struct platform_device *pdev)
}
wctmu->irq = virq;
 
-   /* Enable TMU interrupts */
-   regmap_update_bits(wctmu->regmap, BXTWC_MIRQLVL1,
- BXTWC_MIRQLVL1_MTMU, 0);
-
/* Unmask TMU second level Wake & System alarm */
regmap_update_bits(wctmu->regmap, BXTWC_MTMUIRQ_REG,
  BXTWC_TMU_ALRM_MASK, 0);
-- 
2.7.4

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[PATCH v4 0/9] WCOVE chained IRQ fix

[sathyanarayanan . kuppuswamy]

From: Kuppuswamy Sathyanarayanan 

Following patch set fixes the chained IRQ issue observed in WCOVE PMIC driver.

Changes since v3:
 * Added fix for typec wcove driver.

Kuppuswamy Sathyanarayanan (9):
  mfd: intel_soc_pmic_bxtwc: fix TMU interrupt index
  mfd: intel_soc_pmic_bxtwc: remove thermal second level irqs
  thermal: intel_bxt_pmic_thermal: use first level PMIC thermal irq
  mfd: intel_soc_pmic_bxtwc: remove second level irq for gpio device
  gpio: gpio-wcove: use first level PMIC GPIO irq
  mfd: intel_soc_pmic_bxtwc: utilize devm_* functions in driver probe
  mfd: intel_soc_pmic_bxtwc: use chained irqs for second level irq chips
  platform: x86: intel_bxtwc_tmu: remove first level irq unmask
  usb: typec: typec_wcove: Use charger irq chip to get usbc virq

 drivers/gpio/gpio-wcove.c|  14 +-
 drivers/mfd/intel_soc_pmic_bxtwc.c   | 234 ---
 drivers/platform/x86/intel_bxtwc_tmu.c   |   4 -
 drivers/thermal/intel_bxt_pmic_thermal.c |   2 +-
 drivers/usb/typec/typec_wcove.c  |   2 +-
 include/linux/mfd/intel_soc_pmic.h   |   5 +-
 6 files changed, 175 insertions(+), 86 deletions(-)

-- 
2.7.4

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[PATCH v4 1/9] mfd: intel_soc_pmic_bxtwc: fix TMU interrupt index

[sathyanarayanan . kuppuswamy]

From: Kuppuswamy Sathyanarayanan 

TMU interrupts are registered as a separate interrupt chip, and
hence it should start its interrupt index(BXTWC_TMU_IRQ) number
from 0. But currently, BXTWC_TMU_IRQ is defined as part of enum
bxtwc_irqs_level2 and its index value is 11. Since this index
value is used when calculating .num_irqs of regmap_irq_chip_tmu,
it incorrectly reports number of irqs as 12 instead of actual
value of 1.

This patch fixes this issue by creating new enum of tmu irqs and
resetting its starting index to 0.

Signed-off-by: Kuppuswamy Sathyanarayanan 

Acked-for-MFD-by: Lee Jones 
---
 drivers/mfd/intel_soc_pmic_bxtwc.c | 5 -
 1 file changed, 4 insertions(+), 1 deletion(-)

Changes since v1: 
 * Removed code from commit message.

Changes since v2: 
 * Rebased on top of latest release.

Changes sinve v3:
 * Rebased on top of latest release.

diff --git a/drivers/mfd/intel_soc_pmic_bxtwc.c 
b/drivers/mfd/intel_soc_pmic_bxtwc.c
index 8c3cbf6..7cbaf1e 100644
--- a/drivers/mfd/intel_soc_pmic_bxtwc.c
+++ b/drivers/mfd/intel_soc_pmic_bxtwc.c
@@ -95,7 +95,10 @@ enum bxtwc_irqs_level2 {
BXTWC_GPIO0_IRQ,
BXTWC_GPIO1_IRQ,
BXTWC_CRIT_IRQ,
-   BXTWC_TMU_IRQ,
+};
+
+enum bxtwc_irqs_tmu {
+   BXTWC_TMU_IRQ = 0,
 };
 
 static const struct regmap_irq bxtwc_regmap_irqs[] = {
-- 
2.7.4

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[PATCH v4 6/9] mfd: intel_soc_pmic_bxtwc: utilize devm_* functions in driver probe

[sathyanarayanan . kuppuswamy]

From: Kuppuswamy Sathyanarayanan 

Cleanup the resource allocation/free code in probe function by using
devm_* calls.

Signed-off-by: Kuppuswamy Sathyanarayanan 

Acked-for-MFD-by: Lee Jones 
---
 drivers/mfd/intel_soc_pmic_bxtwc.c | 54 +-
 1 file changed, 18 insertions(+), 36 deletions(-)

Changes since v1:
 * None

Changes since v2:
 * Rebased on top of latest release.

Changes since v3:
 * None

diff --git a/drivers/mfd/intel_soc_pmic_bxtwc.c 
b/drivers/mfd/intel_soc_pmic_bxtwc.c
index af11c43..feeda6e 100644
--- a/drivers/mfd/intel_soc_pmic_bxtwc.c
+++ b/drivers/mfd/intel_soc_pmic_bxtwc.c
@@ -399,45 +399,44 @@ static int bxtwc_probe(struct platform_device *pdev)
return ret;
}
 
-   ret = regmap_add_irq_chip(pmic->regmap, pmic->irq,
- IRQF_ONESHOT | IRQF_SHARED,
- 0, _regmap_irq_chip,
- >irq_chip_data);
+   ret = devm_regmap_add_irq_chip(>dev, pmic->regmap, pmic->irq,
+  IRQF_ONESHOT | IRQF_SHARED,
+  0, _regmap_irq_chip,
+  >irq_chip_data);
if (ret) {
dev_err(>dev, "Failed to add IRQ chip\n");
return ret;
}
 
-   ret = regmap_add_irq_chip(pmic->regmap, pmic->irq,
- IRQF_ONESHOT | IRQF_SHARED,
- 0, _regmap_irq_chip_level2,
- >irq_chip_data_level2);
+   ret = devm_regmap_add_irq_chip(>dev, pmic->regmap, pmic->irq,
+  IRQF_ONESHOT | IRQF_SHARED,
+  0, _regmap_irq_chip_level2,
+  >irq_chip_data_level2);
if (ret) {
dev_err(>dev, "Failed to add secondary IRQ chip\n");
-   goto err_irq_chip_level2;
+   return ret;
}
 
-   ret = regmap_add_irq_chip(pmic->regmap, pmic->irq,
- IRQF_ONESHOT | IRQF_SHARED,
- 0, _regmap_irq_chip_tmu,
- >irq_chip_data_tmu);
+   ret = devm_regmap_add_irq_chip(>dev, pmic->regmap, pmic->irq,
+  IRQF_ONESHOT | IRQF_SHARED,
+  0, _regmap_irq_chip_tmu,
+  >irq_chip_data_tmu);
if (ret) {
dev_err(>dev, "Failed to add TMU IRQ chip\n");
-   goto err_irq_chip_tmu;
+   return ret;
}
 
-   ret = mfd_add_devices(>dev, PLATFORM_DEVID_NONE, bxt_wc_dev,
- ARRAY_SIZE(bxt_wc_dev), NULL, 0,
- NULL);
+   ret = devm_mfd_add_devices(>dev, PLATFORM_DEVID_NONE, bxt_wc_dev,
+  ARRAY_SIZE(bxt_wc_dev), NULL, 0, NULL);
if (ret) {
dev_err(>dev, "Failed to add devices\n");
-   goto err_mfd;
+   return ret;
}
 
ret = sysfs_create_group(>dev.kobj, _group);
if (ret) {
dev_err(>dev, "Failed to create sysfs group %d\n", ret);
-   goto err_sysfs;
+   return ret;
}
 
/*
@@ -451,28 +450,11 @@ static int bxtwc_probe(struct platform_device *pdev)
BXTWC_MIRQLVL1_MCHGR, 0);
 
return 0;
-
-err_sysfs:
-   mfd_remove_devices(>dev);
-err_mfd:
-   regmap_del_irq_chip(pmic->irq, pmic->irq_chip_data_tmu);
-err_irq_chip_tmu:
-   regmap_del_irq_chip(pmic->irq, pmic->irq_chip_data_level2);
-err_irq_chip_level2:
-   regmap_del_irq_chip(pmic->irq, pmic->irq_chip_data);
-
-   return ret;
 }
 
 static int bxtwc_remove(struct platform_device *pdev)
 {
-   struct intel_soc_pmic *pmic = dev_get_drvdata(>dev);
-
sysfs_remove_group(>dev.kobj, _group);
-   mfd_remove_devices(>dev);
-   regmap_del_irq_chip(pmic->irq, pmic->irq_chip_data);
-   regmap_del_irq_chip(pmic->irq, pmic->irq_chip_data_level2);
-   regmap_del_irq_chip(pmic->irq, pmic->irq_chip_data_tmu);
 
return 0;
 }
-- 
2.7.4

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[PATCH v4 9/9] usb: typec: typec_wcove: Use charger irq chip to get usbc virq

[sathyanarayanan . kuppuswamy]

From: Kuppuswamy Sathyanarayanan 

Currently, in Whiskey cove PMIC driver, USBC IRQ is moved under charger
level2 irq chip. So use irq_chip_data_chgr to get the USBC virtual IRQ
number.

Signed-off-by: Kuppuswamy Sathyanarayanan 

---
 drivers/usb/typec/typec_wcove.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

Changes since v3:
 * Added typec fix.

diff --git a/drivers/usb/typec/typec_wcove.c b/drivers/usb/typec/typec_wcove.c
index d5a7b21..00a4bd2 100644
--- a/drivers/usb/typec/typec_wcove.c
+++ b/drivers/usb/typec/typec_wcove.c
@@ -303,7 +303,7 @@ static int wcove_typec_probe(struct platform_device *pdev)
wcove->dev = >dev;
wcove->regmap = pmic->regmap;
 
-   ret = regmap_irq_get_virq(pmic->irq_chip_data_level2,
+   ret = regmap_irq_get_virq(pmic->irq_chip_data_chgr,
  platform_get_irq(pdev, 0));
if (ret < 0)
return ret;
-- 
2.7.4

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[PATCH v4 2/9] mfd: intel_soc_pmic_bxtwc: remove thermal second level irqs

[sathyanarayanan . kuppuswamy]

From: Kuppuswamy Sathyanarayanan 

Since all second level thermal irqs are consumed by the same
device(bxt_wcove_thermal), there is no need to expose them as separate
interrupts. We can just export only the first level irqs for thermal and
let the device(bxt_wcove_thermal) driver handle the second level irqs
based on thermal interrupt status register. Also, just using only the
first level irq will eliminate the bug involved in requesting only the
second level irq and not explicitly enable the first level irq. For
more info on this issue please read the details at,

https://lkml.org/lkml/2017/2/27/148

Signed-off-by: Kuppuswamy Sathyanarayanan 

Acked-for-MFD-by: Lee Jones 
---
 drivers/mfd/intel_soc_pmic_bxtwc.c | 32 
 1 file changed, 12 insertions(+), 20 deletions(-)

Changes since v1:
 * None

Changes since v2: 
 * Rebased on top of latest release.

Changes since v3:
 * Rebased on top of latest release.

diff --git a/drivers/mfd/intel_soc_pmic_bxtwc.c 
b/drivers/mfd/intel_soc_pmic_bxtwc.c
index 7cbaf1e..7c1ed27 100644
--- a/drivers/mfd/intel_soc_pmic_bxtwc.c
+++ b/drivers/mfd/intel_soc_pmic_bxtwc.c
@@ -84,10 +84,7 @@ enum bxtwc_irqs {
 
 enum bxtwc_irqs_level2 {
/* Level 2 */
-   BXTWC_THRM0_IRQ = 0,
-   BXTWC_THRM1_IRQ,
-   BXTWC_THRM2_IRQ,
-   BXTWC_BCU_IRQ,
+   BXTWC_BCU_IRQ = 0,
BXTWC_ADC_IRQ,
BXTWC_USBC_IRQ,
BXTWC_CHGR0_IRQ,
@@ -114,17 +111,14 @@ static const struct regmap_irq bxtwc_regmap_irqs[] = {
 };
 
 static const struct regmap_irq bxtwc_regmap_irqs_level2[] = {
-   REGMAP_IRQ_REG(BXTWC_THRM0_IRQ, 0, 0xff),
-   REGMAP_IRQ_REG(BXTWC_THRM1_IRQ, 1, 0xbf),
-   REGMAP_IRQ_REG(BXTWC_THRM2_IRQ, 2, 0xff),
-   REGMAP_IRQ_REG(BXTWC_BCU_IRQ, 3, 0x1f),
-   REGMAP_IRQ_REG(BXTWC_ADC_IRQ, 4, 0xff),
-   REGMAP_IRQ_REG(BXTWC_USBC_IRQ, 5, BIT(5)),
-   REGMAP_IRQ_REG(BXTWC_CHGR0_IRQ, 5, 0x1f),
-   REGMAP_IRQ_REG(BXTWC_CHGR1_IRQ, 6, 0x1f),
-   REGMAP_IRQ_REG(BXTWC_GPIO0_IRQ, 7, 0xff),
-   REGMAP_IRQ_REG(BXTWC_GPIO1_IRQ, 8, 0x3f),
-   REGMAP_IRQ_REG(BXTWC_CRIT_IRQ, 9, 0x03),
+   REGMAP_IRQ_REG(BXTWC_BCU_IRQ, 0, 0x1f),
+   REGMAP_IRQ_REG(BXTWC_ADC_IRQ, 1, 0xff),
+   REGMAP_IRQ_REG(BXTWC_USBC_IRQ, 2, BIT(5)),
+   REGMAP_IRQ_REG(BXTWC_CHGR0_IRQ, 2, 0x1f),
+   REGMAP_IRQ_REG(BXTWC_CHGR1_IRQ, 3, 0x1f),
+   REGMAP_IRQ_REG(BXTWC_GPIO0_IRQ, 4, 0xff),
+   REGMAP_IRQ_REG(BXTWC_GPIO1_IRQ, 5, 0x3f),
+   REGMAP_IRQ_REG(BXTWC_CRIT_IRQ, 6, 0x03),
 };
 
 static const struct regmap_irq bxtwc_regmap_irqs_tmu[] = {
@@ -142,8 +136,8 @@ static struct regmap_irq_chip bxtwc_regmap_irq_chip = {
 
 static struct regmap_irq_chip bxtwc_regmap_irq_chip_level2 = {
.name = "bxtwc_irq_chip_level2",
-   .status_base = BXTWC_THRM0IRQ,
-   .mask_base = BXTWC_MTHRM0IRQ,
+   .status_base = BXTWC_BCUIRQ,
+   .mask_base = BXTWC_MBCUIRQ,
.irqs = bxtwc_regmap_irqs_level2,
.num_irqs = ARRAY_SIZE(bxtwc_regmap_irqs_level2),
.num_regs = 10,
@@ -177,9 +171,7 @@ static struct resource charger_resources[] = {
 };
 
 static struct resource thermal_resources[] = {
-   DEFINE_RES_IRQ(BXTWC_THRM0_IRQ),
-   DEFINE_RES_IRQ(BXTWC_THRM1_IRQ),
-   DEFINE_RES_IRQ(BXTWC_THRM2_IRQ),
+   DEFINE_RES_IRQ(BXTWC_THRM_LVL1_IRQ),
 };
 
 static struct resource bcu_resources[] = {
-- 
2.7.4

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[PATCH v4 5/9] gpio: gpio-wcove: use first level PMIC GPIO irq

[sathyanarayanan . kuppuswamy]

From: Kuppuswamy Sathyanarayanan 

PMIC mfd driver only exports first level irq for GPIO device.
But currently we are reading the irqs from the second level irq
chip, So this patch fixes this issue by adding support to use
first level PMIC GPIO irq.

Signed-off-by: Kuppuswamy Sathyanarayanan 

Acked-by: Linus Walleij 
---
 drivers/gpio/gpio-wcove.c | 14 +-
 1 file changed, 13 insertions(+), 1 deletion(-)

Changes since v1:
 * used correct mask for GPIO0 and GPIO1 interrupts

Changes since v2: 
 * Rebased on top of latest release.
 * Removed IRQ0 and IRQ1 mask defines.

Changes since v3:
 * None

diff --git a/drivers/gpio/gpio-wcove.c b/drivers/gpio/gpio-wcove.c
index 7b1bc20..bba7704 100644
--- a/drivers/gpio/gpio-wcove.c
+++ b/drivers/gpio/gpio-wcove.c
@@ -401,7 +401,7 @@ static int wcove_gpio_probe(struct platform_device *pdev)
if (!wg)
return -ENOMEM;
 
-   wg->regmap_irq_chip = pmic->irq_chip_data_level2;
+   wg->regmap_irq_chip = pmic->irq_chip_data;
 
platform_set_drvdata(pdev, wg);
 
@@ -449,6 +449,18 @@ static int wcove_gpio_probe(struct platform_device *pdev)
 
gpiochip_set_nested_irqchip(>chip, _irqchip, virq);
 
+   /* Enable GPIO0 interrupts */
+   ret = regmap_update_bits(wg->regmap, IRQ_MASK_BASE, GPIO_IRQ0_MASK,
+0x00);
+   if (ret)
+   return ret;
+
+   /* Enable GPIO1 interrupts */
+   ret = regmap_update_bits(wg->regmap, IRQ_MASK_BASE + 1, GPIO_IRQ1_MASK,
+0x00);
+   if (ret)
+   return ret;
+
return 0;
 }
 
-- 
2.7.4

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[PATCH v4 3/9] thermal: intel_bxt_pmic_thermal: use first level PMIC thermal irq

[sathyanarayanan . kuppuswamy]

From: Kuppuswamy Sathyanarayanan 

PMIC mfd driver only exports first level irq for thermal device.
But currently we are reading the irqs from the second level irq
chip, So this patch fixes this issue by adding support to use
first level PMIC thermal irq.

Signed-off-by: Kuppuswamy Sathyanarayanan 

Acked-by: Zhang Rui 
---
 drivers/thermal/intel_bxt_pmic_thermal.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

Changes since v1:
 * None

Changes since v2: 
 * Rebased on top of latest release.

Changes since v3: 
 * Rebased on top of latest release.

diff --git a/drivers/thermal/intel_bxt_pmic_thermal.c 
b/drivers/thermal/intel_bxt_pmic_thermal.c
index 0f19a39..ef6b322 100644
--- a/drivers/thermal/intel_bxt_pmic_thermal.c
+++ b/drivers/thermal/intel_bxt_pmic_thermal.c
@@ -241,7 +241,7 @@ static int pmic_thermal_probe(struct platform_device *pdev)
}
 
regmap = pmic->regmap;
-   regmap_irq_chip = pmic->irq_chip_data_level2;
+   regmap_irq_chip = pmic->irq_chip_data;
 
pmic_irq_count = 0;
while ((irq = platform_get_irq(pdev, pmic_irq_count)) != -ENXIO) {
-- 
2.7.4

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[PATCH v4 7/9] mfd: intel_soc_pmic_bxtwc: use chained irqs for second level irq chips

[sathyanarayanan . kuppuswamy]

From: Kuppuswamy Sathyanarayanan 

Whishkey cove PMIC has support to mask/unmask interrupts at two levels.
At first level we can mask/unmask interrupt domains like TMU, GPIO, ADC,
CHGR, BCU THERMAL and PWRBTN and at second level, it provides facility
to mask/unmask individual interrupts belong each of this domain. For
example, in case of TMU, at first level we have TMU interrupt domain,
and at second level we have two interrupts, wake alarm, system alarm that
belong to the TMU interrupt domain.

Currently, in this driver all first level irqs are registered as part of
irq chip(bxtwc_regmap_irq_chip). By default, after you register the irq
chip from your driver, all irqs in that chip will masked and can only be
enabled if that irq is requested using request_irq call. This is the
default Linux irq behavior model. And whenever a dependent device that
belongs to PMIC requests only the second level irq and not explicitly
unmask the first level irq, then in essence the second level irq will
still be disabled. For example, if TMU device driver request wake_alarm
irq and not explicitly unmask TMU level 1 irq then according to the default
Linux irq model,  wake_alarm irq will still be disabled. So the proper
solution to fix this issue is to use the chained irq chip concept. We
should chain all the second level chip irqs to the corresponding first
level irq. To do this, we need to create separate irq chips for every
group of second level irqs.

In case of TMU, when adding second level irq chip, instead of using pmic
irq we should use the corresponding first level irq. So the following
code will change from

ret = regmap_add_irq_chip(pmic->regmap, pmic->irq, ...)

to,

virq = regmap_irq_get_virq(>irq_chip_data, BXTWC_TMU_LVL1_IRQ);

ret = regmap_add_irq_chip(pmic->regmap, virq, ...)

Signed-off-by: Kuppuswamy Sathyanarayanan 

Acked-for-MFD-by: Lee Jones 
---
 drivers/mfd/intel_soc_pmic_bxtwc.c | 174 +
 include/linux/mfd/intel_soc_pmic.h |   5 +-
 2 files changed, 144 insertions(+), 35 deletions(-)

Changes since v1:
 * Rebased on top of dev_* cleanup patch.
 * Fixed style & grammer issues reported by Lee Jones

Changes since v2:
 * Rebased on top of latest release.

Changes since v3:
 * None

diff --git a/drivers/mfd/intel_soc_pmic_bxtwc.c 
b/drivers/mfd/intel_soc_pmic_bxtwc.c
index feeda6e..bd78bef 100644
--- a/drivers/mfd/intel_soc_pmic_bxtwc.c
+++ b/drivers/mfd/intel_soc_pmic_bxtwc.c
@@ -82,18 +82,26 @@ enum bxtwc_irqs {
BXTWC_PWRBTN_IRQ,
 };
 
-enum bxtwc_irqs_level2 {
-   /* Level 2 */
+enum bxtwc_irqs_tmu {
+   BXTWC_TMU_IRQ = 0,
+};
+
+enum bxtwc_irqs_bcu {
BXTWC_BCU_IRQ = 0,
-   BXTWC_ADC_IRQ,
-   BXTWC_USBC_IRQ,
+};
+
+enum bxtwc_irqs_adc {
+   BXTWC_ADC_IRQ = 0,
+};
+
+enum bxtwc_irqs_chgr {
+   BXTWC_USBC_IRQ = 0,
BXTWC_CHGR0_IRQ,
BXTWC_CHGR1_IRQ,
-   BXTWC_CRIT_IRQ,
 };
 
-enum bxtwc_irqs_tmu {
-   BXTWC_TMU_IRQ = 0,
+enum bxtwc_irqs_crit {
+   BXTWC_CRIT_IRQ = 0,
 };
 
 static const struct regmap_irq bxtwc_regmap_irqs[] = {
@@ -108,17 +116,26 @@ static const struct regmap_irq bxtwc_regmap_irqs[] = {
REGMAP_IRQ_REG(BXTWC_PWRBTN_IRQ, 1, 0x03),
 };
 
-static const struct regmap_irq bxtwc_regmap_irqs_level2[] = {
+static const struct regmap_irq bxtwc_regmap_irqs_tmu[] = {
+   REGMAP_IRQ_REG(BXTWC_TMU_IRQ, 0, 0x06),
+};
+
+static const struct regmap_irq bxtwc_regmap_irqs_bcu[] = {
REGMAP_IRQ_REG(BXTWC_BCU_IRQ, 0, 0x1f),
-   REGMAP_IRQ_REG(BXTWC_ADC_IRQ, 1, 0xff),
-   REGMAP_IRQ_REG(BXTWC_USBC_IRQ, 2, BIT(5)),
-   REGMAP_IRQ_REG(BXTWC_CHGR0_IRQ, 2, 0x1f),
-   REGMAP_IRQ_REG(BXTWC_CHGR1_IRQ, 3, 0x1f),
-   REGMAP_IRQ_REG(BXTWC_CRIT_IRQ, 6, 0x03),
 };
 
-static const struct regmap_irq bxtwc_regmap_irqs_tmu[] = {
-   REGMAP_IRQ_REG(BXTWC_TMU_IRQ, 0, 0x06),
+static const struct regmap_irq bxtwc_regmap_irqs_adc[] = {
+   REGMAP_IRQ_REG(BXTWC_ADC_IRQ, 0, 0xff),
+};
+
+static const struct regmap_irq bxtwc_regmap_irqs_chgr[] = {
+   REGMAP_IRQ_REG(BXTWC_USBC_IRQ, 0, BIT(5)),
+   REGMAP_IRQ_REG(BXTWC_CHGR0_IRQ, 0, 0x1f),
+   REGMAP_IRQ_REG(BXTWC_CHGR1_IRQ, 1, 0x1f),
+};
+
+static const struct regmap_irq bxtwc_regmap_irqs_crit[] = {
+   REGMAP_IRQ_REG(BXTWC_CRIT_IRQ, 0, 0x03),
 };
 
 static struct regmap_irq_chip bxtwc_regmap_irq_chip = {
@@ -130,15 +147,6 @@ static struct regmap_irq_chip bxtwc_regmap_irq_chip = {
.num_regs = 2,
 };
 
-static struct regmap_irq_chip bxtwc_regmap_irq_chip_level2 = {
-   .name = "bxtwc_irq_chip_level2",
-   .status_base = BXTWC_BCUIRQ,
-   .mask_base = BXTWC_MBCUIRQ,
-   .irqs = bxtwc_regmap_irqs_level2,
-   .num_irqs = ARRAY_SIZE(bxtwc_regmap_irqs_level2),
-   .num_regs = 10,
-};
-
 static struct regmap_irq_chip bxtwc_regmap_irq_chip_tmu = {
.name = "bxtwc_irq_chip_tmu",
  

[PATCH v4 8/9] platform: x86: intel_bxtwc_tmu: remove first level irq unmask

[sathyanarayanan . kuppuswamy]

From: Kuppuswamy Sathyanarayanan 

Currently in WCOVE PMIC mfd driver, all second level irq chips
are chained to the respective first level irqs. So there is no
need for explicitly unmasking the first level irq in this
driver. This patches removes this level 1 irq unmask support.

Signed-off-by: Kuppuswamy Sathyanarayanan 

Reviewed-by: Darren Hart (VMware) 
Reviewed-by: Andy Shevchenko 
---
 drivers/platform/x86/intel_bxtwc_tmu.c | 4 
 1 file changed, 4 deletions(-)

Changes since v1:
 * None

Changes since v2:
 * Rebased on top of latest release.

Changes since v3:
 * None

diff --git a/drivers/platform/x86/intel_bxtwc_tmu.c 
b/drivers/platform/x86/intel_bxtwc_tmu.c
index e202abd..ea865d4 100644
--- a/drivers/platform/x86/intel_bxtwc_tmu.c
+++ b/drivers/platform/x86/intel_bxtwc_tmu.c
@@ -92,10 +92,6 @@ static int bxt_wcove_tmu_probe(struct platform_device *pdev)
}
wctmu->irq = virq;
 
-   /* Enable TMU interrupts */
-   regmap_update_bits(wctmu->regmap, BXTWC_MIRQLVL1,
- BXTWC_MIRQLVL1_MTMU, 0);
-
/* Unmask TMU second level Wake & System alarm */
regmap_update_bits(wctmu->regmap, BXTWC_MTMUIRQ_REG,
  BXTWC_TMU_ALRM_MASK, 0);
-- 
2.7.4

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[PATCH v4 4/9] mfd: intel_soc_pmic_bxtwc: remove second level irq for gpio device

[sathyanarayanan . kuppuswamy]

From: Kuppuswamy Sathyanarayanan 

Currently all PMIC GPIO domain irqs are consumed by the same
device(bxt_wcove_gpio), so there is no need to export them as
separate interrupts. We can just export only the first level
GPIO irq(BXTWC_GPIO_LVL1_IRQ) as an irq resource and let the
GPIO device driver(bxt_wcove_gpio) handle the GPIO sub domain
irqs based on status value of GPIO level2 interrupt status
register. Also, just using only the first level irq will eliminate
the bug involved in requesting only the second level irq and not
explicitly enable the first level irq. For more info on this
issue please read the details at,

https://lkml.org/lkml/2017/2/27/148

Signed-off-by: Kuppuswamy Sathyanarayanan 

Acked-for-MFD-by: Lee Jones 
---
 drivers/mfd/intel_soc_pmic_bxtwc.c | 7 +--
 1 file changed, 1 insertion(+), 6 deletions(-)

Changes since v1:
 * None

Changes since v2: 
 * Rebased on top of latest release.

Changes since v3:
 * None

diff --git a/drivers/mfd/intel_soc_pmic_bxtwc.c 
b/drivers/mfd/intel_soc_pmic_bxtwc.c
index 7c1ed27..af11c43 100644
--- a/drivers/mfd/intel_soc_pmic_bxtwc.c
+++ b/drivers/mfd/intel_soc_pmic_bxtwc.c
@@ -89,8 +89,6 @@ enum bxtwc_irqs_level2 {
BXTWC_USBC_IRQ,
BXTWC_CHGR0_IRQ,
BXTWC_CHGR1_IRQ,
-   BXTWC_GPIO0_IRQ,
-   BXTWC_GPIO1_IRQ,
BXTWC_CRIT_IRQ,
 };
 
@@ -116,8 +114,6 @@ static const struct regmap_irq bxtwc_regmap_irqs_level2[] = 
{
REGMAP_IRQ_REG(BXTWC_USBC_IRQ, 2, BIT(5)),
REGMAP_IRQ_REG(BXTWC_CHGR0_IRQ, 2, 0x1f),
REGMAP_IRQ_REG(BXTWC_CHGR1_IRQ, 3, 0x1f),
-   REGMAP_IRQ_REG(BXTWC_GPIO0_IRQ, 4, 0xff),
-   REGMAP_IRQ_REG(BXTWC_GPIO1_IRQ, 5, 0x3f),
REGMAP_IRQ_REG(BXTWC_CRIT_IRQ, 6, 0x03),
 };
 
@@ -153,8 +149,7 @@ static struct regmap_irq_chip bxtwc_regmap_irq_chip_tmu = {
 };
 
 static struct resource gpio_resources[] = {
-   DEFINE_RES_IRQ_NAMED(BXTWC_GPIO0_IRQ, "GPIO0"),
-   DEFINE_RES_IRQ_NAMED(BXTWC_GPIO1_IRQ, "GPIO1"),
+   DEFINE_RES_IRQ_NAMED(BXTWC_GPIO_LVL1_IRQ, "GPIO"),
 };
 
 static struct resource adc_resources[] = {
-- 
2.7.4

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