Re: [PATCH 36/39] dmaengine: ste_dma40: Allow memcpy channels to be configured from DT

2013-05-30 Thread Linus Walleij 
On Wed, May 15, 2013 at 11:51 AM, Lee Jones lee.jo...@linaro.org wrote:

 At this moment in time the memcpy channels which can be used by the D40
 are fixed, as each supported platform in Mainline uses the same ones.
 However, platforms do exist which don't follow this convention, so
 these will need to be tailored. Fortunately, these platforms will be DT
 only, so this change has very little impact on platform data.

 Cc: Vinod Koul vinod.k...@intel.com
 Cc: Dan Williams d...@fb.com
 Cc: Per Forlin per.for...@stericsson.com
 Cc: Rabin Vincent ra...@rab.in
 Acked-by: Arnd Bergmann a...@arndb.de
 Signed-off-by: Lee Jones lee.jo...@linaro.org

Patch applied with Vinod's ACK.

Yours,
Linus Walleij
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[PATCH 36/39] dmaengine: ste_dma40: Allow memcpy channels to be configured from DT

2013-05-15 Thread Lee Jones 
At this moment in time the memcpy channels which can be used by the D40
are fixed, as each supported platform in Mainline uses the same ones.
However, platforms do exist which don't follow this convention, so
these will need to be tailored. Fortunately, these platforms will be DT
only, so this change has very little impact on platform data.

Cc: Vinod Koul vinod.k...@intel.com
Cc: Dan Williams d...@fb.com
Cc: Per Forlin per.for...@stericsson.com
Cc: Rabin Vincent ra...@rab.in
Acked-by: Arnd Bergmann a...@arndb.de
Signed-off-by: Lee Jones lee.jo...@linaro.org
---
 .../devicetree/bindings/dma/ste-dma40.txt  |2 +
 drivers/dma/ste_dma40.c|   40 
 include/linux/platform_data/dma-ste-dma40.h|2 +
 3 files changed, 36 insertions(+), 8 deletions(-)

diff --git a/Documentation/devicetree/bindings/dma/ste-dma40.txt 
b/Documentation/devicetree/bindings/dma/ste-dma40.txt
index 2679a87..aa272d8 100644
--- a/Documentation/devicetree/bindings/dma/ste-dma40.txt
+++ b/Documentation/devicetree/bindings/dma/ste-dma40.txt
@@ -6,6 +6,7 @@ Required properties:
 - reg-names: Names of the above areas to use during resource look-up
 - interrupt: Should contain the DMAC interrupt number
 - #dma-cells: must be 3
+- memcpy-channels: Channels to be used for memcpy
 
 Optional properties:
 - dma-channels: Number of channels supported by hardware - if not present
@@ -21,6 +22,7 @@ Example:
interrupts = 0 25 0x4;
 
#dma-cells = 2;
+   memcpy-channels  = 56 57 58 59 60;
dma-channels = 8;
};
 
diff --git a/drivers/dma/ste_dma40.c b/drivers/dma/ste_dma40.c
index 76c255f..ae462d3 100644
--- a/drivers/dma/ste_dma40.c
+++ b/drivers/dma/ste_dma40.c
@@ -58,6 +58,8 @@
 #define D40_ALLOC_PHY  BIT(30)
 #define D40_ALLOC_LOG_FREE 0
 
+#define D40_MEMCPY_MAX_CHANS   8
+
 /* Reserved event lines for memcpy only. */
 #define DB8500_DMA_MEMCPY_EV_0 51
 #define DB8500_DMA_MEMCPY_EV_1 56
@@ -522,6 +524,8 @@ struct d40_gen_dmac {
  * @phy_start: Physical memory start of the DMA registers.
  * @phy_size: Size of the DMA register map.
  * @irq: The IRQ number.
+ * @num_memcpy_chans: The number of channels used for memcpy (mem-to-mem
+ * transfers).
  * @num_phy_chans: The number of physical channels. Read from HW. This
  * is the number of available channels for this driver, not counting Secure
  * mode allocated physical channels.
@@ -565,6 +569,7 @@ struct d40_base {
phys_addr_t   phy_start;
resource_size_t   phy_size;
int   irq;
+   int   num_memcpy_chans;
int   num_phy_chans;
int   num_log_chans;
struct device_dma_parameters  dma_parms;
@@ -2938,7 +2943,7 @@ static int __init d40_dmaengine_init(struct d40_base 
*base,
}
 
d40_chan_init(base, base-dma_memcpy, base-log_chans,
- base-num_log_chans, ARRAY_SIZE(dma40_memcpy_channels));
+ base-num_log_chans, base-num_memcpy_chans);
 
dma_cap_zero(base-dma_memcpy.cap_mask);
dma_cap_set(DMA_MEMCPY, base-dma_memcpy.cap_mask);
@@ -3139,6 +3144,7 @@ static struct d40_base * __init d40_hw_detect_init(struct 
platform_device *pdev)
struct d40_base *base = NULL;
int num_log_chans = 0;
int num_phy_chans;
+   int num_memcpy_chans;
int clk_ret = -EINVAL;
int i;
u32 pid;
@@ -3209,6 +3215,12 @@ static struct d40_base * __init 
d40_hw_detect_init(struct platform_device *pdev)
else
num_phy_chans = 4 * (readl(virtbase + D40_DREG_ICFG)  0x7) + 4;
 
+   /* The number of channels used for memcpy */
+   if (plat_data-num_of_memcpy_chans)
+   num_memcpy_chans = plat_data-num_of_memcpy_chans;
+   else
+   num_memcpy_chans = ARRAY_SIZE(dma40_memcpy_channels);
+
num_log_chans = num_phy_chans * D40_MAX_LOG_CHAN_PER_PHY;
 
dev_info(pdev-dev,
@@ -3216,7 +3228,7 @@ static struct d40_base * __init d40_hw_detect_init(struct 
platform_device *pdev)
 rev, res-start, num_phy_chans, num_log_chans);
 
base = kzalloc(ALIGN(sizeof(struct d40_base), 4) +
-  (num_phy_chans + num_log_chans + 
ARRAY_SIZE(dma40_memcpy_channels)) *
+  (num_phy_chans + num_log_chans + num_memcpy_chans) *
   sizeof(struct d40_chan), GFP_KERNEL);
 
if (base == NULL) {
@@ -3226,6 +3238,7 @@ static struct d40_base * __init d40_hw_detect_init(struct 
platform_device *pdev)
 
base-rev = rev;
base-clk = clk;
+   base-num_memcpy_chans = num_memcpy_chans;
base-num_phy_chans = num_phy_chans;
base-num_log_chans = num_log_chans;
base-phy_start = res-start;
@@ -3469,12 +3482,8 @@ static int __init

Re: [PATCH 36/39] dmaengine: ste_dma40: Allow memcpy channels to be configured from DT

2013-05-15 Thread Vinod Koul 
On Wed, May 15, 2013 at 10:51:59AM +0100, Lee Jones wrote:
 At this moment in time the memcpy channels which can be used by the D40
 are fixed, as each supported platform in Mainline uses the same ones.
 However, platforms do exist which don't follow this convention, so
 these will need to be tailored. Fortunately, these platforms will be DT
 only, so this change has very little impact on platform data.
 
 Cc: Vinod Koul vinod.k...@intel.com
 Cc: Dan Williams d...@fb.com
 Cc: Per Forlin per.for...@stericsson.com
 Cc: Rabin Vincent ra...@rab.in
 Acked-by: Arnd Bergmann a...@arndb.de
 Signed-off-by: Lee Jones lee.jo...@linaro.org
Acked-by: Vinod Koul vinod.k...@intel.com

 ---
  .../devicetree/bindings/dma/ste-dma40.txt  |2 +
  drivers/dma/ste_dma40.c|   40 
 
  include/linux/platform_data/dma-ste-dma40.h|2 +
  3 files changed, 36 insertions(+), 8 deletions(-)
 
 diff --git a/Documentation/devicetree/bindings/dma/ste-dma40.txt 
 b/Documentation/devicetree/bindings/dma/ste-dma40.txt
 index 2679a87..aa272d8 100644
 --- a/Documentation/devicetree/bindings/dma/ste-dma40.txt
 +++ b/Documentation/devicetree/bindings/dma/ste-dma40.txt
 @@ -6,6 +6,7 @@ Required properties:
  - reg-names: Names of the above areas to use during resource look-up
  - interrupt: Should contain the DMAC interrupt number
  - #dma-cells: must be 3
 +- memcpy-channels: Channels to be used for memcpy
  
  Optional properties:
  - dma-channels: Number of channels supported by hardware - if not present
 @@ -21,6 +22,7 @@ Example:
   interrupts = 0 25 0x4;
  
   #dma-cells = 2;
 + memcpy-channels  = 56 57 58 59 60;
   dma-channels = 8;
   };
  
 diff --git a/drivers/dma/ste_dma40.c b/drivers/dma/ste_dma40.c
 index 76c255f..ae462d3 100644
 --- a/drivers/dma/ste_dma40.c
 +++ b/drivers/dma/ste_dma40.c
 @@ -58,6 +58,8 @@
  #define D40_ALLOC_PHYBIT(30)
  #define D40_ALLOC_LOG_FREE   0
  
 +#define D40_MEMCPY_MAX_CHANS 8
 +
  /* Reserved event lines for memcpy only. */
  #define DB8500_DMA_MEMCPY_EV_0   51
  #define DB8500_DMA_MEMCPY_EV_1   56
 @@ -522,6 +524,8 @@ struct d40_gen_dmac {
   * @phy_start: Physical memory start of the DMA registers.
   * @phy_size: Size of the DMA register map.
   * @irq: The IRQ number.
 + * @num_memcpy_chans: The number of channels used for memcpy (mem-to-mem
 + * transfers).
   * @num_phy_chans: The number of physical channels. Read from HW. This
   * is the number of available channels for this driver, not counting Secure
   * mode allocated physical channels.
 @@ -565,6 +569,7 @@ struct d40_base {
   phys_addr_t   phy_start;
   resource_size_t   phy_size;
   int   irq;
 + int   num_memcpy_chans;
   int   num_phy_chans;
   int   num_log_chans;
   struct device_dma_parameters  dma_parms;
 @@ -2938,7 +2943,7 @@ static int __init d40_dmaengine_init(struct d40_base 
 *base,
   }
  
   d40_chan_init(base, base-dma_memcpy, base-log_chans,
 -   base-num_log_chans, ARRAY_SIZE(dma40_memcpy_channels));
 +   base-num_log_chans, base-num_memcpy_chans);
  
   dma_cap_zero(base-dma_memcpy.cap_mask);
   dma_cap_set(DMA_MEMCPY, base-dma_memcpy.cap_mask);
 @@ -3139,6 +3144,7 @@ static struct d40_base * __init 
 d40_hw_detect_init(struct platform_device *pdev)
   struct d40_base *base = NULL;
   int num_log_chans = 0;
   int num_phy_chans;
 + int num_memcpy_chans;
   int clk_ret = -EINVAL;
   int i;
   u32 pid;
 @@ -3209,6 +3215,12 @@ static struct d40_base * __init 
 d40_hw_detect_init(struct platform_device *pdev)
   else
   num_phy_chans = 4 * (readl(virtbase + D40_DREG_ICFG)  0x7) + 4;
  
 + /* The number of channels used for memcpy */
 + if (plat_data-num_of_memcpy_chans)
 + num_memcpy_chans = plat_data-num_of_memcpy_chans;
 + else
 + num_memcpy_chans = ARRAY_SIZE(dma40_memcpy_channels);
 +
   num_log_chans = num_phy_chans * D40_MAX_LOG_CHAN_PER_PHY;
  
   dev_info(pdev-dev,
 @@ -3216,7 +3228,7 @@ static struct d40_base * __init 
 d40_hw_detect_init(struct platform_device *pdev)
rev, res-start, num_phy_chans, num_log_chans);
  
   base = kzalloc(ALIGN(sizeof(struct d40_base), 4) +
 -(num_phy_chans + num_log_chans + 
 ARRAY_SIZE(dma40_memcpy_channels)) *
 +(num_phy_chans + num_log_chans + num_memcpy_chans) *
  sizeof(struct d40_chan), GFP_KERNEL);
  
   if (base == NULL) {
 @@ -3226,6 +3238,7 @@ static struct d40_base * __init 
 d40_hw_detect_init(struct platform_device *pdev)
  
   base-rev = rev;
   base-clk = clk;
 + base-num_memcpy_chans = num_memcpy_chans;