Re: [PATCH v2 1/5] dt-bindings: Add usb3.0 phy binding for MT65xx SoCs

2015-07-15 Thread chunfeng yun 
On Tue, 2015-07-14 at 09:45 +0200, Sascha Hauer wrote:
 On Tue, Jul 14, 2015 at 02:19:51PM +0800, chunfeng yun wrote:
  hi,
  On Fri, 2015-07-10 at 07:10 +0200, Sascha Hauer wrote:
   On Wed, Jul 08, 2015 at 05:41:03PM +0800, Chunfeng Yun wrote:
add a DT binding documentation of usb3.0 phy for MT65xx
SoCs from Mediatek.

Signed-off-by: Chunfeng Yun chunfeng@mediatek.com
---
 .../devicetree/bindings/usb/mt65xx-u3phy.txt   | 34 
++
 1 file changed, 34 insertions(+)
 create mode 100644 
Documentation/devicetree/bindings/usb/mt65xx-u3phy.txt

diff --git a/Documentation/devicetree/bindings/usb/mt65xx-u3phy.txt 
b/Documentation/devicetree/bindings/usb/mt65xx-u3phy.txt
new file mode 100644
index 000..056b2aa
--- /dev/null
+++ b/Documentation/devicetree/bindings/usb/mt65xx-u3phy.txt
@@ -0,0 +1,34 @@
+MT65xx U3PHY
+
+The device node for Mediatek SOC usb3.0 phy
+
+Required properties:
+ - compatible : Should be mediatek,mt8173-u3phy
+ - reg: Offset and length of registers, the first is for mac 
domain,
+   another for phy domain
+ - power-domains: to enable usb's mtcmos
+ - usb-wakeup-ctrl : to access usb wakeup control register
+ - wakeup-src : 1: ip sleep wakeup mode; 2: line state wakeup mode; 
others
+   means don't enable wakeup source of usb
+ - u2port-num : number of usb2.0 ports to support which should be 1 or 
2
+ - clocks : must support all clocks that phy need
+ - clock-names: should be wakeup_deb_p0, wakeup_deb_p1 for wakeup
+   debounce control clocks, and u3phya_ref for u3phya reference 
clock.
+
+Example:
+
+u3phy: usb-phy@11271000 {
+   compatible = mediatek,mt8173-u3phy;
+   reg = 0 0x11271000 0 0x3000,
+ 0 0x1128 0 0x2;
   
   0x11271000 is the register space the xhci controller takes. You should
   not expose the same register space to two different drivers.
   
  
  usb: usb30@1127 {
 compatible = mediatek,mt8173-xhci;
 reg = 0 0x1127 0 0x1000;
  
  the size of xhci register space is 0x1000, and the range is
  [0x1127, 0x11271000 - 1], so the address of 0x11271000 is not
  included.
 
 Indeed, you are right. Nevertheless my datasheet lists these resources:
 
 0x1127 - 0x1127: SSUSB CSR
 0x1128 - 0x1128: SSUSB SIF
 0x1129 - 0x1129: SSUSB
 
 It seems that with the current binding you are not modelling the
 hardware but something that reflects your current implementation. This
 is not a good sign. Normally I would expect device nodes that match the
 above resources, but your USB phy spans most of the SSUSB CSR register
 space and both the SSUSB SIF and SSUSB regster space. I think it would
 be good if you could give an overview over the USB hardware and explain
 why you have to violate the above resources.
 
 Also something to consider: Is your binding suitable for adding OTG
 support later? You don't have to add OTG support to the Kernel now,
 but your binding should be suitable to add it later.
 
 Sascha
 

I agree with you, but timing parameter settings of super speed port are
put in [0x11272400 - 0x11272800], which is not included by xhci register
space. SSUSB SIF includes some control and status registers of each
ports and also OTG etc. It is better to put them into the node of gadget
device node which is not supported now, so put them into phy device
node.

Do you have any good idea to deal with the special case?


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Re: [PATCH v2 1/5] dt-bindings: Add usb3.0 phy binding for MT65xx SoCs

2015-07-14 Thread Sascha Hauer 
On Tue, Jul 14, 2015 at 02:19:51PM +0800, chunfeng yun wrote:
 hi,
 On Fri, 2015-07-10 at 07:10 +0200, Sascha Hauer wrote:
  On Wed, Jul 08, 2015 at 05:41:03PM +0800, Chunfeng Yun wrote:
   add a DT binding documentation of usb3.0 phy for MT65xx
   SoCs from Mediatek.
   
   Signed-off-by: Chunfeng Yun chunfeng@mediatek.com
   ---
.../devicetree/bindings/usb/mt65xx-u3phy.txt   | 34 
   ++
1 file changed, 34 insertions(+)
create mode 100644 Documentation/devicetree/bindings/usb/mt65xx-u3phy.txt
   
   diff --git a/Documentation/devicetree/bindings/usb/mt65xx-u3phy.txt 
   b/Documentation/devicetree/bindings/usb/mt65xx-u3phy.txt
   new file mode 100644
   index 000..056b2aa
   --- /dev/null
   +++ b/Documentation/devicetree/bindings/usb/mt65xx-u3phy.txt
   @@ -0,0 +1,34 @@
   +MT65xx U3PHY
   +
   +The device node for Mediatek SOC usb3.0 phy
   +
   +Required properties:
   + - compatible : Should be mediatek,mt8173-u3phy
   + - reg: Offset and length of registers, the first is for mac 
   domain,
   + another for phy domain
   + - power-domains: to enable usb's mtcmos
   + - usb-wakeup-ctrl : to access usb wakeup control register
   + - wakeup-src : 1: ip sleep wakeup mode; 2: line state wakeup mode; 
   others
   + means don't enable wakeup source of usb
   + - u2port-num : number of usb2.0 ports to support which should be 1 or 2
   + - clocks : must support all clocks that phy need
   + - clock-names: should be wakeup_deb_p0, wakeup_deb_p1 for wakeup
   + debounce control clocks, and u3phya_ref for u3phya reference clock.
   +
   +Example:
   +
   +u3phy: usb-phy@11271000 {
   + compatible = mediatek,mt8173-u3phy;
   + reg = 0 0x11271000 0 0x3000,
   +   0 0x1128 0 0x2;
  
  0x11271000 is the register space the xhci controller takes. You should
  not expose the same register space to two different drivers.
  
 
 usb: usb30@1127 {
compatible = mediatek,mt8173-xhci;
reg = 0 0x1127 0 0x1000;
 
 the size of xhci register space is 0x1000, and the range is
 [0x1127, 0x11271000 - 1], so the address of 0x11271000 is not
 included.

Indeed, you are right. Nevertheless my datasheet lists these resources:

0x1127 - 0x1127: SSUSB CSR
0x1128 - 0x1128: SSUSB SIF
0x1129 - 0x1129: SSUSB

It seems that with the current binding you are not modelling the
hardware but something that reflects your current implementation. This
is not a good sign. Normally I would expect device nodes that match the
above resources, but your USB phy spans most of the SSUSB CSR register
space and both the SSUSB SIF and SSUSB regster space. I think it would
be good if you could give an overview over the USB hardware and explain
why you have to violate the above resources.

Also something to consider: Is your binding suitable for adding OTG
support later? You don't have to add OTG support to the Kernel now,
but your binding should be suitable to add it later.

Sascha

-- 
Pengutronix e.K.   | |
Industrial Linux Solutions | http://www.pengutronix.de/  |
Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0|
Amtsgericht Hildesheim, HRA 2686   | Fax:   +49-5121-206917- |
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Re: [PATCH v2 1/5] dt-bindings: Add usb3.0 phy binding for MT65xx SoCs

2015-07-14 Thread chunfeng yun 
hi,
On Fri, 2015-07-10 at 07:10 +0200, Sascha Hauer wrote:
 On Wed, Jul 08, 2015 at 05:41:03PM +0800, Chunfeng Yun wrote:
  add a DT binding documentation of usb3.0 phy for MT65xx
  SoCs from Mediatek.
  
  Signed-off-by: Chunfeng Yun chunfeng@mediatek.com
  ---
   .../devicetree/bindings/usb/mt65xx-u3phy.txt   | 34 
  ++
   1 file changed, 34 insertions(+)
   create mode 100644 Documentation/devicetree/bindings/usb/mt65xx-u3phy.txt
  
  diff --git a/Documentation/devicetree/bindings/usb/mt65xx-u3phy.txt 
  b/Documentation/devicetree/bindings/usb/mt65xx-u3phy.txt
  new file mode 100644
  index 000..056b2aa
  --- /dev/null
  +++ b/Documentation/devicetree/bindings/usb/mt65xx-u3phy.txt
  @@ -0,0 +1,34 @@
  +MT65xx U3PHY
  +
  +The device node for Mediatek SOC usb3.0 phy
  +
  +Required properties:
  + - compatible : Should be mediatek,mt8173-u3phy
  + - reg: Offset and length of registers, the first is for mac 
  domain,
  +   another for phy domain
  + - power-domains: to enable usb's mtcmos
  + - usb-wakeup-ctrl : to access usb wakeup control register
  + - wakeup-src : 1: ip sleep wakeup mode; 2: line state wakeup mode; others
  +   means don't enable wakeup source of usb
  + - u2port-num : number of usb2.0 ports to support which should be 1 or 2
  + - clocks : must support all clocks that phy need
  + - clock-names: should be wakeup_deb_p0, wakeup_deb_p1 for wakeup
  +   debounce control clocks, and u3phya_ref for u3phya reference clock.
  +
  +Example:
  +
  +u3phy: usb-phy@11271000 {
  +   compatible = mediatek,mt8173-u3phy;
  +   reg = 0 0x11271000 0 0x3000,
  + 0 0x1128 0 0x2;
 
 0x11271000 is the register space the xhci controller takes. You should
 not expose the same register space to two different drivers.
 

usb: usb30@1127 {
   compatible = mediatek,mt8173-xhci;
   reg = 0 0x1127 0 0x1000;

the size of xhci register space is 0x1000, and the range is
[0x1127, 0x11271000 - 1], so the address of 0x11271000 is not
included.

 Sascha
 


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Re: [PATCH v2 1/5] dt-bindings: Add usb3.0 phy binding for MT65xx SoCs

2015-07-09 Thread Sascha Hauer 
On Wed, Jul 08, 2015 at 05:41:03PM +0800, Chunfeng Yun wrote:
 add a DT binding documentation of usb3.0 phy for MT65xx
 SoCs from Mediatek.
 
 Signed-off-by: Chunfeng Yun chunfeng@mediatek.com
 ---
  .../devicetree/bindings/usb/mt65xx-u3phy.txt   | 34 
 ++
  1 file changed, 34 insertions(+)
  create mode 100644 Documentation/devicetree/bindings/usb/mt65xx-u3phy.txt
 
 diff --git a/Documentation/devicetree/bindings/usb/mt65xx-u3phy.txt 
 b/Documentation/devicetree/bindings/usb/mt65xx-u3phy.txt
 new file mode 100644
 index 000..056b2aa
 --- /dev/null
 +++ b/Documentation/devicetree/bindings/usb/mt65xx-u3phy.txt
 @@ -0,0 +1,34 @@
 +MT65xx U3PHY
 +
 +The device node for Mediatek SOC usb3.0 phy
 +
 +Required properties:
 + - compatible : Should be mediatek,mt8173-u3phy
 + - reg: Offset and length of registers, the first is for mac domain,
 + another for phy domain
 + - power-domains: to enable usb's mtcmos
 + - usb-wakeup-ctrl : to access usb wakeup control register
 + - wakeup-src : 1: ip sleep wakeup mode; 2: line state wakeup mode; others
 + means don't enable wakeup source of usb
 + - u2port-num : number of usb2.0 ports to support which should be 1 or 2
 + - clocks : must support all clocks that phy need
 + - clock-names: should be wakeup_deb_p0, wakeup_deb_p1 for wakeup
 + debounce control clocks, and u3phya_ref for u3phya reference clock.
 +
 +Example:
 +
 +u3phy: usb-phy@11271000 {
 + compatible = mediatek,mt8173-u3phy;
 + reg = 0 0x11271000 0 0x3000,
 +   0 0x1128 0 0x2;

0x11271000 is the register space the xhci controller takes. You should
not expose the same register space to two different drivers.

Sascha

-- 
Pengutronix e.K.   | |
Industrial Linux Solutions | http://www.pengutronix.de/  |
Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0|
Amtsgericht Hildesheim, HRA 2686   | Fax:   +49-5121-206917- |
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[PATCH v2 1/5] dt-bindings: Add usb3.0 phy binding for MT65xx SoCs

2015-07-08 Thread Chunfeng Yun 
add a DT binding documentation of usb3.0 phy for MT65xx
SoCs from Mediatek.

Signed-off-by: Chunfeng Yun chunfeng@mediatek.com
---
 .../devicetree/bindings/usb/mt65xx-u3phy.txt   | 34 ++
 1 file changed, 34 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/usb/mt65xx-u3phy.txt

diff --git a/Documentation/devicetree/bindings/usb/mt65xx-u3phy.txt 
b/Documentation/devicetree/bindings/usb/mt65xx-u3phy.txt
new file mode 100644
index 000..056b2aa
--- /dev/null
+++ b/Documentation/devicetree/bindings/usb/mt65xx-u3phy.txt
@@ -0,0 +1,34 @@
+MT65xx U3PHY
+
+The device node for Mediatek SOC usb3.0 phy
+
+Required properties:
+ - compatible : Should be mediatek,mt8173-u3phy
+ - reg: Offset and length of registers, the first is for mac domain,
+   another for phy domain
+ - power-domains: to enable usb's mtcmos
+ - usb-wakeup-ctrl : to access usb wakeup control register
+ - wakeup-src : 1: ip sleep wakeup mode; 2: line state wakeup mode; others
+   means don't enable wakeup source of usb
+ - u2port-num : number of usb2.0 ports to support which should be 1 or 2
+ - clocks : must support all clocks that phy need
+ - clock-names: should be wakeup_deb_p0, wakeup_deb_p1 for wakeup
+   debounce control clocks, and u3phya_ref for u3phya reference clock.
+
+Example:
+
+u3phy: usb-phy@11271000 {
+   compatible = mediatek,mt8173-u3phy;
+   reg = 0 0x11271000 0 0x3000,
+ 0 0x1128 0 0x2;
+   power-domains = scpsys MT8173_POWER_DOMAIN_USB;
+   usb-wakeup-ctrl = pericfg;
+   wakeup-src = 1;
+   u2port-num = 2;
+   clocks = perisys PERI_USB0,
+perisys PERI_USB1,
+apmixedsys CLK_APMIXED_REF2USB_TX;
+   clock-names = wakeup_deb_p0,
+ wakeup_deb_p1,
+ u3phya_ref;
+};
-- 
1.8.1.1.dirty

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