Re: [PATCH v2 3/6] phy: meson: add USB2 PHY support for Meson8b and GXBB

[Kishon Vijay Abraham I]

On Monday 19 September 2016 10:12 PM, Kevin Hilman wrote:
> Kishon Vijay Abraham I  writes:
> 
>> Hi Kevin,
>>
>> On Wednesday 14 September 2016 09:36 PM, Kevin Hilman wrote:
>>> Kishon,
>>>
>>> Martin Blumenstingl  writes:
>>>
 This is a new driver for the USB PHY found in Meson8b and GXBB SoCs.

 Signed-off-by: Martin Blumenstingl 
 Signed-off-by: Jerome Brunet 
 Tested-by: Kevin Hilman 
>>>
>>> Will you be picking this up for v4.9?
>>
>> It's already late for 4.9. Generally send pull request to Greg around -rc6.
>> This can go only in 4.10.
> 
> That's fine.
> 
> Does that mean you have it queued someplace?  I don't see it in any of
> your branches.

I haven't queued so far. I'll create a testing branch to queue pending patches.

Thanks
Kishon
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Re: [PATCH v2 3/6] phy: meson: add USB2 PHY support for Meson8b and GXBB

[Kevin Hilman]

Kishon Vijay Abraham I  writes:

> Hi Kevin,
>
> On Wednesday 14 September 2016 09:36 PM, Kevin Hilman wrote:
>> Kishon,
>> 
>> Martin Blumenstingl  writes:
>> 
>>> This is a new driver for the USB PHY found in Meson8b and GXBB SoCs.
>>>
>>> Signed-off-by: Martin Blumenstingl 
>>> Signed-off-by: Jerome Brunet 
>>> Tested-by: Kevin Hilman 
>> 
>> Will you be picking this up for v4.9?
>
> It's already late for 4.9. Generally send pull request to Greg around -rc6.
> This can go only in 4.10.

That's fine.

Does that mean you have it queued someplace?  I don't see it in any of
your branches.

Kevin
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Re: [PATCH v2 3/6] phy: meson: add USB2 PHY support for Meson8b and GXBB

[Kishon Vijay Abraham I]

Hi Kevin,

On Wednesday 14 September 2016 09:36 PM, Kevin Hilman wrote:
> Kishon,
> 
> Martin Blumenstingl  writes:
> 
>> This is a new driver for the USB PHY found in Meson8b and GXBB SoCs.
>>
>> Signed-off-by: Martin Blumenstingl 
>> Signed-off-by: Jerome Brunet 
>> Tested-by: Kevin Hilman 
> 
> Will you be picking this up for v4.9?

It's already late for 4.9. Generally send pull request to Greg around -rc6.
This can go only in 4.10.

Thanks
Kishon

> 
> Kevin
> 
>> ---
>>  drivers/phy/Kconfig  |  11 ++
>>  drivers/phy/Makefile |   1 +
>>  drivers/phy/phy-meson-usb2.c | 280 
>> +++
>>  3 files changed, 292 insertions(+)
>>  create mode 100644 drivers/phy/phy-meson-usb2.c
>>
>> diff --git a/drivers/phy/Kconfig b/drivers/phy/Kconfig
>> index 19bff3a..6ad87ec 100644
>> --- a/drivers/phy/Kconfig
>> +++ b/drivers/phy/Kconfig
>> @@ -453,4 +453,15 @@ config PHY_NS2_PCIE
>>  help
>>Enable this to support the Broadcom Northstar2 PCIe PHY.
>>If unsure, say N.
>> +
>> +config PHY_MESON_USB2
>> +tristate "Meson USB2 PHY driver"
>> +default ARCH_MESON
>> +depends on OF && (ARCH_MESON || COMPILE_TEST)
>> +select GENERIC_PHY
>> +help
>> +  Enable this to support the Meson USB2 PHYs found in Meson8b
>> +  and GXBB SoCs.
>> +  If unsure, say N.
>> +
>>  endmenu
>> diff --git a/drivers/phy/Makefile b/drivers/phy/Makefile
>> index 90ae198..dd507ac 100644
>> --- a/drivers/phy/Makefile
>> +++ b/drivers/phy/Makefile
>> @@ -56,3 +56,4 @@ obj-$(CONFIG_PHY_PISTACHIO_USB)+= 
>> phy-pistachio-usb.o
>>  obj-$(CONFIG_PHY_CYGNUS_PCIE)   += phy-bcm-cygnus-pcie.o
>>  obj-$(CONFIG_ARCH_TEGRA) += tegra/
>>  obj-$(CONFIG_PHY_NS2_PCIE)  += phy-bcm-ns2-pcie.o
>> +obj-$(CONFIG_PHY_MESON_USB2)+= phy-meson-usb2.o
>> diff --git a/drivers/phy/phy-meson-usb2.c b/drivers/phy/phy-meson-usb2.c
>> new file mode 100644
>> index 000..eece521
>> --- /dev/null
>> +++ b/drivers/phy/phy-meson-usb2.c
>> @@ -0,0 +1,280 @@
>> +/*
>> + * Meson USB2 PHY driver
>> + *
>> + * Copyright (C) 2016 Martin Blumenstingl 
>> 
>> + *
>> + * This program is free software; you can redistribute it and/or modify
>> + * it under the terms of the GNU General Public License version 2 as
>> + * published by the Free Software Foundation.
>> + *
>> + * You should have received a copy of the GNU General Public License
>> + * along with this program. If not, see .
>> + */
>> +
>> +#include 
>> +#include 
>> +#include 
>> +#include 
>> +#include 
>> +#include 
>> +#include 
>> +#include 
>> +#include 
>> +
>> +#define REG_CONFIG  0x00
>> +#define REG_CONFIG_CLK_EN   BIT(0)
>> +#define REG_CONFIG_CLK_SEL_MASK GENMASK(3, 1)
>> +#define REG_CONFIG_CLK_DIV_MASK GENMASK(10, 4)
>> +#define REG_CONFIG_CLK_32k_ALTSEL   BIT(15)
>> +#define REG_CONFIG_TEST_TRIGBIT(31)
>> +
>> +#define REG_CTRL0x04
>> +#define REG_CTRL_SOFT_PRST  BIT(0)
>> +#define REG_CTRL_SOFT_HRESETBIT(1)
>> +#define REG_CTRL_SS_SCALEDOWN_MODE_MASK GENMASK(3, 2)
>> +#define REG_CTRL_CLK_DET_RSTBIT(4)
>> +#define REG_CTRL_INTR_SEL   BIT(5)
>> +#define REG_CTRL_CLK_DETECTED   BIT(8)
>> +#define REG_CTRL_SOF_SENT_RCVD_TGL  BIT(9)
>> +#define REG_CTRL_SOF_TOGGLE_OUT BIT(10)
>> +#define REG_CTRL_POWER_ON_RESET BIT(15)
>> +#define REG_CTRL_SLEEPM BIT(16)
>> +#define REG_CTRL_TX_BITSTUFF_ENN_H  BIT(17)
>> +#define REG_CTRL_TX_BITSTUFF_ENNBIT(18)
>> +#define REG_CTRL_COMMON_ON  BIT(19)
>> +#define REG_CTRL_REF_CLK_SEL_MASK   GENMASK(21, 20)
>> +#define REG_CTRL_REF_CLK_SEL_SHIFT  20
>> +#define REG_CTRL_FSEL_MASK  GENMASK(24, 22)
>> +#define REG_CTRL_FSEL_SHIFT 22
>> +#define REG_CTRL_PORT_RESET BIT(25)
>> +#define REG_CTRL_THREAD_ID_MASK GENMASK(31, 26)
>> +
>> +#define REG_ENDP_INTR   0x08
>> +
>> +/* bits [31:26], [24:21] and [15:3] seem to be read-only */
>> +#define REG_ADP_BC  0x0c
>> +#define REG_ADP_BC_VBUS_VLD_EXT_SEL BIT(0)
>> +#define REG_ADP_BC_VBUS_VLD_EXT BIT(1)
>> +#define REG_ADP_BC_OTG_DISABLE  BIT(2)
>> +#define REG_ADP_BC_ID_PULLUPBIT(3)
>> +#define REG_ADP_BC_DRV_VBUS

Re: [PATCH v2 3/6] phy: meson: add USB2 PHY support for Meson8b and GXBB

[Martin Blumenstingl]

On Sun, Sep 11, 2016 at 3:41 PM, Martin Blumenstingl
 wrote:
> This is a new driver for the USB PHY found in Meson8b and GXBB SoCs.
>
> Signed-off-by: Martin Blumenstingl 
> Signed-off-by: Jerome Brunet 
> Tested-by: Kevin Hilman 
> ---
>  drivers/phy/Kconfig  |  11 ++
>  drivers/phy/Makefile |   1 +
>  drivers/phy/phy-meson-usb2.c | 280 
> +++
>  3 files changed, 292 insertions(+)
>  create mode 100644 drivers/phy/phy-meson-usb2.c
>
> diff --git a/drivers/phy/Kconfig b/drivers/phy/Kconfig
> index 19bff3a..6ad87ec 100644
> --- a/drivers/phy/Kconfig
> +++ b/drivers/phy/Kconfig
> @@ -453,4 +453,15 @@ config PHY_NS2_PCIE
> help
>   Enable this to support the Broadcom Northstar2 PCIe PHY.
>   If unsure, say N.
> +
> +config PHY_MESON_USB2
> +   tristate "Meson USB2 PHY driver"
> +   default ARCH_MESON
> +   depends on OF && (ARCH_MESON || COMPILE_TEST)
> +   select GENERIC_PHY
as pointed out by Arnd Bergmann (see [0]) this is missing a "select
USB_COMMON", just like the PHY_SUN4I_USB and PHY_SUN9I_USB drivers as
we use of_usb_get_dr_mode_by_phy() to get the mode of the USB
controller (as the PHY needs special configuration for host-mode).

I will send an update on Sunday.


Regards,
Martin


[0] http://marc.info/?l=linux-usb=147386117604824=2
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[PATCH v2 3/6] phy: meson: add USB2 PHY support for Meson8b and GXBB

[Martin Blumenstingl]

This is a new driver for the USB PHY found in Meson8b and GXBB SoCs.

Signed-off-by: Martin Blumenstingl 
Signed-off-by: Jerome Brunet 
Tested-by: Kevin Hilman 
---
 drivers/phy/Kconfig  |  11 ++
 drivers/phy/Makefile |   1 +
 drivers/phy/phy-meson-usb2.c | 280 +++
 3 files changed, 292 insertions(+)
 create mode 100644 drivers/phy/phy-meson-usb2.c

diff --git a/drivers/phy/Kconfig b/drivers/phy/Kconfig
index 19bff3a..6ad87ec 100644
--- a/drivers/phy/Kconfig
+++ b/drivers/phy/Kconfig
@@ -453,4 +453,15 @@ config PHY_NS2_PCIE
help
  Enable this to support the Broadcom Northstar2 PCIe PHY.
  If unsure, say N.
+
+config PHY_MESON_USB2
+   tristate "Meson USB2 PHY driver"
+   default ARCH_MESON
+   depends on OF && (ARCH_MESON || COMPILE_TEST)
+   select GENERIC_PHY
+   help
+ Enable this to support the Meson USB2 PHYs found in Meson8b
+ and GXBB SoCs.
+ If unsure, say N.
+
 endmenu
diff --git a/drivers/phy/Makefile b/drivers/phy/Makefile
index 90ae198..dd507ac 100644
--- a/drivers/phy/Makefile
+++ b/drivers/phy/Makefile
@@ -56,3 +56,4 @@ obj-$(CONFIG_PHY_PISTACHIO_USB)   += 
phy-pistachio-usb.o
 obj-$(CONFIG_PHY_CYGNUS_PCIE)  += phy-bcm-cygnus-pcie.o
 obj-$(CONFIG_ARCH_TEGRA) += tegra/
 obj-$(CONFIG_PHY_NS2_PCIE) += phy-bcm-ns2-pcie.o
+obj-$(CONFIG_PHY_MESON_USB2)   += phy-meson-usb2.o
diff --git a/drivers/phy/phy-meson-usb2.c b/drivers/phy/phy-meson-usb2.c
new file mode 100644
index 000..eece521
--- /dev/null
+++ b/drivers/phy/phy-meson-usb2.c
@@ -0,0 +1,280 @@
+/*
+ * Meson USB2 PHY driver
+ *
+ * Copyright (C) 2016 Martin Blumenstingl 
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see .
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#define REG_CONFIG 0x00
+   #define REG_CONFIG_CLK_EN   BIT(0)
+   #define REG_CONFIG_CLK_SEL_MASK GENMASK(3, 1)
+   #define REG_CONFIG_CLK_DIV_MASK GENMASK(10, 4)
+   #define REG_CONFIG_CLK_32k_ALTSEL   BIT(15)
+   #define REG_CONFIG_TEST_TRIGBIT(31)
+
+#define REG_CTRL   0x04
+   #define REG_CTRL_SOFT_PRST  BIT(0)
+   #define REG_CTRL_SOFT_HRESETBIT(1)
+   #define REG_CTRL_SS_SCALEDOWN_MODE_MASK GENMASK(3, 2)
+   #define REG_CTRL_CLK_DET_RSTBIT(4)
+   #define REG_CTRL_INTR_SEL   BIT(5)
+   #define REG_CTRL_CLK_DETECTED   BIT(8)
+   #define REG_CTRL_SOF_SENT_RCVD_TGL  BIT(9)
+   #define REG_CTRL_SOF_TOGGLE_OUT BIT(10)
+   #define REG_CTRL_POWER_ON_RESET BIT(15)
+   #define REG_CTRL_SLEEPM BIT(16)
+   #define REG_CTRL_TX_BITSTUFF_ENN_H  BIT(17)
+   #define REG_CTRL_TX_BITSTUFF_ENNBIT(18)
+   #define REG_CTRL_COMMON_ON  BIT(19)
+   #define REG_CTRL_REF_CLK_SEL_MASK   GENMASK(21, 20)
+   #define REG_CTRL_REF_CLK_SEL_SHIFT  20
+   #define REG_CTRL_FSEL_MASK  GENMASK(24, 22)
+   #define REG_CTRL_FSEL_SHIFT 22
+   #define REG_CTRL_PORT_RESET BIT(25)
+   #define REG_CTRL_THREAD_ID_MASK GENMASK(31, 26)
+
+#define REG_ENDP_INTR  0x08
+
+/* bits [31:26], [24:21] and [15:3] seem to be read-only */
+#define REG_ADP_BC 0x0c
+   #define REG_ADP_BC_VBUS_VLD_EXT_SEL BIT(0)
+   #define REG_ADP_BC_VBUS_VLD_EXT BIT(1)
+   #define REG_ADP_BC_OTG_DISABLE  BIT(2)
+   #define REG_ADP_BC_ID_PULLUPBIT(3)
+   #define REG_ADP_BC_DRV_VBUS BIT(4)
+   #define REG_ADP_BC_ADP_PRB_EN   BIT(5)
+   #define REG_ADP_BC_ADP_DISCHARGEBIT(6)
+   #define REG_ADP_BC_ADP_CHARGE   BIT(7)
+   #define REG_ADP_BC_SESS_END BIT(8)
+   #define REG_ADP_BC_DEVICE_SESS_VLD  BIT(9)
+   #define REG_ADP_BC_B_VALID  BIT(10)
+   #define REG_ADP_BC_A_VALID  BIT(11)
+   #define REG_ADP_BC_ID_DIG   BIT(12)
+