Hi William,
Am Freitag, 13. Mai 2016, 17:24:56 schrieb William Wu:
> This series add support for rockchip dwc3 driver,
> and add additional optional properties for specific
> platforms (e.g., rockchip platform).
when submitting new versions of patchsets please also start a new thread.
It is hard
Hi William,
Am Dienstag, 21. Juni 2016, 17:11:44 schrieb William Wu:
> On 06/20/2016 10:44 PM, Heiko Stübner wrote:
> > Am Freitag, 17. Juni 2016, 17:18:59 schrieb William Wu:
> >> On 06/17/2016 07:15 AM, Heiko Stübner wrote:
> >>> Am Donnerstag, 2. Juni 2016, 20:34:56 schrieb William Wu:
> T
-by: Frank Wang
> Suggested-by: Heiko Stuebner
> Suggested-by: Guenter Roeck
> Suggested-by: Doug Anderson
still looks nice, so still
Reviewed-by: Heiko Stuebner
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Hi William,
Am Dienstag, 28. Juni 2016, 11:18:04 schrieb William Wu:
> >> So about the usb3 controller clk management, I think it should contain
> >> the following clk:
> >> 1. aclk_usb3otg1
> >> 2. aclk_usb3otg0
> >> 3. aclk_usb3_grf
> >
> > correct, aclk_usb3otgX would then be the busclk for
Hi Kishon,
Am Mittwoch, 29. Juni 2016, 19:44:52 schrieb Kishon Vijay Abraham I:
> On Friday 17 June 2016 10:16 PM, Heiko Stübner wrote:
> > Am Freitag, 17. Juni 2016, 17:24:46 schrieb Kishon Vijay Abraham I:
> > [...]
> >
> >>> + /* find out a proper config which can be matched with dt. */
> >>>
Hi William,
Am Donnerstag, 30. Juni 2016, 19:16:40 schrieb William Wu:
> This patch adds the devicetree documentation required for Rockchip
> USB3.0 core wrapper consisting of USB3.0 IP from Synopsys.
>
> It supports DRD mode, and could operate in device mode (SS, HS, FS)
> and host mode (SS, HS,
he reset and
simply call it again in the reset-case, the whole refcounting done in phy_init
and phy_exit (phy->init_count) really shows that init and exit should be
called pairwise, so that extra reset callback seems justified, so from my phy-
noob-pov
Reviewed-by: Heiko Stuebner
with one mino
ould be
called pairwise, so that extra reset callback seems justified, so from my phy-
noob-pov
Reviewed-by: Heiko Stuebner
> ---
> drivers/phy/phy-core.c | 14 ++
> include/linux/phy/phy.h | 3 +++
> 2 files changed, 17 insertions(+)
>
> diff --git a/drivers/phy/ph
Hi Randy,
could you check if the other host-only dwc2 are also affected by this (rk3188,
rk3036) please? Because they also seem to act up in some strange way
sometimes.
Thanks
Heiko
Am Samstag, 10. September 2016, 02:59:36 CEST schrieb Randy Li:
> At this stage it is the only "full features"
Am Dienstag, 13. September 2016, 19:26:03 CEST schrieb ayaka:
> On 09/13/2016 07:06 PM, Heiko Stuebner wrote:
> > Hi Randy,
> >
> > could you check if the other host-only dwc2 are also affected by this
> > (rk3188, rk3036) please? Because they also seem to act up in s
Hi,
Am Dienstag, 20. September 2016, 11:36:41 CEST schrieb Peter Chen:
> We have an well-known problem that the device needs to do some power
> sequence before it can be recognized by related host, the typical
> example like hard-wired mmc devices and usb devices.
>
> This power sequence is hard
Am Donnerstag, 13. Oktober 2016, 09:22:16 CEST schrieb Peter Chen:
> On Wed, Oct 12, 2016 at 12:30:29PM +0200, Heiko Stuebner wrote:
> > Hi,
> >
> > Am Dienstag, 20. September 2016, 11:36:41 CEST schrieb Peter Chen:
> > > We have an well-known problem that the
Am Montag, 11. Januar 2016, 16:32:00 schrieb John Youn:
> This series fixes a couple regressions reported on Raspberry Pi.
same regressions (Isaw strange usb resets) seem to affect Rockchip as well
and these two patches seem to fix that there too, so
Tested-by: Heiko Stuebner
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To unsubscr
rd input.
When looking over to the other desk and the person using that veyron-
jerry not cursing anymore, it seem to be running fine in a real-world use
for 2 hours now ;-)
So,
Tested-by: Heiko Stuebner
> The patches here will speed up the interrupt controller significantly.
> After th
he newest user manual. It's presumed that
> the "- 1" should have always been there and that this was always a
> documentation error. If some hardware needs the "- 1" and other
> hardware doesn't, we'll have to add a configuration parameter for it in
&
these
> issues without having an unconditional delay.
>
> Fixes: 09c96980dc72 ("usb: dwc2: Add functions to set and clear force
> mode") Reported-by: Caesar Wang
> Tested-by: Caesar Wang
> Signed-off-by: John Youn
Tested-by: Heiko Stuebner
(also on a rk3036 where
Hi William,
Am Donnerstag, 7. Juli 2016, 10:54:24 schrieb William Wu:
> Add a quirk to configure the core to support the
> UTMI+ PHY with an 8- or 16-bit interface. UTMI+ PHY
> interface is hardware property, and it's platform
> dependent. Normall, the PHYIf can be configured
> during coreconsulta
Am Samstag, 9. Juli 2016, 11:38:00 schrieb William.wu:
> Dear Heiko & Balbi，
>
> On 2016/7/8 21:29, Felipe Balbi wrote:
> > Hi,
> >
> > Heiko Stuebner writes:
> >> Am Donnerstag, 7. Juli 2016, 10:54:24 schrieb William Wu:
> >>> Add a quirk
ip phys
Acked-by: Heiko Stuebner
> ---
>
> With growing number of phy drivers, it makes sense to
> group these drivers under their respective vendor/platform
> umbrella directory.
>
> Build-tested 'multi_v7_defconfig'.
>
> drivers/phy/Kconfig
Hi Frank,
Am Sonntag, 5. Februar 2017, 10:51:00 CET schrieb Frank Wang:
> The original posting on Jan 19th have not received any responses, so I
> resend them.
>
> The Current default dwc2 just handle one clock named otg, however, it may
> have two or more clock need to manage for some new SoCs(s
Hi Frank,
Am Montag, 6. Februar 2017, 09:40:35 CET schrieb Frank Wang:
> On 2017/2/5 17:41, Heiko Stuebner wrote:
> > Am Sonntag, 5. Februar 2017, 10:51:00 CET schrieb Frank Wang:
> >> The original posting on Jan 19th have not received any responses, so I
> >> resend t
Hi Frank,
Am Sonntag, 5. Februar 2017, 10:51:01 CET schrieb Frank Wang:
> Originally, dwc2 just handle one clock named otg, however, it may have
> two or more clock need to manage for some new SoCs, so this adds
> change clk to clk's array of dwc2_hsotg to handle more clocks operation.
>
> Signed
Hi Francesco,
Am Donnerstag, 23. Februar 2017, 19:11:37 CET schrieb Francesco Lavra:
> I'm having trouble getting the RK3288 OTG controller (the one at
> ff58) to work in peripheral mode. I'm using a Firefly Reload board,
> and I know the hardware is fine because I can successfully use the por
Am Mittwoch, 1. März 2017, 18:34:23 CET schrieb Meng Dongyang:
> Add u2phy config information in the data of match table for
> rk3328.
>
> Signed-off-by: Meng Dongyang
in general looks good, so
Reviewed-by: Heiko Stuebner
one question below
> drivers/phy/phy-rockchip-i
Hi Daniel,
Am Mittwoch, 1. März 2017, 18:34:22 CET schrieb Meng Dongyang:
> Due to the u2phy registers are separated from general grf, we need to
> add u2phy grf node and place u2phy node in it. And on some platform,
> the 480m clock may need to assign clock parent in dts in stead of
> clock drive
Am Freitag, 3. März 2017, 00:21:56 CET schrieb Rob Herring:
> On Thu, Mar 02, 2017 at 03:49:04PM +0800, Meng Dongyang wrote:
> > Due to the u2phy registers are separated from general grf, we need to
> > add u2phy grf node and place u2phy node in it. So this patch add u2phy
> > grf node.
>
> Simila
o remove unnecessary EXPORT_SYMBOL_GPL calls
With this series applied I get the warning below about a sleeping
function, that is not present without it. This happens quite often (on boot,
when going to suspend, etc).
Other than that, usb still works and the dwc2 now also
finally suspends :-D, so on a
"usb: dwc2: host: add flag to reflect bus state")
> Signed-off-by: Douglas Anderson
I've talked with Doug a lot about that problem today and from reading
this change and the referenced causing change, it looks correct
and good to me, so
Reviewed-by: Heiko Stuebner
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y win you friends. ;)
I gave this a simple spin on my veyron-pinky with both a device attached
directly to the port as well as with an usb-hub in between. Everything was
still working smoothly, so
Tested-by: Heiko Stuebner
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ere also breaks display-output on dwc2-based
Rockchip devices (likely even more), probably due to making the regulator
framework hickup.
With this patch applied, apart from not seeing the NULL-ptr, I also get
display output on my rk3288-veycron Chromebook again, so
Tested-by: Heiko Stuebner
re and playback.
>
> William Wu (2):
> usb: dwc2: alloc dma aligned buffer for isoc split in
> usb: dwc2: fix isoc split in transfer with no data
On rk3036, rk3188, rk3288 and rk3328
Tested-by: Heiko Stuebner
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From: William Wu
Rockchip's RK3328 evaluation board has one USB 3.0 OTG controller,
we enable it and set it act as static xHCI host controller to
support USB 3.0 HOST on RK3328 evaluation board.
Signed-off-by: William Wu
Signed-off-by: Heiko Stuebner
---
changes in v2:
none
arch/arm64
From: William Wu
Adds the device tree bindings description for RK3328 and
compatible USB DWC3 controller.
Signed-off-by: William Wu
Acked-by: Rob Herring
Signed-off-by: Heiko Stuebner
---
changes in v2:
- add Rob's Ack
Ideally usb maintainers would pick up this patch to the binding
doc
Enable the nodes to make the usb3 port usable on that board.
Signed-off-by: Heiko Stuebner
---
changes in v2:
- new patch
arch/arm64/boot/dts/rockchip/rk3328-rock64.dts | 9 +
1 file changed, 9 insertions(+)
diff --git a/arch/arm64/boot/dts/rockchip/rk3328-rock64.dts
b/arch/arm64
From: William Wu
RK3328 has one USB 3.0 OTG controller which uses DWC_USB3
core's general architecture. It can act as static xHCI host
controller, static device controller, USB 3.0/2.0 OTG basing
on ID of USB3.0 PHY.
Signed-off-by: William Wu
Signed-off-by: Heiko Stuebner
---
changes
Am Montag, 4. Dezember 2017, 10:40:38 CET schrieb Heiko Stuebner:
> From: William Wu
>
> Adds the device tree bindings description for RK3328 and
> compatible USB DWC3 controller.
>
> Signed-off-by: William Wu
> Acked-by: Rob Herring
> Signed-off-by: Heiko Stuebne
Hi Greg, Felipe,
Am Montag, 4. Dezember 2017, 10:40:38 CET schrieb Heiko Stuebner:
> From: William Wu
>
> Adds the device tree bindings description for RK3328 and
> compatible USB DWC3 controller.
>
> Signed-off-by: William Wu
> Acked-by: Rob Herring
> Signed-off-by:
Am Montag, 4. Dezember 2017, 10:40:38 CET schrieb Heiko Stuebner:
> From: William Wu
>
> Adds the device tree bindings description for RK3328 and
> compatible USB DWC3 controller.
>
> Signed-off-by: William Wu
> Acked-by: Rob Herring
> Signed-off-by: Heiko Stueb
Hi Stefan,
Am Montag, 17. April 2017, 13:05:40 CEST schrieb Stefan Wahren:
> > Stefan Wahren hat am 31. Oktober 2016 um 21:34
> > geschrieben:
> >
> >
> > I inspired by this issue [1] i build up a slightly modified setup with a
> > Raspberry Pi B (mainline kernel 4.9rc3), a powered 7 port USB
This is split out from the series adding the px30 support, due to
the dwc2 binding change not having landed yet in a maintainer tree.
The Acked binding change should go through some usb tree, while
I'll pick up the dts changes once that has happened.
The binding itself is unchanged.
From: Liang Chen
This patch adds the compatible of dwc2 for PX30 SoCs.
Signed-off-by: Liang Chen
Acked-by: Rob Herring
Signed-off-by: Heiko Stuebner
---
unchanged from it being part of the general px30 series
Documentation/devicetree/bindings/usb/dwc2.txt | 1 +
1 file changed, 1 insertion
Add the node for the dwc2-based otg controller on the px30 soc.
Signed-off-by: Heiko Stuebner
---
arch/arm64/boot/dts/rockchip/px30.dtsi | 16
1 file changed, 16 insertions(+)
diff --git a/arch/arm64/boot/dts/rockchip/px30.dtsi
b/arch/arm64/boot/dts/rockchip/px30.dtsi
index
Enable the newly added controller on the px30 evaluation board.
Signed-off-by: Heiko Stuebner
---
arch/arm64/boot/dts/rockchip/px30-evb.dts | 4
1 file changed, 4 insertions(+)
diff --git a/arch/arm64/boot/dts/rockchip/px30-evb.dts
b/arch/arm64/boot/dts/rockchip/px30-evb.dts
index
Hi,
I'm currently trying to wrap my head around the new typec subsystem and
also how to do it correctly on Rockchip rk3399 devices.
The issue (and Guenter might know quite a bit about that) is that on
ChromeOS devices the embedded controller hides the whole tcpm/vdm
logic from the operating syste
Hi Heikki,
Am Montag, 13. August 2018, 15:36:37 CEST schrieb Heikki Krogerus:
> On Mon, Aug 13, 2018 at 12:36:55PM +0200, Heiko Stuebner wrote:
> > I'm currently trying to wrap my head around the new typec subsystem and
> > also how to do it correctly on Rockchip rk3399 d
Hi Greg, Felipe,
Am Donnerstag, 2. August 2018, 15:01:31 CEST schrieb Heiko Stuebner:
> From: Liang Chen
>
> This patch adds the compatible of dwc2 for PX30 SoCs.
>
> Signed-off-by: Liang Chen
> Acked-by: Rob Herring
> Signed-off-by: Heiko Stuebner
Do you want to pi
Hi Guenter,
Am Montag, 13. August 2018, 14:29:15 CEST schrieb Guenter Roeck:
> On 08/13/2018 03:36 AM, Heiko Stuebner wrote:
> > Hi,
> >
> > I'm currently trying to wrap my head around the new typec subsystem and
> > also how to do it correctly on Rockchip rk3399
Am Donnerstag, 2. August 2018, 15:01:30 CEST schrieb Heiko Stuebner:
> This is split out from the series adding the px30 support, due to
> the dwc2 binding change not having landed yet in a maintainer tree.
>
> The Acked binding change should go through some usb tree, while
> I
Hi,
Am Mittwoch, 15. August 2018, 16:46:36 CEST schrieb Heikki Krogerus:
> On Tue, Aug 14, 2018 at 03:58:31PM +0200, Heiko Stuebner wrote:
> > Am Montag, 13. August 2018, 15:36:37 CEST schrieb Heikki Krogerus:
> > > On Mon, Aug 13, 2018 at 12:36:55PM +0200, Heiko Stuebner w
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