Re: [PATCH v2 2/3] usb: dwc3: use BIT() macro where possible

2017-03-10 Thread Felipe Balbi 
Roger Quadros  writes:

> To avoid checkpatch warnings with new patches let's
> start using the BIT() macro wherever possible.
>
> Signed-off-by: Roger Quadros 

unfortunately doesn't apply:

checking file drivers/usb/dwc3/core.h
Hunk #2 succeeded at 67 (offset 1 line).
Hunk #3 succeeded at 177 (offset 1 line).
Hunk #4 succeeded at 194 (offset 1 line).
Hunk #5 FAILED at 221.
Hunk #6 succeeded at 250 (offset 2 lines).
Hunk #7 succeeded at 291 (offset 2 lines).
Hunk #8 succeeded at 312 (offset 2 lines).
Hunk #9 succeeded at 343 (offset 2 lines).
Hunk #10 succeeded at 366 (offset 2 lines).
Hunk #11 succeeded at 405 (offset 2 lines).
Hunk #12 succeeded at 423 (offset 2 lines).
Hunk #13 succeeded at 460 (offset 2 lines).
Hunk #14 succeeded at 502 (offset 2 lines).
Hunk #15 succeeded at 552 (offset 2 lines).
Hunk #16 succeeded at 640 (offset 2 lines).
Hunk #17 succeeded at 1056 (offset 6 lines).
1 out of 17 hunks FAILED
checking file drivers/usb/dwc3/dwc3-omap.c
checking file drivers/usb/dwc3/gadget.h

-- 
balbi


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[PATCH v2 2/3] usb: dwc3: use BIT() macro where possible

2017-02-16 Thread Roger Quadros 
To avoid checkpatch warnings with new patches let's
start using the BIT() macro wherever possible.

Signed-off-by: Roger Quadros 
---
v2:
-include bitops.h

 drivers/usb/dwc3/core.h  | 193 ++-
 drivers/usb/dwc3/dwc3-omap.c |  48 +--
 drivers/usb/dwc3/gadget.h|  20 ++---
 3 files changed, 131 insertions(+), 130 deletions(-)

diff --git a/drivers/usb/dwc3/core.h b/drivers/usb/dwc3/core.h
index 14b7602..85f44e1 100644
--- a/drivers/usb/dwc3/core.h
+++ b/drivers/usb/dwc3/core.h
@@ -23,6 +23,7 @@
 #include 
 #include 
 #include 
+#include 
 #include 
 #include 
 #include 
@@ -65,7 +66,7 @@
 #define DWC3_DEVICE_EVENT_OVERFLOW 11
 
 #define DWC3_GEVNTCOUNT_MASK   0xfffc
-#define DWC3_GEVNTCOUNT_EHB(1 << 31)
+#define DWC3_GEVNTCOUNT_EHBBIT(31)
 #define DWC3_GSNPSID_MASK  0x
 #define DWC3_GSNPSREV_MASK 0x
 
@@ -175,11 +176,11 @@
 /* Global RX Threshold Configuration Register */
 #define DWC3_GRXTHRCFG_MAXRXBURSTSIZE(n) (((n) & 0x1f) << 19)
 #define DWC3_GRXTHRCFG_RXPKTCNT(n) (((n) & 0xf) << 24)
-#define DWC3_GRXTHRCFG_PKTCNTSEL (1 << 29)
+#define DWC3_GRXTHRCFG_PKTCNTSEL BIT(29)
 
 /* Global Configuration Register */
 #define DWC3_GCTL_PWRDNSCALE(n)((n) << 19)
-#define DWC3_GCTL_U2RSTECN (1 << 16)
+#define DWC3_GCTL_U2RSTECN BIT(16)
 #define DWC3_GCTL_RAMCLKSEL(x) (((x) & DWC3_GCTL_CLK_MASK) << 6)
 #define DWC3_GCTL_CLK_BUS  (0)
 #define DWC3_GCTL_CLK_PIPE (1)
@@ -192,24 +193,24 @@
 #define DWC3_GCTL_PRTCAP_DEVICE2
 #define DWC3_GCTL_PRTCAP_OTG   3
 
-#define DWC3_GCTL_CORESOFTRESET(1 << 11)
-#define DWC3_GCTL_SOFITPSYNC   (1 << 10)
+#define DWC3_GCTL_CORESOFTRESETBIT(11)
+#define DWC3_GCTL_SOFITPSYNC   BIT(10)
 #define DWC3_GCTL_SCALEDOWN(n) ((n) << 4)
 #define DWC3_GCTL_SCALEDOWN_MASK   DWC3_GCTL_SCALEDOWN(3)
-#define DWC3_GCTL_DISSCRAMBLE  (1 << 3)
-#define DWC3_GCTL_U2EXIT_LFPS  (1 << 2)
-#define DWC3_GCTL_GBLHIBERNATIONEN (1 << 1)
-#define DWC3_GCTL_DSBLCLKGTNG  (1 << 0)
+#define DWC3_GCTL_DISSCRAMBLE  BIT(3)
+#define DWC3_GCTL_U2EXIT_LFPS  BIT(2)
+#define DWC3_GCTL_GBLHIBERNATIONEN BIT(1)
+#define DWC3_GCTL_DSBLCLKGTNG  BIT(0)
 
 /* Global User Control 1 Register */
-#define DWC3_GUCTL1_DEV_L1_EXIT_BY_HW  (1 << 24)
+#define DWC3_GUCTL1_DEV_L1_EXIT_BY_HW  BIT(24)
 
 /* Global USB2 PHY Configuration Register */
-#define DWC3_GUSB2PHYCFG_PHYSOFTRST(1 << 31)
-#define DWC3_GUSB2PHYCFG_U2_FREECLK_EXISTS (1 << 30)
-#define DWC3_GUSB2PHYCFG_SUSPHY(1 << 6)
-#define DWC3_GUSB2PHYCFG_ULPI_UTMI (1 << 4)
-#define DWC3_GUSB2PHYCFG_ENBLSLPM  (1 << 8)
+#define DWC3_GUSB2PHYCFG_PHYSOFTRSTBIT(31)
+#define DWC3_GUSB2PHYCFG_U2_FREECLK_EXISTS BIT(30)
+#define DWC3_GUSB2PHYCFG_SUSPHYBIT(6)
+#define DWC3_GUSB2PHYCFG_ULPI_UTMI BIT(4)
+#define DWC3_GUSB2PHYCFG_ENBLSLPM  BIT(8)
 #define DWC3_GUSB2PHYCFG_PHYIF(n)  (n << 3)
 #define DWC3_GUSB2PHYCFG_PHYIF_MASKDWC3_GUSB2PHYCFG_PHYIF(1)
 #define DWC3_GUSB2PHYCFG_USBTRDTIM(n)  (n << 10)
@@ -220,25 +221,25 @@
 #define UTMI_PHYIF_8_BIT   0
 
 /* Global USB2 PHY Vendor Control Register */
-#define DWC3_GUSB2PHYACC_NEWREGREQ (1 << 25)
-#define DWC3_GUSB2PHYACC_BUSY  (1 << 23)
-#define DWC3_GUSB2PHYACC_WRITE (1 << 22)
+#define DWC3_GUSB2PHYACC_NEWREGREQ BIT(25)
+#define DWC3_GUSB2PHYACC_BUSY  BIT(23)
+#define DWC3_GUSB2PHYACC_WRITE BIT(22)
 #define DWC3_GUSB2PHYACC_ADDR(n)   (n << 16)
 #define DWC3_GUSB2PHYACC_EXTEND_ADDR(n)(n << 8)
 #define DWC3_GUSB2PHYACC_DATA(n)   (n & 0xff)
 
 /* Global USB3 PIPE Control Register */
-#define DWC3_GUSB3PIPECTL_PHYSOFTRST   (1 << 31)
-#define DWC3_GUSB3PIPECTL_U2SSINP3OK   (1 << 29)
-#define DWC3_GUSB3PIPECTL_DISRXDETINP3 (1 << 28)
-#define DWC3_GUSB3PIPECTL_REQP1P2P3(1 << 24)
+#define DWC3_GUSB3PIPECTL_PHYSOFTRST   BIT(31)
+#define DWC3_GUSB3PIPECTL_U2SSINP3OK   BIT(29)
+#define DWC3_GUSB3PIPECTL_DISRXDETINP3 BIT(28)
+#define DWC3_GUSB3PIPECTL_REQP1P2P3BIT(24)
 #define DWC3_GUSB3PIPECTL_DEP1P2P3(n)  ((n) << 19)
 #define DWC3_GUSB3PIPECTL_DEP1P2P3_MASKDWC3_GUSB3PIPECTL_DEP1P2P3(7)
 #define DWC3_GUSB3PIPECTL_DEP1P2P3_EN  DWC3_GUSB3PIPECTL_DEP1P2P3(1)
-#define DWC3_GUSB3PIPECTL_DEPOCHANGE   (1 << 18)
-#define DWC3_GUSB3PIPECTL_SUSPHY   (1 << 17)
-#define DWC3_GUSB3PIPECTL_LFPSFILT (1 << 9)
-#define DWC3_GUSB3PIPECTL_RX_DETOPOLL  (1 << 8)
+#define DWC3_GUSB3PIPECTL_DEPOCHANGE   BIT(18)
+#define DWC3_GUSB3PIPECTL_SUSPHY   BIT(17)
+#define DWC3_GUSB3PIPECTL_LFPSFILT BIT(9)
+#define DWC3_GUSB3PIPECTL_RX_DETOPOLL  BIT(8)
 #define DWC3_GUSB3PIPECTL_TX_DEEPH_MASKDWC3_GUSB3PIPECTL_TX_DEEPH(3)
 #define DWC3_GUSB3PIPECTL_TX_DEEPH(n)  ((n) << 1)
 
@@ -247,7 +248,7 @@
 #define DWC3_GTXFIFOSIZ_TXFSTADDR(n)   ((n) & 0x)
 
 /* Global