On 2018/11/13 04:17, Bruce Ashfield wrote:
> On 2018-11-12 4:49 a.m., He Zhe wrote:
>>
>>
>> On 2018/11/6 00:05, Bruce Ashfield wrote:
>>> On 11/2/18 4:42 AM, He Zhe wrote:
When merging tag 'v4.18.10' into v4.18/standard/base, 05a9931 "of: fix
phandle
cache creation for DTs with n
Since 'CONFIG_NR_CPUS=256' was moved to intel-x86-64.cfg, seeing
commit [11917e28727], we would better explicitly set CONFIG_NR_CPUS
to 64 in intel-x86-32.cfg for a future re-org of the fragments.
And the '64' is also the default value for intel-x86-32.
Signed-off-by: Hongzhi.Song
---
bsp/intel
On 2018-11-12 4:49 a.m., He Zhe wrote:
On 2018/11/6 00:05, Bruce Ashfield wrote:
On 11/2/18 4:42 AM, He Zhe wrote:
When merging tag 'v4.18.10' into v4.18/standard/base, 05a9931 "of: fix phandle
cache creation for DTs with no phandles" from v4.18.10 introduces an undefined
label "out" and caus
On 2018/11/6 00:05, Bruce Ashfield wrote:
> On 11/2/18 4:42 AM, He Zhe wrote:
>> When merging tag 'v4.18.10' into v4.18/standard/base, 05a9931 "of: fix
>> phandle
>> cache creation for DTs with no phandles" from v4.18.10 introduces an
>> undefined
>> label "out" and causes the follow compilatio
