[linux-yocto] [yocto-kernel-cache] [PATCH 0/4] Enable more kernel driver features for Broxton

From: "Chang, Rebecca Swee Fun" Hi Bruce, Broxton supports the following kernel driver features: - LPC bridge for Intel ICH and SCH - iSMT support - iTCO watchdog I have enabled the features under broxton soc config. I have also expanded the usb-net coverage

[linux-yocto] [yocto-kernel-cache] [PATCH 2/4] features: broxton: enable iSMT support

From: "Chang, Rebecca Swee Fun" This will include support for Intel iSMT SMBus host controller interface for Broxton. Signed-off-by: Chang, Rebecca Swee Fun --- features/soc/broxton/broxton.cfg | 3 +++ 1 file changed, 3

[linux-yocto] [yocto-kernel-cache] [PATCH 4/4] features: usb-net: provide more coverage on USB network devices

From: "Chang, Rebecca Swee Fun" Expanding the list of USB network devices supported by various BSP. Compiled as modules to provide more flexibility on use cases. Signed-off-by: Chang, Rebecca Swee Fun ---

[linux-yocto] [yocto-kernel-cache] [PATCH 1/4] features: broxton: enable LPC bridge function for Intel ICH and SCH

From: "Chang, Rebecca Swee Fun" Signed-off-by: Chang, Rebecca Swee Fun --- features/soc/broxton/broxton.cfg | 4 1 file changed, 4 insertions(+) diff --git a/features/soc/broxton/broxton.cfg

[linux-yocto] [yocto-kernel-cache] [PATCH] Fix bitbake warnings on build

From: Rebecca Chang Swee Fun Hi Bruce, With a build test run on Intel Common BSP, some warning messages poped out about actual value set is not matched with requested value on CONFIG_GPIO_GENERIC. This can be resolved by setting CONFIG_GPIO_GENERIC_PLATFORM=y

[linux-yocto] [yocto-kernel-cache] [PATCH] broxton: set CONFIG_GPIO_GENERIC_PLATFORM instead of CONFIG_GPIO_GENERIC

From: Rebecca Chang Swee Fun CONFIG_GPIO_GENERIC option is tristate, this will ensure we enable by selecting CONFIG_GPIO_GENERIC_PLATFORM. This addresses the following message: Value requested for CONFIG_GPIO_GENERIC not in final ".config" Requested value:

[linux-yocto] [yocto-kernel-cache] [PATCH 7/9] bsp/intel-common: Add broxton to supported SoCs in intel-core* BSPs

From: California Sullivan Adds support to features found on Broxton SoCs. Signed-off-by: California Sullivan Signed-off-by: Bruce Ashfield (cherry picked from commit

[linux-yocto] [yocto-kernel-cache] [PATCH 9/9] bsp/intel-corei7-64: Add intel-telemetry feature

From: California Sullivan intel-telemetry is a 64 bit feature available on the Apollo Lake platform and beyond. Signed-off-by: Bruce Ashfield (cherry picked from commit 9ab4787fe2aea2ae0fcc31a5e067eaba19ef64c8) Signed-off-by:

[linux-yocto] [yocto-kernel-cache] [PATCH 5/9] baytrail; valleyisland: Use designware-usb3 feature instead of config

From: California Sullivan A common configuration is shared across many platforms. Use a feature instead of additional configuration options in each file. Signed-off-by: California Sullivan Signed-off-by: Bruce Ashfield

[linux-yocto] [yocto-kernel-cache] [PATCH 6/9] features: add broxton soc feature

From: California Sullivan This feature fragment should support most functions provided by the Broxton SoC. Signed-off-by: California Sullivan Signed-off-by: Bruce Ashfield (cherry picked from

[linux-yocto] [yocto-kernel-cache] [PATCH 4/9] features/usb: Add usb-designware2 and 3 features

From: California Sullivan These features support DesignWare USB2 and USB3 controllers and are used by many SoCs. Signed-off-by: California Sullivan Signed-off-by: Bruce Ashfield (cherry picked from

[linux-yocto] [yocto-kernel-cache] [PATCH 3/9] cfg/sound.cfg: Add USB audio support

From: California Sullivan Sound over USB is very common and should be part of general sound configuration. Signed-off-by: California Sullivan Signed-off-by: Bruce Ashfield (cherry picked from

[linux-yocto] [yocto-kernel-cache] [PATCH 2/9] features/i915: Add CONFIG_KMS_FB_HELPER=y

From: California Sullivan We already get this option through a select. Add it to the configuration for clarity. Signed-off-by: California Sullivan Signed-off-by: Bruce Ashfield (cherry picked from

[linux-yocto] [yocto-kernel-cache] [PATCH 1/9] intel_pwm: refactor and use the feature fragment

From: California Sullivan Configure PWMs on Intel platforms as modules and add it to intel-common-drivers. Remove PWM configurations from baytrail.cfg since its enabled elsewhere. Signed-off-by: California Sullivan

[linux-yocto] [yocto-kernel-cache] [PATCH 0/9] Backport config fragments from yocto-4.4

From: Rebecca Chang Swee Fun Hi, This series of patches are cherry-picked from yocto-4.4 branch and intend to merge into yocto-4.1. The fragments involved are generally used by Atom based BSP. This backport also enabled linux kernel v4.1.x support for Broxton

[linux-yocto] [PATCH 0/1] meta: features: update baytrail.cfg

From: Chang Rebecca Swee Fun rebecca.swee.fun.ch...@intel.com Hi, Here is an update to fix typo error in baytrail.cfg. CONFIG_DW_PCI is invalid. It was not detected in Valley Island BSP because Valley Island has its own feature scc and cfg in linux-yocto-3.10 and linux-yocto-3.14 kernel but not

[linux-yocto] [PATCH 1/1] features: soc: fix typo in baytrail.cfg

From: Chang Rebecca Swee Fun rebecca.swee.fun.ch...@intel.com Fix the DMA config typo to CONFIG_DW_DMA_PCI. Signed-off-by: Chang Rebecca Swee Fun rebecca.swee.fun.ch...@intel.com --- meta/cfg/kernel-cache/features/soc/baytrail/baytrail.cfg | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)

[linux-yocto] [PATCHv2 4/6] pinctrl-baytrail: unmap interrupt when free the gpio pin

From: Chew, Kean Ho kean.ho.c...@intel.com In to_irq() callback, we create the hwirq to linux irq mapping for the requested GPIO pin. Hence, we unamp the mapping when the gpio pin is being released. Signed-off-by: Chew, Kean Ho kean.ho.c...@intel.com Signed-off-by: Chew, Chiau Ee

[linux-yocto] [PATCHv2 3/6] pinctrl-baytrail: add function mux checking in gpio pin request

From: Chew, Kean Ho kean.ho.c...@intel.com The requested gpio pin must has the func_pin_mux field set to GPIO function by BIOS/FW in advanced. Else, the gpio pin request would fail. This is to ensure that we do not expose any gpio pins which shall be used for alternate functions, for eg: wakeup

[linux-yocto] [PATCHv2 2/6] x86/byt: enable board file for Baytrail LPSS PCI mode

From: Chang Rebecca Swee Fun rebecca.swee.fun.ch...@intel.com This commit enables the following: - register SPI slave - fix device name string for clkdev registration - insert kernel module param to allow user to disable the BYT PCI board file Signed-off-by: Chew Chiau Ee

[linux-yocto] [PATCHv2 5/6] pinctrl-baytrail: enable platform device in the absent of ACPI enumeration

From: Chew, Kean Ho kean.ho.c...@intel.com This is to cater the need for non-ACPI system whereby a platform device has to be created in order to bind with the BYT Pinctrl GPIO platform driver. Signed-off-by: Chew, Kean Ho kean.ho.c...@intel.com Signed-off-by: Chew, Chiau Ee

[linux-yocto] [PATCHv2 6/6] pinctrl-baytrail: setup IOAPIC interrupt for GPIO clusters on non-ACPI system

From: Chew, Kean Ho kean.ho.c...@intel.com BayTrail GPIO NORTH, SOUTH and SUS clusters use IRQ48, 49 and 50 respectively. On non-ACPI system, we need to setup IOAPIC RTE for device that use interrupt beyond IRQ23. Signed-off-by: Chew, Kean Ho kean.ho.c...@intel.com Signed-off-by: Chew, Chiau Ee

[linux-yocto] [PATCHv2 0/6] [3.10] Feature branch for Baytrail IO

From: Chang Rebecca Swee Fun rebecca.swee.fun.ch...@intel.com Hi all, Patchv2: This is the 2nd revision of the feature branch I have submitted yesterday. I have used the outdated board file for Baytrail in previous submission. I have updated the tree with a latest board file to enable DMA clock

[linux-yocto] [PATCH 03/28] pwm: add support for Intel Low Power Subsystem PWM

From: Mika Westerberg mika.westerb...@linux.intel.com Add support for Intel Low Power I/O subsystem PWM controllers found on Intel BayTrail SoC. Signed-off-by: Mika Westerberg mika.westerb...@linux.intel.com Signed-off-by: Chew, Kean Ho kean.ho.c...@intel.com Signed-off-by: Chang, Rebecca Swee

[linux-yocto] [PATCH 04/28] pwm: lpss: Add support for PCI devices

From: Alan Cox a...@linux.intel.com Not all systems enumerate the PWM devices via ACPI. They can also be exposed via the PCI interface. Signed-off-by: Alan Cox a...@linux.intel.com Signed-off-by: Chew, Chiau Ee chiau.ee.c...@intel.com Reviewed-by: Mika Westerberg mika.westerb...@linux.intel.com

[linux-yocto] [PATCH 02/28] ACPI / LPSS: Add Intel BayTrail ACPI mode PWM

From: Chew, Chiau Ee chiau.ee.c...@intel.com Intel BayTrail LPSS consists of two PWM controllers which can be enumerated from ACPI namespace. This change will cause platform device objects to be created for Intel BayTrail PWM controllers which will allow the pwm-lpss driver to bind to them and

[linux-yocto] [PATCH 01/28] pwm: Add sysfs interface

From: H Hartley Sweeten hartl...@visionengravers.com Add a simple sysfs interface to the generic PWM framework. /sys/class/pwm/ `-- pwmchipN/ for each PWM chip |-- export (w/o) ask the kernel to export a PWM channel |-- npwm(r/o) number of PWM

[linux-yocto] [PATCH 05/28] pwm: lpss: Fix const qualifier and sparse warnings

From: Thierry Reding thierry.red...@gmail.com Fixes the following warnings reported by the 0-DAY kernel build testing backend: drivers/pwm/pwm-lpss.c: In function 'pwm_lpss_probe_pci': drivers/pwm/pwm-lpss.c:192:2: warning: passing argument 3 of 'pwm_lpss_probe' discards 'const' qualifier

[linux-yocto] [PATCH 11/28] serial: 8250_pci: add support for Intel BayTrail

From: Heikki Krogerus heikki.kroge...@linux.intel.com Intel BayTrail has two HS-UARTs with 64 byte fifo, support for DMA and support for 16750 compatible Auto Flow Control. Signed-off-by: Heikki Krogerus heikki.kroge...@linux.intel.com Signed-off-by: Greg Kroah-Hartman gre...@linuxfoundation.org

[linux-yocto] [PATCH 12/28] 8250_dw: Support all baudrates on baytrail

From: Loic Poulain loic.poul...@intel.com In the same manner as 8250_pci, 8250_dw needs some baytrail specific quirks to be used. The reference clock needs to be adjusted before divided in order to have the minimum error rate on the baudrate. The specific byt set termios function is stored in

[linux-yocto] [PATCH 09/28] serial: 8250_dma: check the result of TX buffer mapping

From: Heikki Krogerus heikki.kroge...@linux.intel.com Using dma_mapping_error() to make sure the mapping did not fail. Signed-off-by: Heikki Krogerus heikki.kroge...@linux.intel.com Signed-off-by: Greg Kroah-Hartman gre...@linuxfoundation.org (cherry picked from commit

[linux-yocto] [PATCH 10/28] serial: 8250: don't change the fifo trigger level when using dma

From: Heikki Krogerus heikki.kroge...@linux.intel.com DMA engines usually expect the fifo trigger level to be aligned with the burst size. It should not be changed even with small baud rates. This will fix an issue with Designware DMA engine where the data can not be transferred over UART with

[linux-yocto] [PATCH 14/28] mmc: sdhci: Preset value not supported in Baytrail eMMC

From: Maurice Petallo mauricex.r.peta...@intel.com SDHCI_QUIRK2_PRESET_VALUE_BROKEN quirk is added to prohibit preset value enabling for Baytrail eMMC controller. Signed-off-by: Maurice Petallo mauricex.r.peta...@intel.com Acked-by: Adrian Hunter adrian.hun...@intel.com Signed-off-by: Ulf

[linux-yocto] [PATCH 13/28] mmc: sdhci: Allow for irq being shared

From: Adrian Hunter adrian.hun...@intel.com If the SDHCI irq is shared with another device then the interrupt handler can get called while SDHCI is runtime suspended. That is harmless but the warning message is not useful so remove it. Also returning IRQ_NONE is more appropriate.

[linux-yocto] [PATCH 21/28] spi: remove DEFINE_PCI_DEVICE_TABLE macro

From: Jingoo Han jg1@samsung.com Don't use DEFINE_PCI_DEVICE_TABLE macro, because this macro is not preferred. Signed-off-by: Jingoo Han jg1@samsung.com Signed-off-by: Mark Brown broo...@linaro.org (cherry picked from commit 9a21e4770ac828a49e722897c3c0250f630f4a48) Signed-off-by: Chang

[linux-yocto] [PATCH 20/28] i2c: designware-pci: set ideal HCNT, LCNT and SDA hold time value

From: Chew, Chiau Ee chiau.ee.c...@intel.com On Intel BayTrail, there was case whereby the resulting fast mode bus speed becomes slower (~20% slower compared to expected speed) if using the HCNT/LCNT calculated in the core layer. Thus, this patch is added to allow pci glue layer to pass in

[linux-yocto] [PATCH 19/28] i2c: designware-pci: add 10-bit addressing mode functionality for BYT I2C

From: Chew, Chiau Ee chiau.ee.c...@intel.com All the I2C controllers on Intel BayTrail LPSS subsystem able to support 10-bit addressing mode functionality. Signed-off-by: Chew, Chiau Ee chiau.ee.c...@intel.com Signed-off-by: Ong, Boon Leong boon.leong@intel.com Signed-off-by: Wolfram Sang

[linux-yocto] [PATCH 16/28] usb: gadget: don't fail when DMA isn't present

From: Alan Stern st...@rowland.harvard.edu When CONFIG_HAS_DMA isn't enabled, the UDC core gets build errors: drivers/built-in.o: In function `dma_set_coherent_mask': include/linux/dma-mapping.h:93: undefined reference to `dma_supported' include/linux/dma-mapping.h:93: undefined reference to

[linux-yocto] [PATCH 17/28] usb: gadget: udc-core: move sysfs_notify() to a workqueue

From: Felipe Balbi ba...@ti.com usb_gadget_set_state() will call sysfs_notify() which might sleep. Some users might want to call usb_gadget_set_state() from the very IRQ handler which actually changes the gadget state. Instead of having every UDC driver add their own workqueue for such a simple

[linux-yocto] [PATCH 24/28] spi/pxa2xx: Prevent DMA from transferring too many bytes

From: Mika Westerberg mika.westerb...@linux.intel.com In case we are doing DMA transfer and the size of the buffer is not multiple of 4 bytes the driver truncates that to 4-byte boundary and tries to handle remaining bytes using PIO. Or that is what it tried to do. What actually happens is that

[linux-yocto] [PATCH 28/28] spi/pxa2xx-pci: Add common clock framework support in PCI glue layer

From: Chew, Chiau Ee chiau.ee.c...@intel.com pending to upstream in linux-next commit afa93c9017fd48d4d5265854c75f5fcde0871548 SPI PXA2XX core layer has dependency on common clock framework to obtain information on host supported clock rate. Thus, we setup the clock device in the PCI glue layer

[linux-yocto] [PATCH 1/6] x86/Kconfig: add PCI dependency for CONFIG_X86_INTEL_LPSS

From: Chew, Chiau Ee chiau.ee.c...@intel.com Allow CONFIG_X86_INTEL_LPSS to be set when ACPI or PCI is set. Signed-off-by: Chew, Chiau Ee chiau.ee.c...@intel.com Signed-off-by: Maurice Petallo mauricex.r.peta...@intel.com --- arch/x86/Kconfig | 2 +- 1 file changed, 1 insertion(+), 1

[linux-yocto] [PATCH 6/6] pinctrl-baytrail: setup IOAPIC interrupt for GPIO clusters on non-ACPI system

From: Chew, Kean Ho kean.ho.c...@intel.com BayTrail GPIO NORTH, SOUTH and SUS clusters use IRQ48, 49 and 50 respectively. On non-ACPI system, we need to setup IOAPIC RTE for device that use interrupt beyond IRQ23. Signed-off-by: Chew, Kean Ho kean.ho.c...@intel.com Signed-off-by: Chew, Chiau Ee

[linux-yocto] [PATCH 3/6] pinctrl-baytrail: add function mux checking in gpio pin request

From: Chew, Kean Ho kean.ho.c...@intel.com The requested gpio pin must has the func_pin_mux field set to GPIO function by BIOS/FW in advanced. Else, the gpio pin request would fail. This is to ensure that we do not expose any gpio pins which shall be used for alternate functions, for eg: wakeup

[linux-yocto] [PATCH 4/6] pinctrl-baytrail: unmap interrupt when free the gpio pin

From: Chew, Kean Ho kean.ho.c...@intel.com In to_irq() callback, we create the hwirq to linux irq mapping for the requested GPIO pin. Hence, we unamp the mapping when the gpio pin is being released. Signed-off-by: Chew, Kean Ho kean.ho.c...@intel.com Signed-off-by: Chew, Chiau Ee

[linux-yocto] [PATCH 0/6] [3.10] Feature branch for Baytrail IO

From: Chang Rebecca Swee Fun rebecca.swee.fun.ch...@intel.com Hi all, This is the rebased feature branch for valley island BSP. The purpose of this feature branch is to stage the Baytrail I/O specific patches that is not encouraged to be upstream, for example, board file. This tree also consists

[linux-yocto] [PATCH 2/6] x86/byt: enable board file for Baytrail LPSS PCI mode

From: Chang Rebecca Swee Fun rebecca.swee.fun.ch...@intel.com This commit enables the following: - register SPI slave - insert kernel module param to allow user to disable the BYT PCI board file Signed-off-by: Chew Chiau Ee chiau.ee.c...@intel.com Signed-off-by: Maurice Petallo

[linux-yocto] [PATCH 0/1] meta: update valleyisland scc to merge new feature branch

From: Chang Rebecca Swee Fun rebecca.swee.fun.ch...@intel.com Hi all, Valley Island I/O feature branch was recently rebased to new version and I would like to push this patch into meta branch so that we can merge the new feature branch with standard/base. This patch is about updating the scc

[linux-yocto] [PATCH 1/1] meta: update valleyisland scc to merge feature branch

From: Chang Rebecca Swee Fun rebecca.swee.fun.ch...@intel.com Valley Island feature branch was rebased recently and its scc file need update in order to merge new feature branch, valleyisland-io-2.0. Signed-off-by: Chang Rebecca Swee Fun rebecca.swee.fun.ch...@intel.com ---

[linux-yocto] [PATCH 07/21] serial: 8250: don't change the fifo trigger level when using dma

From: Heikki Krogerus heikki.kroge...@linux.intel.com DMA engines usually expect the fifo trigger level to be aligned with the burst size. It should not be changed even with small baud rates. This will fix an issue with Designware DMA engine where the data can not be transferred over UART with

[linux-yocto] [PATCH 16/21] pwm: Add sysfs interface

From: H Hartley Sweeten hartl...@visionengravers.com Add a simple sysfs interface to the generic PWM framework. /sys/class/pwm/ `-- pwmchipN/ for each PWM chip |-- export (w/o) ask the kernel to export a PWM channel |-- npwm(r/o) number of PWM

[linux-yocto] [PATCH 18/21] pinctrl-baytrail: add function mux checking in gpio pin request

From: Chew, Kean Ho kean.ho.c...@intel.com The requested gpio pin must has the func_pin_mux field set to GPIO function by BIOS/FW in advanced. Else, the gpio pin request would fail. This is to ensure that we do not expose any gpio pins which shall be used for alternate functions, for eg: wakeup

[linux-yocto] [PATCH 11/21] i2c: designware-pci: Add Baytrail PCI IDs

From: Mika Westerberg mika.westerb...@linux.intel.com Intel Baytrail I2C controllers can be enumerated from PCI as well as from ACPI. In order to support this add the Baytrail PCI IDs to the driver. Signed-off-by: Mika Westerberg mika.westerb...@linux.intel.com Signed-off-by: Wolfram Sang

[linux-yocto] [PATCH 17/21] mmc: sdhci: Allow for irq being shared

From: Adrian Hunter adrian.hun...@intel.com If the SDHCI irq is shared with another device then the interrupt handler can get called while SDHCI is runtime suspended. That is harmless but the warning message is not useful so remove it. Also returning IRQ_NONE is more appropriate.

[linux-yocto] [PATCH 15/21] ACPI / LPSS: Add Intel BayTrail ACPI mode PWM

From: Chew, Chiau Ee chiau.ee.c...@intel.com Intel BayTrail LPSS consists of two PWM controllers which can be enumerated from ACPI namespace. This change will cause platform device objects to be created for Intel BayTrail PWM controllers which will allow the pwm-lpss driver to bind to them and

[linux-yocto] [PATCH 04/21] spi/pxa2xx-pci: Add support for Intel BYT SPI

From: Chew, Chiau Ee chiau.ee.c...@intel.com The pxa2xx pci glue layer only support CE4100 SPI port by default. To add BYT SPI port support, we make it a generic PCI glue layer by renaming ce4100_xxx to pxa2xx_spi_xxx. This commit is created in reference to Mika's commit during kernel-3.5

[linux-yocto] [PATCH 13/21] i2c: designware-pci: set ideal HCNT, LCNT and SDA hold time value

From: Chew, Chiau Ee chiau.ee.c...@intel.com On Intel BayTrail, there was case whereby the resulting fast mode bus speed becomes slower (~20% slower compared to expected speed) if using the HCNT/LCNT calculated in the core layer. Thus, this patch is added to allow pci glue layer to pass in

[linux-yocto] [PATCH 09/21] usb: gadget: don't fail when DMA isn't present

From: Alan Stern st...@rowland.harvard.edu When CONFIG_HAS_DMA isn't enabled, the UDC core gets build errors: drivers/built-in.o: In function `dma_set_coherent_mask': include/linux/dma-mapping.h:93: undefined reference to `dma_supported' include/linux/dma-mapping.h:93: undefined reference to

[linux-yocto] [PATCH 05/21] spi/pxa2xx: Fix BYT ACPI mode SPI DMA transfer failure at low speeds

From: Chew, Chiau Ee chiau.ee.c...@intel.com BYT ACPI mode SPI not read/writing correctly at low speeds using DMA mode. Fix the issue by changing DMA SRC_MSIZE and DEST_MSIZE of SPI FIFO side from 16 to 32. Signed-off-by: Chew, Chiau Ee chiau.ee.c...@intel.com Signed-off-by: Maurice Petallo

[linux-yocto] [PATCH 12/21] i2c: designware-pci: add 10-bit addressing mode functionality for BYT I2C

From: Chew, Chiau Ee chiau.ee.c...@intel.com All the I2C controllers on Intel BayTrail LPSS subsystem able to support 10-bit addressing mode functionality. Signed-off-by: Chew, Chiau Ee chiau.ee.c...@intel.com Signed-off-by: Ong, Boon Leong boon.leong@intel.com Signed-off-by: Wolfram Sang

[linux-yocto] [PATCH 0/1] [linux-yocto-3.10] [PATCH] Enable PCI mode enumeration for Valley Island

From: Chang Rebecca Swee Fun rebecca.swee.fun.ch...@intel.com Hi all, This patch is to enable PCI mode enumeration for Valley Island LPSS I/O devices. The I/O device drivers that can be PCI enumerated are:- GPIO, I2C Designware, SPI, DW_DMAC. Feature branch will be send out next. There will be

[linux-yocto] [PATCH 01/24] x86/Kconfig: add PCI dependency for CONFIG_X86_INTEL_LPSS

From: Chew, Chiau Ee chiau.ee.c...@intel.com Allow CONFIG_X86_INTEL_LPSS to be set when ACPI or PCI is set. Signed-off-by: Chew, Chiau Ee chiau.ee.c...@intel.com Signed-off-by: Maurice Petallo mauricex.r.peta...@intel.com --- arch/x86/Kconfig | 2 +- 1 file changed, 1 insertion(+), 1

[linux-yocto] [PATCH 00/24] [linux-yocto-3.10] [Scenerio 1] Enable feature branch for Valley Island features

From: Chang Rebecca Swee Fun rebecca.swee.fun.ch...@intel.com Hi all, This is the scenerio 1 that Boon Leong mentioned in the Feature Branch planning email thread. This will be the feature branch that consists of all patches that are queuing into 3.10 LTS/LTSI and also the so called staging

[linux-yocto] [PATCH 02/24] x86/byt: enable board file for Baytrail LPSS PCI mode

From: Chang Rebecca Swee Fun rebecca.swee.fun.ch...@intel.com This commit enables the following: - setup clock tree for PCI mode SPI, DMA and PWM host as the controller drivers require clock information during device/driver probe - register SPI slave - fix device name string for clkdev

[linux-yocto] [PATCH 04/24] spi/pxa2xx-pci: Add support for Intel BYT SPI

From: Chew, Chiau Ee chiau.ee.c...@intel.com The pxa2xx pci glue layer only support CE4100 SPI port by default. To add BYT SPI port support, we make it a generic PCI glue layer by renaming ce4100_xxx to pxa2xx_spi_xxx. This commit is created in reference to Mika's commit during kernel-3.5

[linux-yocto] [PATCH 05/24] spi/pxa2xx: Fix BYT ACPI mode SPI DMA transfer failure at low speeds

From: Chew, Chiau Ee chiau.ee.c...@intel.com BYT ACPI mode SPI not read/writing correctly at low speeds using DMA mode. Fix the issue by changing DMA SRC_MSIZE and DEST_MSIZE of SPI FIFO side from 16 to 32. Signed-off-by: Chew, Chiau Ee chiau.ee.c...@intel.com Signed-off-by: Maurice Petallo

[linux-yocto] [PATCH 06/24] dma: dw: Add suspend and resume handling for PCI mode DW_DMAC.

From: Chew, Chiau Ee chiau.ee.c...@intel.com This is to disable/enable DW_DMAC hw during late suspend/early resume. Since DMA is providing service to other clients (eg: SPI, HSUART), we need to ensure DMA suspends after the clients and resume before the clients are active. Signed-off-by: Chew,

[linux-yocto] [PATCH 10/24] usb: gadget: udc-core: move sysfs_notify() to a workqueue

From: Felipe Balbi ba...@ti.com usb_gadget_set_state() will call sysfs_notify() which might sleep. Some users might want to call usb_gadget_set_state() from the very IRQ handler which actually changes the gadget state. Instead of having every UDC driver add their own workqueue for such a simple

[linux-yocto] [PATCH 11/24] i2c: designware-pci: Add Baytrail PCI IDs

From: Mika Westerberg mika.westerb...@linux.intel.com Intel Baytrail I2C controllers can be enumerated from PCI as well as from ACPI. In order to support this add the Baytrail PCI IDs to the driver. Signed-off-by: Mika Westerberg mika.westerb...@linux.intel.com Signed-off-by: Wolfram Sang

[linux-yocto] [PATCH 15/24] ACPI / LPSS: Add Intel BayTrail ACPI mode PWM

From: Chew, Chiau Ee chiau.ee.c...@intel.com Intel BayTrail LPSS consists of two PWM controllers which can be enumerated from ACPI namespace. This change will cause platform device objects to be created for Intel BayTrail PWM controllers which will allow the pwm-lpss driver to bind to them and

[linux-yocto] [PATCH 14/24] pwm: add support for Intel Low Power Subsystem PWM

From: Mika Westerberg mika.westerb...@linux.intel.com Add support for Intel Low Power I/O subsystem PWM controllers found on Intel BayTrail SoC. Signed-off-by: Mika Westerberg mika.westerb...@linux.intel.com Signed-off-by: Chew, Kean Ho kean.ho.c...@intel.com Signed-off-by: Chang, Rebecca Swee

[linux-yocto] [PATCH 21/24] pinctrl-baytrail: setup IOAPIC interrupt for GPIO clusters on non-ACPI system

From: Chew, Kean Ho kean.ho.c...@intel.com BayTrail GPIO NORTH, SOUTH and SUS clusters use IRQ48, 49 and 50 respectively. On non-ACPI system, we need to setup IOAPIC RTE for device that use interrupt beyond IRQ23. Signed-off-by: Chew, Kean Ho kean.ho.c...@intel.com Signed-off-by: Chew, Chiau Ee

[linux-yocto] [PATCH 22/24] i2c: i801: SMBus patch for Intel Coleto Creek DeviceIDs

From: Seth Heasley seth.heas...@intel.com This patch adds the i801 SMBus Controller DeviceIDs for the Intel Coleto Creek PCH. Signed-off-by: Seth Heasley seth.heas...@intel.com Signed-off-by: Wolfram Sang w...@the-dreams.de (cherry picked from commit f39901c1befa556bc91902516a3e2e46b4a8)

[linux-yocto] [PATCH 01/15] dma: dw: Add suspend and resume handling for PCI mode DW_DMAC.

From: Chew, Chiau Ee chiau.ee.c...@intel.com This is to disable/enable DW_DMAC hw during late suspend/early resume. Since DMA is providing service to other clients (eg: SPI, HSUART), we need to ensure DMA suspends after the clients and resume before the clients are active. Signed-off-by: Chew,

[linux-yocto] [PATCH 06/15] i2c: designware-pci: Add Baytrail PCI IDs

From: Mika Westerberg mika.westerb...@linux.intel.com Intel Baytrail I2C controllers can be enumerated from PCI as well as from ACPI. In order to support this add the Baytrail PCI IDs to the driver. Signed-off-by: Mika Westerberg mika.westerb...@linux.intel.com Signed-off-by: Wolfram Sang

[linux-yocto] [PATCH 09/15] pwm: add support for Intel Low Power Subsystem PWM

From: Mika Westerberg mika.westerb...@linux.intel.com Add support for Intel Low Power I/O subsystem PWM controllers found on Intel BayTrail SoC. Signed-off-by: Mika Westerberg mika.westerb...@linux.intel.com Signed-off-by: Chew, Kean Ho kean.ho.c...@intel.com Signed-off-by: Chang, Rebecca Swee

[linux-yocto] [PATCH 11/15] pwm: Add sysfs interface

From: H Hartley Sweeten hartl...@visionengravers.com Add a simple sysfs interface to the generic PWM framework. /sys/class/pwm/ `-- pwmchipN/ for each PWM chip |-- export (w/o) ask the kernel to export a PWM channel |-- npwm(r/o) number of PWM

[linux-yocto] [PATCH 12/15] mmc: sdhci: Allow for irq being shared

From: Adrian Hunter adrian.hun...@intel.com If the SDHCI irq is shared with another device then the interrupt handler can get called while SDHCI is runtime suspended. That is harmless but the warning message is not useful so remove it. Also returning IRQ_NONE is more appropriate.

[linux-yocto] [PATCH 13/15] pinctrl-baytrail: add function mux checking in gpio pin request

From: Chew, Kean Ho kean.ho.c...@intel.com The requested gpio pin must has the func_pin_mux field set to GPIO function by BIOS/FW in advanced. Else, the gpio pin request would fail. This is to ensure that we do not expose any gpio pins which shall be used for alternate functions, for eg: wakeup

[linux-yocto] [PATCH 15/15] i2c: i801: enable Intel BayTrail SMBUS

From: Chew, Kean ho kean.ho.c...@intel.com Add Device ID of Intel BayTrail SMBus Controller. Signed-off-by: Chew, Kean ho kean.ho.c...@intel.com Signed-off-by: Chew, Chiau Ee chiau.ee.c...@intel.com Reviewed-by: Jean Delvare jdelv...@suse.de Signed-off-by: Wolfram Sang w...@the-dreams.de (cherry

[linux-yocto] [PATCH 2/9] x86/byt: enable board file for Baytrail LPSS PCI mode

From: Chang Rebecca Swee Fun rebecca.swee.fun.ch...@intel.com This commit enables the following: - setup clock tree for PCI mode SPI, DMA and PWM host as the controller drivers require clock information during device/driver probe - register SPI slave - fix device name string for clkdev

[linux-yocto] [PATCH 3/9] serial: 8250_dw: Added support for 1M, 2M, 3M and 4M exat baud rate

From: Chew, Chiau Ee chiau.ee.c...@intel.com This will enable high speed baud rates namely 1M, 2M, 3M, and 4M in Intel Baytrail Designware controller. Signed-off-by: Chew, Chiau Ee chiau.ee.c...@intel.com Signed-off-by: Maurice Petallo mauricex.r.peta...@intel.com ---

[linux-yocto] [PATCH 4/9] spi/pxa2xx-pci: Add support for Intel BYT SPI

From: Chew, Chiau Ee chiau.ee.c...@intel.com The pxa2xx pci glue layer only support CE4100 SPI port by default. To add BYT SPI port support, we make it a generic PCI glue layer by renaming ce4100_xxx to pxa2xx_spi_xxx. This commit is created in reference to Mika's commit during kernel-3.5

[linux-yocto] [PATCH 1/9] x86/Kconfig: add PCI dependency for CONFIG_X86_INTEL_LPSS

From: Chew, Chiau Ee chiau.ee.c...@intel.com Allow CONFIG_X86_INTEL_LPSS to be set when ACPI or PCI is set. Signed-off-by: Chew, Chiau Ee chiau.ee.c...@intel.com Signed-off-by: Maurice Petallo mauricex.r.peta...@intel.com --- arch/x86/Kconfig | 2 +- 1 file changed, 1 insertion(+), 1

[linux-yocto] [PATCH 6/9] pinctrl-baytrail: add function mux checking in gpio pin request

From: Chew, Kean Ho kean.ho.c...@intel.com The requested gpio pin must has the func_pin_mux field set to GPIO function by BIOS/FW in advanced. Else, the gpio pin request would fail. This is to ensure that we do not expose any gpio pins which shall be used for alternate functions, for eg: wakeup

[linux-yocto] [PATCH 7/9] pinctrl-baytrail: unmap interrupt when free the gpio pin

From: Chew, Kean Ho kean.ho.c...@intel.com In to_irq() callback, we create the hwirq to linux irq mapping for the requested GPIO pin. Hence, we unamp the mapping when the gpio pin is being released. Signed-off-by: Chew, Kean Ho kean.ho.c...@intel.com Signed-off-by: Chew, Chiau Ee

[linux-yocto] [PATCH 9/9] pinctrl-baytrail: setup IOAPIC interrupt for GPIO clusters on non-ACPI system

From: Chew, Kean Ho kean.ho.c...@intel.com BayTrail GPIO NORTH, SOUTH and SUS clusters use IRQ48, 49 and 50 respectively. On non-ACPI system, we need to setup IOAPIC RTE for device that use interrupt beyond IRQ23. Signed-off-by: Chew, Kean Ho kean.ho.c...@intel.com Signed-off-by: Chew, Chiau Ee

[linux-yocto] [PATCH 8/9] pinctrl-baytrail: enable platform device in the absent of ACPI enumeration

From: Chew, Kean Ho kean.ho.c...@intel.com This is to cater the need for non-ACPI system whereby a platform device has to be created in order to bind with the BYT Pinctrl GPIO platform driver. Signed-off-by: Chew, Kean Ho kean.ho.c...@intel.com Signed-off-by: Chew, Chiau Ee

[linux-yocto] [PATCH 0/1] [PATCH] meta: add USB feature support for Mohonpeak

From: Chang Rebecca Swee Fun rebecca.swee.fun.ch...@intel.com Hi, Here is a patch to add USB feature support for Mohonpeak platform. We found USB features are missing when we failed to boot images through USB devices. By including the USB features, USB devices such as thumb drive, keyboards and

[linux-yocto] [PATCH 1/1] meta: enable USB features for Mohonpeak

From: Chang Rebecca Swee Fun rebecca.swee.fun.ch...@intel.com Added USB host controller driver support for Mohonpeak. This also enable live bootable image to be able to boot through USB devices. Signed-off-by: Chang Rebecca Swee Fun rebecca.swee.fun.ch...@intel.com ---

[linux-yocto] [PATCH 11/29] i2c: designware-pci: Add support for Intel BayTrail LPSS I2C

From: Chew, Chiau Ee chiau.ee.c...@intel.com This is to enable PCI mode of Intel BayTrail LPSS I2C. This commit is created in reference to Wilson's work during kernel-3.5 development. Signed-off-by: Chew, Chiau Ee chiau.ee.c...@intel.com Signed-off-by: Maurice Petallo

[linux-yocto] [PATCH 00/29] Create new feature branch for Valley Island BSP

From: Chang Rebecca Swee Fun rebecca.swee.fun.ch...@intel.com Hi all, Here is a request to create feature branch to host Valley Island PCI enumerated LPSS I/O device drivers. We expect the patch series to be removed over time. This will give us time to stage a working code while we are working

[linux-yocto] [PATCH 03/29] dma: dw: Fix Intel MID DMA driver and Designware DMA driver loading sequence

From: Chew, Chiau Ee chiau.ee.c...@intel.com There is channel resource contention between Intel MID DMA driver and Designware DMA driver if Intel MID DMA driver is enabled for LPE Audio usage. Since LPIO devices are tied to fixed DMA channel numbers, so the Designware DMA controller has to be

[linux-yocto] [PATCH 10/29] usb: dwc3: pci: Enable/disable ulpi phy refclk

From: Maurice Petallo mauricex.r.peta...@intel.com Due to power saving purpose, BIOS disabled ulpi phy refclk by default. Hence, the refclk will only be enabled during device/driver probing. and disabled during driver removal. Signed-off-by: Maurice Petallo mauricex.r.peta...@intel.com

[linux-yocto] [PATCH 16/29] mmc: sdhci: Force BYT SDCARD host to run with SDR25 mode

From: Chew, Kean Ho kean.ho.c...@intel.com The clock appears to be unstable when SDCARD host running with DDR50 mode, thus causing CRC issue. This is to introduce a new quirk to force host with broken DDR50 mode to run with SDR25 mode. Signed-off-by: Chew, Kean Ho kean.ho.c...@intel.com

[linux-yocto] [PATCH 04/29] dma: dw: Implement suspend/resume callbacks

From: Chew, Chiau Ee chiau.ee.c...@intel.com This will add PCI mode suspend and resume callbacks to support system suspend to and resume from S3. Signed-off-by: Chew, Chiau Ee chiau.ee.c...@intel.com Signed-off-by: Maurice Petallo mauricex.r.peta...@intel.com --- drivers/dma/dw/pci.c | 36

[linux-yocto] [PATCH 06/29] serial: 8250_pci: add support for Intel BayTrail

From: Heikki Krogerus heikki.kroge...@linux.intel.com Intel BayTrail has two HS-UARTs with 64 byte fifo, support for DMA and support for 16750 compatible Auto Flow Control. Signed-off-by: Heikki Krogerus heikki.kroge...@linux.intel.com Signed-off-by: Greg Kroah-Hartman gre...@linuxfoundation.org

[linux-yocto] [PATCH 22/29] pwm: Add sysfs interface

From: H Hartley Sweeten hartl...@visionengravers.com Add a simple sysfs interface to the generic PWM framework. /sys/class/pwm/ `-- pwmchipN/ for each PWM chip |-- export (w/o) ask the kernel to export a PWM channel |-- npwm(r/o) number of PWM

[linux-yocto] [PATCH 13/29] i2c: designware-pcidrv: Option to set custom HCNT, LCNT and SDA value

From: Chew, Chiau Ee chiau.ee.c...@intel.com Provide option to set the HCNT, LCNT and SDA if the target values are known ahead. Instead of depends on formula to calculate the HCNT and LCNT. Signed-off-by: Chew, Chiau Ee chiau.ee.c...@intel.com Signed-off-by: Maurice Petallo

[linux-yocto] [PATCH 24/29] mmc: sdhci: Fix continuous warning prints in ISR if shared interrupt

From: Maurice Petallo mauricex.r.peta...@intel.com sdhc host may share same interrupt line with other IO devices that trigger interrupt frequently, like USB. In this case, we encountered continous prints of warning message got irq while runtime suspended when the interrupt triggered by other IO

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