From: Dinh Nguyen <dinh.ngu...@intel.com>
commit b002bf552cb779951ca843a058545dc146989270 from
https://github.com/altera-opensource/linux-socfpga.git
Populate the clocks property in the watchdog timers on Stratix10.
Signed-off-by: Dinh Nguyen <dinh.ngu...@intel.com>
Signed-off-by: Meng Li <meng...@windriver.com>
---
arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi
b/arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi
index c8bc964..dc0a4a6 100644
--- a/arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi
+++ b/arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi
@@ -882,6 +882,7 @@
reg = <0xffd00200 0x100>;
interrupts = <0 117 4>;
resets = <&rst WATCHDOG0_RESET>;
+ clocks = <&l4_sys_free_clk>;
status = "disabled";
};
@@ -890,6 +891,7 @@
reg = <0xffd00300 0x100>;
interrupts = <0 118 4>;
resets = <&rst WATCHDOG1_RESET>;
+ clocks = <&l4_sys_free_clk>;
status = "disabled";
};
@@ -898,6 +900,7 @@
reg = <0xffd00400 0x100>;
interrupts = <0 125 4>;
resets = <&rst WATCHDOG2_RESET>;
+ clocks = <&l4_sys_free_clk>;
status = "disabled";
};
@@ -906,6 +909,7 @@
reg = <0xffd00500 0x100>;
interrupts = <0 126 4>;
resets = <&rst WATCHDOG3_RESET>;
+ clocks = <&l4_sys_free_clk>;
status = "disabled";
};
--
1.7.9.5
--
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