From: Jonas Svennebring <jonas.svennebr...@gmail.com>
AXXIA uncore perf support, fixes for the following issues:
- Added files to makefile, build based on CONFIG_HW_PERF_EVENTS.
- Added support for silicon rev 1.1 changes to DDR controllers.
- Changed default to use rev 1.1 silicon register map.
If rev 1.0 is needed the AXM55XX_Rn definition needs to be
changed in perf_event_platform.h. The rev 1.0 silicon had
some register address differences. Due to the limited number
of rev 1.0 boards availible the selection is solved this way
and rev 1.0 will be depricated at a later stage.
- Removed two unused functions that triggered compilation warnings.
The AXXIA memory blocks, other than caches and CCN which are
handled with respective driver, can be accessed by raw counters.
Perf offsets are set in mach-axxia/perf_event_platform.h.
Each memory controller supports two active events.
Default raw events are based on the following system:
0x 10000 AXXIA Platform counters
0x 8 Memory subsystem
0 SMC0 (DDR controller 0)
1 SMC1 (DDR controller 1)
2 ELM0
3 ELM1
nn event id, see ref. man for detailed list.
Key SMC events are:
0 Uncorrectable ECC errors
1 Correctable ECC errors
13 Write request issued (i.e. 64B cache line)
16 Read request issued (i.e. 64B cache line)
Note: Perf cli tool does not efficiently support platform events
today, ensure that these are only accessed through one core, ex.
by using -C 0.
perf stat -C 0 -e r18013,r18016,r18113,r18116 sleep 1
Signed-off-by: Jonas Svennebring <jonas.svennebr...@gmail.com>
---
arch/arm/mach-axxia/Makefile | 1 +
arch/arm/mach-axxia/perf_event_memc.c | 29 ++++++++++++++++++-----------
arch/arm/mach-axxia/perf_event_memc.h | 7 ++++++-
arch/arm/mach-axxia/perf_event_platform.h | 2 +-
arch/arm/mach-axxia/perf_event_vp.c | 4 ----
5 files changed, 26 insertions(+), 17 deletions(-)
diff --git a/arch/arm/mach-axxia/Makefile b/arch/arm/mach-axxia/Makefile
index 8bea5f1..5b4c6f9 100644
--- a/arch/arm/mach-axxia/Makefile
+++ b/arch/arm/mach-axxia/Makefile
@@ -13,3 +13,4 @@ obj-$(CONFIG_SMP) += platsmp.o headsmp.o
obj-$(CONFIG_ARCH_AXXIA_GIC) += axxia-gic.o
obj-$(CONFIG_HOTPLUG_CPU) += hotplug.o lsi_power_management.o
axxia_circular_queue.o
obj-$(CONFIG_AXXIA_RIO) += rapidio.o
+obj-$(CONFIG_HW_PERF_EVENTS) += perf_event_platform.o smon.o
diff --git a/arch/arm/mach-axxia/perf_event_memc.c
b/arch/arm/mach-axxia/perf_event_memc.c
index a20fc8a..2abd47a 100644
--- a/arch/arm/mach-axxia/perf_event_memc.c
+++ b/arch/arm/mach-axxia/perf_event_memc.c
@@ -13,22 +13,37 @@
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307
USA
*/
#include "perf_event_memc.h"
static void memc_startup_init(void)
{
+ uint32_t config;
+
smon_init_ncp(&ddrc0_smon, DDRC0, DDRC_PERF, DDRC_SMON);
smon_init_ncp(&ddrc1_smon, DDRC1, DDRC_PERF, DDRC_SMON);
smon_init_mem(&elm0_smon, ELM0, ELM_SMON);
smon_init_mem(&elm1_smon, ELM1, ELM_SMON);
+
+ /* enable SMC SMON registers */
+ ncr_read(NCP_REGION_ID(DDRC0, DDRC_CTRL), CTRL_SMON,
+ REG_SZ, &config);
+ config |= SMON_ENABLE;
+ ncr_write(NCP_REGION_ID(DDRC0, DDRC_CTRL), CTRL_SMON,
+ REG_SZ, &config);
+
+ ncr_read(NCP_REGION_ID(DDRC1, DDRC_CTRL), CTRL_SMON,
+ REG_SZ, &config);
+ config |= SMON_ENABLE;
+ ncr_write(NCP_REGION_ID(DDRC1, DDRC_CTRL), CTRL_SMON,
+ REG_SZ, &config);
}
static uint32_t memc_pmu_event_init(uint32_t event, struct perf_event *pevent)
@@ -36,14 +51,6 @@ static uint32_t memc_pmu_event_init(uint32_t event, struct
perf_event *pevent)
return 0;
}
-static void memc_pmu_event_destroy(uint32_t event, struct perf_event *pevent)
-{
- smon_stop_if_unassigned(&ddrc0_smon);
- smon_stop_if_unassigned(&ddrc1_smon);
- smon_stop_if_unassigned(&elm0_smon);
- smon_stop_if_unassigned(&elm1_smon);
-}
-
static uint32_t memc_pmu_event_add(uint32_t ev, struct perf_event *pevent)
{
uint32_t ret;
@@ -93,7 +100,7 @@ static uint32_t memc_pmu_event_add(uint32_t ev, struct
perf_event *pevent)
* Remove event and return counter update.
*/
static uint32_t memc_pmu_event_del(uint32_t ev, struct perf_event *pevent,
- int flags)
+ int flags)
{
uint32_t count = 0;
diff --git a/arch/arm/mach-axxia/perf_event_memc.h
b/arch/arm/mach-axxia/perf_event_memc.h
index e4a4f7d..6e9ba51 100644
--- a/arch/arm/mach-axxia/perf_event_memc.h
+++ b/arch/arm/mach-axxia/perf_event_memc.h
@@ -38,9 +38,11 @@
#define DDRC0 0x0f
#define DDRC1 0x22
/* Target */
+#define DDRC_CTRL 0x00
#define DDRC_PERF 0x02
-
/* Address */
+#define CTRL_SMON 0x1fc
+
#ifdef AXM55XX_R1
#define DDRC_SMON 0x40
#endif
@@ -48,6 +50,9 @@
#define DDRC_SMON 0xA0
#endif
+/* Settings */
+#define SMON_ENABLE 0x20000000
+
/* Base Address */
#define ELM0 0x2010060000
#define ELM1 0x2010070000
diff --git a/arch/arm/mach-axxia/perf_event_platform.h
b/arch/arm/mach-axxia/perf_event_platform.h
index 5446855..29698c5 100644
--- a/arch/arm/mach-axxia/perf_event_platform.h
+++ b/arch/arm/mach-axxia/perf_event_platform.h
@@ -1,4 +1,4 @@
- #define AXM55XX_R1
+#define AXM55XX_R2 "1.1"
#define AXM_55XX_PLATFORM_BASE 0x10000
#define AXM_55XX_VP_BASE (AXM_55XX_PLATFORM_BASE + 0x00)
diff --git a/arch/arm/mach-axxia/perf_event_vp.c
b/arch/arm/mach-axxia/perf_event_vp.c
index 3993f24..e20f2db 100644
--- a/arch/arm/mach-axxia/perf_event_vp.c
+++ b/arch/arm/mach-axxia/perf_event_vp.c
@@ -45,7 +45,3 @@ static uint32_t vp_pmu_event_del(uint32_t event, struct
perf_event *pevent,
{
return 0;
}
-
-static void vp_pmu_event_destroy(uint32_t event, struct perf_event *pevent)
-{
-}
--
1.8.1.4
--
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