Hi Sone,
Thanks for the comments, looks like an update to the update will be on it's
way shortly !
On Friday 18 Jul 2003 05:56, SONE Takeshi wrote:
On Fri, Jul 18, 2003 at 01:29:48AM +0100, Mark Wilkinson wrote:
Just a quick note to say that I've updated my EPIA howto to include
On Fri, Jul 18, 2003 at 07:20:22AM +0100, Mark Wilkinson wrote:
Will correct that, although what I can remember from the northbridge docs is
that a setting of 0 also disables the framebuffer - perhaps this option is
really a 'have framebuffer, but don't share with it memory option'
I am new to linux bios. My project is based on geode chip. I want my linuxOS to be in Flash ROM(capacity 4 MB). I saw the HOW-TO for Sis based on DiskOnChip. What I have to modify and what other information i have to add if I want to boot from Flash ROM into SDRAM.
Please help.
Thanks.
Do you
On Fri, 18 Jul 2003, John Praveen wrote:
I am new to linux bios. My project is based on
geode chip. I want my linux OS to be in Flash ROM(capacity 4 MB).
I have sad news. You can't get a 4 MB chip on that board, I bet. It is
probably 4 Mbits, 512 KB. You'll have to
Hi,
OK, looks like Ill be implementing this unless Andrew Ip already
committed something (but I have not seen it).
Not yet. I still have to work on the DDR config for EPIA-M. Help
are welcome. :)
-Andrew
--
Andrew Ip
Email: [EMAIL PROTECTED]
Tel:(852) 2542 2046
Fax:(852) 2542
On Fri, 18 Jul 2003, Dave Ashley wrote:
Inside src/arch/i386/lib/idt.c
case MEMSIZE:
// who cares.
eax = 64 * 1024;
ret = 0;
break;
+#ifdef CONFIG_INT21HANDLER
+ case 0x15:
+ ret=handleint21( edi, esi, ebp,
On Fri, 18 Jul 2003, Dave Ashley wrote:
How would C code work without the DRAM present? C requires a stack. I'd like
to understand this if it is actually possible :^).
freebios2/util/romcc. Needs no memory.
read all about it. Quite cool.
ron
___
Setting up a c-diff would be tricky on my end. The CVS checkout doesn't
actually work as described in the linuxbios web page. I had to download the
daily snapshot, then extract that into my own cvs server, then check that
out to get the code. However I then started checking stuff back in since it
are you sure that the I2C is not being read now on EPIA-M? I have not
looked but it seems it ought to be.
ron
___
Linuxbios mailing list
[EMAIL PROTECTED]
http://www.clustermatic.org/mailman/listinfo/linuxbios
I'm not sure of anything, except that epia-m currently hardcodes the dram
settings which isn't optimum. My approach was going to be
A) Figure out how bloatware lm_sensors is reading the eeprom
B) Understand the underlying mechanics
C) Look for similiar functionality/implementation in
On Fri, Jul 18, 2003 at 08:08:24AM -0600, ron minnich wrote:
suggestion: next week the config tool should be basically done for
freebios2. You folks cold look at converting DRAM code to C and porting
the EPIA code to freebios2. It is about 100 times easier to code this
stuff up in C.
My
I used the freebios/util/scanspd code as a starting point and found out
the DDR ram is at slot 0x50 and can be accessed through standard SMBus reads
at io ports 0x500+. A dump of my working eeprom is this:
128 8 7 12 10 1 64 0 4 117 117 0 128 8 0 1
14 4 12 1 2 32 0 160 117 0 0 80 60 80 45 32
144
When I write some assembly code and I've got the syntax wrong, the build
fails but the line numbers reported in error messages don't relate to the
source I'm working on. I'm wondering could the build process for the assembly
code be changed so the python script creates a global
toplevel.asm
file
On Fri, 18 Jul 2003, Dave Ashley wrote:
What disadvantages does SPD have other than it is more complex? Wouldn't it
let you then be able to correctly use any DDR module you want?
some SPD roms have incorrect information. You have to take care with SPD.
Overall, SPD is better. However, if you
* ron minnich [EMAIL PROTECTED] [030718 21:12]:
On Fri, 18 Jul 2003, Dave Ashley wrote:
What disadvantages does SPD have other than it is more complex? Wouldn't it
let you then be able to correctly use any DDR module you want?
some SPD roms have incorrect information. You have to take
On Fri, 18 Jul 2003, Stefan Reinauer wrote:
some SPD roms have incorrect information. You have to take care with SPD.
Does this happen if you buy cheap ram, or ram of a certain type?
You need to find quality vendors and stick with them. Even then, you can
get in trouble.
How can this
Dave Ashley [EMAIL PROTECTED] writes:
I used the freebios/util/scanspd code as a starting point and found out
the DDR ram is at slot 0x50 and can be accessed through standard SMBus reads
at io ports 0x500+. A dump of my working eeprom is this:
128 8 7 12 10 1 64 0 4 117 117 0 128 8 0 1
14
Dave Ashley [EMAIL PROTECTED] writes:
When I write some assembly code and I've got the syntax wrong, the build
fails but the line numbers reported in error messages don't relate to the
source I'm working on. I'm wondering could the build process for the assembly
code be changed so the python
On 18 Jul 2003, Eric W. Biederman wrote:
There's nothing especially bad about ASM code development, but things
like accurate error reporting can make it easier (or harder when absent).
I agree it is nice not to need an intermediate step. Unless it is an absolutely
trivial change we
src/sdram/smbus_pcibus.inc has some smbus code, I was able to compile it
into the epia-m tree and do some test SMBUS_READ_BYTE calls that actually
read out values from the ddr eeprom. I had to #if out the section that
actually does the dram configuration to get it to compile.
I'm in a bad way for
On Fri, 18 Jul 2003, Dave Ashley wrote:
the BIOS and plug in a new one if something goes bad, and do the reverse
to recover. I've fried 2 motherboards with my pliers rubbing out traces
under the flashrom socket (good luck fixing that!).
you need to go to radioshack and get the flash part
This is what the new configuration scheme in freebios2 does.
Greg
At 2:25 PM -0700 18/7/03, Dave Ashley wrote:
When I write some assembly code and I've got the syntax wrong, the build
fails but the line numbers reported in error messages don't relate to the
source I'm working on. I'm wondering
Stefan Reinauer wrote:
* ron minnich [EMAIL PROTECTED] [030718 21:12]:
On Fri, 18 Jul 2003, Dave Ashley wrote:
What disadvantages does SPD have other than it is more complex? Wouldn't it
let you then be able to correctly use any DDR module you want?
some SPD roms have incorrect
On Fri, 18 Jul 2003 17:07:49 -0500, Bari Ari wrote:
Stefan Reinauer wrote:
* ron minnich [EMAIL PROTECTED] [030718 21:12]:
On Fri, 18 Jul 2003, Dave Ashley wrote:
What disadvantages does SPD have other than it is more complex? Wouldn't it
let you then be able to correctly use
ron minnich wrote:
I need something that comes in at ca. $25 ...
Perhaps a high end 450W power supply (cost divided by 4) with a custom
Y cable from a cable maker. In quantity the cables might be cheap
enough. Someone will have to calculate a power budget for each voltage.
It would be best
Hi,
I have an application for IDE hdd hotswap, and I'm trying to determine
the best chipset. I think one thing to consider is the ability or
Linux/LinuxBIOS to completely initialize the chipset from power on reset
to use UltraDMA (133 if possible). If it can do that, logically it can
re-do
Jeremy Jackson wrote:
The second issue is the ability to tri-state off the bus, but I can find
that info elsewhere (ie kernel source) The hdparm utility/kernel driver
has the beginnings of this support.
I know its an old chipset but the 440bx has a bit that you set to
disable the ide[01]
Eric,
My boss has said that I can release the source code to you.
Please find out the patch I made. Make the diff to today's tree.
I didn't test RON new script and still use the old scripts tools.
I strip out the LSI scsi support, because I don't know if there is any
license problem, and I
Hi
Thanks. My Geode one is SC1200.ron minnich [EMAIL PROTECTED] wrote:
On Fri, 18 Jul 2003, John Praveen wrote: I am new to linux bios. My project is based on geode chip. I want my linux OS to be in Flash ROM(capacity 4 MB). I have sad news. You can't get a 4 MB chip on that board, I bet.
I
Hi Dave,
src/sdram/smbus_pcibus.inc has some smbus code, I was able to compile it
into the epia-m tree and do some test SMBUS_READ_BYTE calls that actually
read out values from the ddr eeprom. I had to #if out the section that
actually does the dram configuration to get it to compile.
I'm in
Hi Ron,
are you sure that the I2C is not being read now on EPIA-M? I have not
looked but it seems it ought to be.
DDR init is now hardcoded such that it might work for some DDR but not
all. In long term, SPD will be implemented.
-Andrew
--
Andrew Ip
Email: [EMAIL PROTECTED]
Tel:(852)
YhLu [EMAIL PROTECTED] writes:
Eric,
My boss has said that I can release the source code to you.
Please find out the patch I made. Make the diff to today's tree.
I didn't test RON new script and still use the old scripts tools.
I strip out the LSI scsi support, because I don't know
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