You were right. There is a problem with the sdram
setup. It fails the ramtest.
I set about attempting to dump the memory controller
registers on linux running with phoenix bios (with the
intent of having something to compare with what
linuxbios sets these regs to). i'm not completely sure
if the
* Stefan Reinauer [EMAIL PROTECTED] [050115 22:07]:
enum {
MPTABLE_CPUS,
[..]
ACPI_COMPLETE_TABLES,
} table_t;
and dev::write_tables() would look similar to this:
static void amd8111_write_tables(device_t dev, table_t id)
{
struct resource *res;
* Ronald G. Minnich rminnich@lanl.gov [050118 03:31]:
no argument that we have to create those tables, I just don't want the
baseline format to be binary, if at all possible. It's very non-portable
to non-x86 systems.
The baseline really is our internal device tree representation.
Everything
The 2350 I believe was the original design from Wyse including water
cooling - I am serious about that - they have a huge aluminum plate on the
CPU with an aluminum pipe to another flange connected to a HUGE heatsink -
as a result I am not able to see which particular Geode it has in it, but,
it
Stefan Reinauer [EMAIL PROTECTED] writes:
Hi,
Porting LinuxBIOS to new motherboards has become easier and easier over
the last period of time. There's almost no need for assembler coding
anymore, Hypertransport featured systems do a completely automatical
setup of their non coherent
Li-Ta Lo [EMAIL PROTECTED] writes:
On Tue, 2005-01-11 at 16:52, Ronald G. Minnich wrote:
Ollie, you did it!
We should thank SciTech for their wonderful emulator.
Yes.
Ollie just took a big stack of video cards, some AGP and some PCI, and
booted linuxbios one at a time and showed
YhLu could you please, please, please fix your mailer so it
sets In-Reply-To: and References: correctly or could you switch
to a mailer that does. Catching up on a conversation like
this when all of the threads are chopped in to little pieces
is a major pain.
It does not help that you are also
* Eric W. Biederman ebiederman@lnxi.com [050118 12:51]:
I agree that there is an issue particularly with respect to
interrupts. A lot of this has waited until we have the time to
do this properly.
I agree. However I also think we are coming close to the point were
the existing
* [EMAIL PROTECTED] [EMAIL PROTECTED] [050118 02:06]:
What was the a reason you had to move to the alpha version for the
userspace program in V2? Seems like a lot of trouble for not much
real gain.
It is used because it is in FC2. I believe it is in recent SuSe too.
I think it is
Hi,
as far as I see CPU-CPU HT links are configured with 800MHz at max.
C0 and newer K8 CPUs should be able to do 1000. Is there any reason not
to enable this in such case?
Also, if there happened to be 8131 which do 800MHz on the link,
can we make this configurable via cmos or is Config.lb the
I'm right now trying to install the linuxbios on a DFI P4M266A-MLV board can
somebody help me how to make this step by step...:
I want to install by a boot floppy is it possible?
Please help me!
_
Del din verden med
Ive been stuck at
this problem for a while. My linuxbios boots a NON-SMP kernel ok but not the
SMP one.
The SMP kernel gets loaded
and run. When it tries to access an IDE drive, an IDE command timed out before anything
returns(kernel messages). My I/O APIC settings correspond
to the MP
Hamish Guthrie Maillists wrote:
The 2350 I believe was the original design from Wyse including water
cooling - I am serious about that - they have a huge aluminum plate on the
CPU with an aluminum pipe to another flange connected to a HUGE heatsink -
as a result I am not able to see which
Frank wrote:
Just FYI we're working on V2 for the CN400 (Epia-nano).
-Bari
The board looks very attractive for an application I'm thinking
about. If I were to go out and buy an Epia board tomorrow, which
one should I get if I want to use V2...
Anyone know the status of all the Epia's working with
On Jan 18, 2005, at 4:51 AM, Eric W. Biederman wrote:
Stefan Reinauer [EMAIL PROTECTED] writes:
* ACPI tables need information on the Apics as well. Now the ACPI
implementation I wrote a longer while ago is completely static and
basically only works for systems with a single IOAPIC and not
* Greg Watson [EMAIL PROTECTED] [050118 15:56]:
The only issue really is what format to use for serialization. I'm
leaning towards s-expressions for use with openbios. However, it's
conceivable that different serialzation methods could be provided for
different payloads, though probably not
Hi Bari,
Quoting Bari Ari [EMAIL PROTECTED]:
Frank wrote:
Just FYI we're working on V2 for the CN400 (Epia-nano).
-Bari
The board looks very attractive for an application I'm thinking
about. If I were to go out and buy an Epia board tomorrow, which
one should I get if I want to use V2...
Anyone
On Tue, 18 Jan 2005 [EMAIL PROTECTED] wrote:
CVS is upto date with my current northbridge code, but not my clean up of the
southbridge code.
arg! I thought I had applied this, can you resend.
ron
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This is the geode chipset, right?
Seems to me that
lspci -xxx -s 0:0.0 will give you all you need, or is there some other
place that dram config gets stored?
ron
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On Tue, 2005-01-18 at 04:54, Eric W. Biederman wrote:
Li-Ta Lo [EMAIL PROTECTED] writes:
On Tue, 2005-01-11 at 16:52, Ronald G. Minnich wrote:
Ollie, you did it!
We should thank SciTech for their wonderful emulator.
Yes.
Ollie just took a big stack of video cards, some
* Li-Ta Lo [EMAIL PROTECTED] [050118 17:14]:
Some of them don't have correct 0x55aa signature. All of them have
wrong Class code.
Then it is not a pci option rom as described by the standard. Do they
have the other pci option rom structs?
___
It is weird that fuctory bios can still use them.
There's gotta be a hack in fuctory bios, I would guess, something like:
if (the pci card is a vga there is an option rom)
callit();
i.e. I betcha that fuctory bioses will call an option rom on vga even if
it violates the spec.
I
It is used because it is in FC2. I believe it is in recent SuSe too.
I think it is requred for x86_64.
I changed it to be configurable in the Makefile. Just enter your libpci
version there and it will compile. Unfortunately there is no simple way
I didn't see that in V2 makefile I was
* Richard Smith [EMAIL PROTECTED] [050118 17:40]:
It is used because it is in FC2. I believe it is in recent SuSe too.
I think it is requred for x86_64.
I changed it to be configurable in the Makefile. Just enter your libpci
version there and it will compile. Unfortunately there is
On Tue, Jan 18, 2005 at 08:19:47AM -0600, Bari Ari wrote:
Anyone ever get the VSA ROM to work with LinuxBIOS?
I don't think so. I had a document describing how to set up VSA that
I acquired outside of NDA (download from NSC website) with which one
could have made a VSM loader for LinuxBIOS, but
On Tue, 2005-01-18 at 09:29, Ronald G. Minnich wrote:
It is weird that fuctory bios can still use them.
There's gotta be a hack in fuctory bios, I would guess, something like:
if (the pci card is a vga there is an option rom)
callit();
i.e. I betcha that fuctory bioses will call
It is weird that fuctory bios can still use them.
There's gotta be a hack in fuctory bios, I would guess, something like:
if (the pci card is a vga there is an option rom)
callit();
i.e. I betcha that fuctory bioses will call an option rom on vga even if
it violates the spec.
On Tue, 2005-01-18 at 10:06, Richard Smith wrote:
It is weird that fuctory bios can still use them.
There's gotta be a hack in fuctory bios, I would guess, something like:
if (the pci card is a vga there is an option rom)
callit();
i.e. I betcha that fuctory bioses will
Do cvs update. The path is still hardcoded.
Both the #include statements in the .c files and the path to the
library had to be changed.
Why did you have to change the #include statements?!?
The include is linux/pci so it will grab my system copy of the
headers.. I can't update the
i.e. I betcha that fuctory bioses will call an option rom on vga even if
it violates the spec.
I doubt that.. I've scrubbed the 0xAA55 from several VGA cards so I
could plug them into a factory bios system and not have the VGA
enabled. None of them ever went ahead and ran the bios.
I can
The include is linux/pci so it will grab my system copy of the
Oops that should have been pci/pci.h
I see you tweaked on the source a bit. Yeah this was not present in
the stuff I was working with.
It compiles fine now. Thanks.
--
Richard A. Smith
Maybe I need to change my mail program. What should I use?
YH
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About APIC and ACPI.
Some chipset has problems with apic and the workaround must to be used with
acpi BIOS.
YH
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Maybe need to check the CPU rev to find out the errata to be applied to
limit the speed to 800Mz. That would be easy.
YH
-Original Message-
From: Stefan Reinauer [mailto:[EMAIL PROTECTED]
Sent: Tuesday, January 18, 2005 5:30 AM
To: linuxbios@clustermatic.org
Subject: configurable HT
Ollie,
I fixed one bug in the class code ...in pci_rom.c. please check it. ...
YH
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Ronald G. Minnich wrote:
Who's a good supplier for the epia-nano?
I don't know. We're building our own CN400 design.
Here are some systems that use the Via-N Nano-ITX board:
http://www.viaembedded.com/product/reference_design_story.jsp?motherboardId=221
-Bari
On Tue, 18 Jan 2005 10:07:00 -0800, YhLu [EMAIL PROTECTED] wrote:
Maybe I need to change my mail program. What should I use?
Thunderbird. http://www.mozilla.org
--
Richard A. Smith
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Can I use that to connect Exchange Server in IMAP?
YH
-Original Message-
From: Richard Smith [mailto:[EMAIL PROTECTED]
Sent: Tuesday, January 18, 2005 10:13 AM
To: YhLu
Cc: ebiederman@lnxi.com; Li-Ta Lo; Sagiv Yefet; LinuxBIOS
Subject: Re: Running with VGA
On Tue, 18 Jan 2005 10:07:00
On Tue, 2005-01-18 at 11:13, YhLu wrote:
Ollie,
I fixed one bug in the class code ...in pci_rom.c. please check it. ...
YH
Did you check in ?
Ollie
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On Tue, 18 Jan 2005, Stefan Reinauer wrote:
Those platforms rather offer an IEEE 1275-1994 interface (which is
binary+callback, all evil combined, but it is well proven)
the consensus seems to be that we make the tree contain what we need, and
the last step is to generate tables from the
Thats it. The LV-671 board is out on E-bay. If any one wants a very fast
systerm, have a look.
http://cgi.ebay.com/ws/eBayISAPI.dll?ViewItemitem=6737466248
-Adam Talbot
- Original Message -
From: Ronald G. Minnich rminnich@lanl.gov
To: Adam Talbot [EMAIL PROTECTED]
Cc:
* YhLu [EMAIL PROTECTED] [050118 19:34]:
Can I use that to connect Exchange Server in IMAP?
Yes, it works fine.
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Yes. I swap the class_hi and class_lo in pci_rom.h
YH
-Original Message-
From: Li-Ta Lo [mailto:[EMAIL PROTECTED]
Sent: Tuesday, January 18, 2005 10:31 AM
To: YhLu
Cc: Eric W. Biederman; Ronald G. Minnich; LinuxBIOS
Subject: Re: Overlaping IO resource for AMD K8
On Tue, 2005-01-18 at
My board is similar to Tyan/s2735, does anyone get this booted with a
SMP linux before??
we are buying two of these and hope to have them for test next week.
ron
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Ronald G. Minnich rminnich@lanl.gov writes:
On Tue, 18 Jan 2005, Greg Watson wrote:
I'd like to hear more about what Stefan had in mind for the 'small set of C
functions'. Maybe the simplest way would be to pass the device tree itself
to
the payload? I guess it wouldn't solve the
On Tue, 18 Jan 2005, Eric W. Biederman wrote:
Taking this one step farther I am not at all convinced that we want to even
export a tree. The simplest representation is actually a graph of the
connections between hardware devices. This requires one list of hardware
devices and a second
You are kidding. I put junk in the CVS server?
I guess he still need some time to figure out how to modify his mptable.c.
YH
-Original Message-
From: ebiederman@lnxi.com [mailto:[EMAIL PROTECTED]
Sent: Tuesday, January 18, 2005 11:35 AM
To: Gin
Cc: 'LinuxBIOS'
Subject: Re: SMP linux
On Tue, 18 Jan 2005, Stefan Reinauer wrote:
Also, the 0x55aa sequence has to be at any 4k boundary within the rom.
Before that any data may occur. IIRC the standard does not say that the
option rom image has to start at the beginning of the physical chip.
I never saw that requirement
With normal BIOS, there is option to let End user to select 1000Mhz or
800Hz.
And customer report there is performance difference with that.
YH
In addition I measured it on a dual cpu system and I could not
detect a performance difference based on the link speed so I decided
to play that one
Page 99 of the rev 4.1 GX1 spec shows the SDRAM Memory
Controller control registers. That info corresponds
with the addresses that get written by
src/northbridge/nsc/gx1/raminit.inc (also the ones
that I think I'm dumping).
I matched the northbridge pci config space config (the
lspci -xxx -s
On Tue, 18 Jan 2005, ramesh bios wrote:
Page 99 of the rev 4.1 GX1 spec shows the SDRAM Memory
do you have URL handy for this?
ron
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On Tue, 18 Jan 2005, YhLu wrote:
With normal BIOS, there is option to let End user to select 1000Mhz or
800Hz.
wow. Is this strictly legal?
ron
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On Tue, 2005-01-18 at 12:58, Ronald G. Minnich wrote:
On Tue, 18 Jan 2005, Stefan Reinauer wrote:
Also, the 0x55aa sequence has to be at any 4k boundary within the rom.
Before that any data may occur. IIRC the standard does not say that the
option rom image has to start at the beginning
Eric,
When can you put the E7520 support on the CVS server?
I have worked out all amd64 dual core support even on 8 way system and want
to play something else.
Regards
YH
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Stefan Reinauer [EMAIL PROTECTED] writes:
* Eric W. Biederman ebiederman@lnxi.com [050118 12:51]:
I agree that there is an issue particularly with respect to
interrupts. A lot of this has waited until we have the time to
do this properly.
I agree. However I also think we are coming
Greg Watson [EMAIL PROTECTED] writes:
On Jan 18, 2005, at 4:51 AM, Eric W. Biederman wrote:
The only issue really is what format to use for serialization. I'm leaning
towards s-expressions for use with openbios. However, it's conceivable that
different serialzation methods could be provided
[EMAIL PROTECTED] writes:
Hi Bari,
I have the plain old VIA EPIA (800/5000) working a good 80 % of the time.
Not sure if my problems are buggy northbridge setup or buggy motherboard - it
generates some spurious serial at power on, and sometimes hangs reading the
smbus to size the ram.
YhLu [EMAIL PROTECTED] writes:
You are kidding. I put junk in the CVS server?
No. I just could not remember if it was a recent or an ancient board.
If it was an ancient board in the v2 tree I could see problems.
I guess he still need some time to figure out how to modify his mptable.c.
Eric
I moved that from V1 to V2 before you change the cpu initialization
structure.
YH
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YhLu [EMAIL PROTECTED] writes:
Eric,
When can you put the E7520 support on the CVS server?
I have worked out all amd64 dual core support even on 8 way system and want
to play something else.
:)
Currently this is Eric limited :) I need to send off the latest version
of my kexec work to
On Jan 18, 2005, at 1:19 PM, Eric W. Biederman wrote:
Greg Watson [EMAIL PROTECTED] writes:
On Jan 18, 2005, at 4:51 AM, Eric W. Biederman wrote:
The only issue really is what format to use for serialization. I'm
leaning
towards s-expressions for use with openbios. However, it's
conceivable that
Greg Watson [EMAIL PROTECTED] writes:
An arbitrary graph seems to be adding additional complexity that we don't
really
need. Do you have an example of where a tree won't actually suffice?
The way interrupts are hooked up on most every board, I have seen including
dec alphas.
When you add
Committed.
Please check it.
i wonder what the different between
offs = ( pci_read_config16(dev, pos + PCI_CAP_FLAGS) (110)) ?
PCI_HT_SLAVE1_OFFS : PCI_HT_SLAVE0_OFFS;
and
offs = ( (pci_read_config16(dev, pos + PCI_CAP_FLAGS) 10) 1) ?
PCI_HT_SLAVE1_OFFS : PCI_HT_SLAVE0_OFFS;
All ISA devices are mapped to the I/O IOAPIC at 0xFEC0. But where
do
we set this I/O APIC up? How does it know to route the IRQs to the
local
APIC?
Linux looks at the mptable.
I understand Linux looks at the mptable and looks for IOAPIC entries.
I meant where in Linuxbios do we
You are kidding. I put junk in the CVS server?
Didn't mean to be rude. I just want to be sure.
gin
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Yes, I do.
http://www.intworks.biz/ ramesh/geode_gx1.pdf
The register I've been examining is:
MC_BANK_CFG, on page 114
LinuxBIOS sets it up as:
Probing for DIMM0
Probing for DIMM1
Found DIMM1
Page Size: 1000
Component Banks: 4
Module Banks:2
DIMM size:
I think you may have found a bug I never had time to fix. Certain DIMMs
never worked on my Geodes.
ron
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Does any one have a EPIA-MII 1.2GHz , or the 1.0GHz?? If you would be so
kind as to give me a copy of the output from cat /proc/cpuinfo? Just
would like to no what CPU is on the board. More info then what I can get off
via's web site.
Thank you
-Adam Talbot
Oooh, I guess it's a chance for me to contribute in
some way. :-)
I'm not familiar with DIMM autosizing. But I believe
the problem is coming from the following block of code
that does the module bank detection. At least that's
the first sign of trouble since module bank detection
is done and then
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