If the PCI-Ex hose link training is failed, the kernel will halt at the
PCI scan process on MPC8641HPCN board.
This patch will remove and free the hose from PCI host list if the
PCI hose link training is failed.
Signed-off-by: Zhang Wei [EMAIL PROTECTED]
---
arch/powerpc/platforms/86xx/pci.c |
Signed-off-by: Li Yang [EMAIL PROTECTED]
---
diff --git a/arch/powerpc/boot/dts/ebony.dts b/arch/powerpc/boot/dts/ebony.dts
index 0ec02f4..59bbae2 100644
--- a/arch/powerpc/boot/dts/ebony.dts
+++ b/arch/powerpc/boot/dts/ebony.dts
@@ -31,8 +31,8 @@
reg = 0;
On Wed, 4 Jul 2007, Geert Uytterhoeven wrote:
This is the fourth submission of the new PS3 storage drivers:
[1] ps3: Preallocate bootmem memory for the PS3 FLASH ROM storage driver
[2] ps3: Storage Driver Core
[3] ps3: Storage device registration routines.
[4] ps3: Disk Storage Driver
I was expecting a lower DMM performance but wasn't expecting such a
drain on kernel/network load.
OK, to be clear: you seem to be saying that using the SLOB instead
of the SLAB allocator results in such terrible memory fragmentation
that network performance is degraded by large factors
This patch add DMA sector to MPC8641HPCN board dts.
Signed-off-by: Zhang Wei [EMAIL PROTECTED]
Signed-off-by: Ebony Zhu [EMAIL PROTECTED]
---
arch/powerpc/boot/dts/mpc8641_hpcn.dts | 30 ++
1 files changed, 30 insertions(+), 0 deletions(-)
diff --git
Add channel wait queue and transfer callback dma_xfer_callback().
If the DMA controller and driver support interrupt, when the
transfer is finished, it will wakeup the wait queue
and call the callback function of the channel.
Add dma_async_raw_xfer() to API and device_raw_xfer() to struct
This driver adopts DMA engine API, which could be used for
MEM--MEM, IO_ADDR--MEM and IO_ADDR--IO_ADDR data transfer.
This driver support both Basic and Extended chain mode of Freescale
MPC8xxx DMA controller.
Signed-off-by: Zhang Wei [EMAIL PROTECTED]
Signed-off-by: Ebony Zhu [EMAIL PROTECTED]
Paul Mackerras [EMAIL PROTECTED] writes:
Andreas Schwab writes:
Paul Mackerras [EMAIL PROTECTED] writes:
Manish Ahuja writes:
Repost to fix my email id.
Fix to correct a possible infinite loop or an always true check when the
unsigned long counter i is used in
lmb_add_region()
On Tue, Jul 10 2007, Geert Uytterhoeven wrote:
On Wed, 4 Jul 2007, Geert Uytterhoeven wrote:
This is the fourth submission of the new PS3 storage drivers:
[1] ps3: Preallocate bootmem memory for the PS3 FLASH ROM storage driver
[2] ps3: Storage Driver Core
[3] ps3: Storage device
On Fri, May 18, 2007 at 05:52:45PM +0100, Matt Sealey wrote:
Kumar Gala wrote:
On May 18, 2007, at 9:48 AM, Thomas Gleixner wrote:
On Fri, 2007-05-18 at 15:28 +0100, Matt Sealey wrote:
I think both the MPC52xx GPT0-7 and the SLT0-1 fulfil this fairly
easily.
There is some
Roland Dreier [EMAIL PROTECTED] wrote on 09.07.2007 23:35:31:
Out of curiousity, does this mean that a GRH will be sent on all UD
messages (for non-LL QPs)?
No - the bit instructs the hardware to fetch the GRH parts of the QP
context.
The GRH will only be used if the WQE says so.
Joachim
I just pushed the following patches to the for-2.6.23 branch on
powerpc.git. I intend to ask Linus to pull everything on the
for-2.6.23 branch shortly, unless I hear loud screams to the
contrary. :)
Paul.
Documentation/feature-removal-schedule.txt | 12 +
+Sense and level information follows the Linux convention
+(specified in include/linux/interrupt.h) and should be encoded
+as follows:
+
+ 1 = low to high edge sensitive type enabled
+ 2 = high to low edge sensitive type enabled
+ 4 = active high level sensitive type enabled
I may be missing the obvious, but doesn't that defeat the purpose of
non-executable mappings?
The hardware in question doesn't support non-executable mappings;
Not on a per-page basis, anyway.
otherwise, it'd never have worked in the first place. Note that
this is
only allowed on
In older versions of glibc (through 2.3), the dynamic linker
executes a
small amount of code from the data segment, which is not marked as
executable. A recent change (commit
9ba4ace39fdfe22268daca9f28c5df384ae462cf)
stops this from working; there should be a deprecation period before
What decides if a QP is LL or not?
- R.
Currently we use a high bit in the QP type, which is not how we want to
keep it permanently.
What would you suggest, add two additional LL QP types, or change something
more fundamental
in libibverbs and kernel ib core?
We think we can get along quite
+ [EMAIL PROTECTED]
+ compatible = fsl,mpc8xxx-dma;
Please use a real name, not this xxx stuff.
+ reg = 21000 100;
+ ranges = 0 21000 1000;
These overlap, that can't be right; it is just begging for
trouble.
+
+ [EMAIL PROTECTED]
dma-controller btw. And a space before the { (here and
elsewhere) :-)
Segher
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On 7/10/07, Andrei Konovalov [EMAIL PROTECTED] wrote:
Grant Likely wrote:
From: Grant Likely [EMAIL PROTECTED]
This patch allows multiple xilinxfb devices to be registered and used
Signed-off-by: Grant Likely [EMAIL PROTECTED]
cc: Andrei Konovalov [EMAIL PROTECTED]
---
Looks OK
On 7/10/07, Stuart Yoder [EMAIL PROTECTED] wrote:
document level/sense encoding info for IPIC
interrupt controllers
Signed-off-by: Stuart Yoder [EMAIL PROTECTED]
---
+ 2 = high to low edge sense type enabled
+ 8 = active low level sense type enabled
+
+Note: other
All of the platforms except PPC64 share a common mm_context_t definition.
Defining it in mmu.h avoids duplicating it in the platform specific mmu
header files.
Signed-off-by: Josh Boyer [EMAIL PROTECTED]
---
include/asm-powerpc/mmu-44x.h |5 -
include/asm-powerpc/mmu-8xx.h |
This series of patches do:
(1) unify the PCI/PCI express support
for 83xx/85xx/86xx.
(2) Add basic PCI Express support for mpc8548 Rev 2.0
board.
(3) Add basic PCI support for mpc8568mds board.
The patches have been tested on 8548 rev2.0 with Arcadia 3.1
board, mpc8568mds board and 8641HPCN
From: Roy Zang [EMAIL PROTECTED]
User Freescale pci/pcie common routing for 83xx/85xx/86xx
boards.
Signed-off-by: Roy Zang [EMAIL PROTECTED]
---
arch/powerpc/Kconfig |2 +-
arch/powerpc/platforms/83xx/Kconfig|4 +
arch/powerpc/platforms/83xx/mpc8313_rdb.c
On Tue, Jul 10, 2007 at 04:01:19PM +0200, Segher Boessenkool wrote:
+- compatible : Should be fsl,mpc8xxx-dma
Should _include_, not should _be_. And none of this xxx
business, of course.
Especially since the 85xx/86xx version is not 100% compatible with the
83xx version. How about
On Tuesday 10 July 2007, Josh Boyer wrote:
+#ifdef CONFIG_PPC64
+typedef unsigned long mm_context_id_t;
+
+typedef struct {
+ mm_context_id_t id;
+ u16 user_psize; /* page size index */
+
+#ifdef CONFIG_PPC_MM_SLICES
+ u64 low_slices_psize; /* SLB page size
On Tue, 10 Jul 2007 17:45:11 +0800 Zhang Wei wrote:
Add channel wait queue and transfer callback dma_xfer_callback().
If the DMA controller and driver support interrupt, when the
transfer is finished, it will wakeup the wait queue
and call the callback function of the channel.
Add
On Tue, 2007-07-10 at 18:36 +0200, Arnd Bergmann wrote:
On Tuesday 10 July 2007, Josh Boyer wrote:
+#ifdef CONFIG_PPC64
+typedef unsigned long mm_context_id_t;
+
+typedef struct {
+ mm_context_id_t id;
+ u16 user_psize; /* page size index */
+
+#ifdef
On Tuesday 10 July 2007, Josh Boyer wrote:
+ u16 user_psize; /* page size index */
+
+#ifdef CONFIG_PPC64
This needs to be moved up to encompass the u16 user_psize member as
well, yes?
Yes, of course. my bad.
Arnd
___
Jan-Bernd Themann wrote:
This patch introduces a capability flag that is used by the DLPAR userspace
tool to check which DLPAR features are supported by the eHEA driver.
Missing goto has been included.
Signed-off-by: Jan-Bernd Themann [EMAIL PROTECTED]
applied
Vitaly Bordug wrote:
device_bind_driver() error code returning has been fixed.
release() function has been written, so that to free resources
in correct way; the release path is now clean.
Before the rework, it used to cause
Device '[EMAIL PROTECTED]:1' does not have a release() function,
On Tue, 2007-07-10 at 22:38 +1000, Paul Mackerras wrote:
I just pushed the following patches to the for-2.6.23 branch on
powerpc.git. I intend to ask Linus to pull everything on the
for-2.6.23 branch shortly, unless I hear loud screams to the
contrary. :)
Can we get Ben's new emac driver
hello,
I am trying to implement hugetlbfs on the IBM Bluegene/L IO node
(ppc440) and I have a big problem as well as a few questions to ask
the group. I patched a 2.6.21.6 linux kernel (manually) with Edi
Shmueli's hugetlbfs implementation (found here:
Paul Mackerras wrote:
Andreas Schwab writes:
??? There is no rgn-cnt involved in the comparison.
Look further down in lmb_add_region; there is a second for loop that
does
for (i = rgn-cnt-1; i = 0; i--)
Which is exactly the one quoted above. I still don't see
On 7/10/07, Zhang Wei [EMAIL PROTECTED] wrote:
Add channel wait queue and transfer callback dma_xfer_callback().
If the DMA controller and driver support interrupt, when the
transfer is finished, it will wakeup the wait queue
and call the callback function of the channel.
Add
On Sun, Jul 08, 2007 at 03:15:41PM +0200, Bartlomiej Zolnierkiewicz wrote:
on the argument that drivers/ide/ is going away soon. Most
current distros have already moved over to using libata
exclusively.
The in-kernel default for PATA systems is still IDE subsystem.
In part because
+Sense and level information follows the Linux convention
+(specified in include/linux/interrupt.h) and should be encoded
+as follows:
+
+ 2 = high to low edge sensitive type enabled
+ 8 = active low level sensitive type enabled
... but it is probably worthwhile commentting
... but it is probably worthwhile commentting that sense types 1 4
are not supported; just to fill in the obvious gaps. :-)
Same for sense types 0, 3, 5, 6, ...
Just name the sense types 0 and 1, similar to what all other
OF interrupt controller bindings do.
I'm not really keen on
pci1: [EMAIL PROTECTED] {
interrupt-map-mask = 1f800 0 0 7;
Set the mask to 1800 0 0 7, and you need only 16
entries to encode the swizzle. Except...
+ /* bus 1 , idsel 0x2 Tsi310 bridge secondary */
...interrupts on bus 1
Indentify pci, pcie host by compatible property
fsl,mpc83xx-pci,83xx
fsl,mpc85xx-pci,85xx
fsl,mpc86xx-pci,86xx
and
fsl, mpc85xx-pciex,85xx
fsl, mpc86xx-pciex,86xx
This can't ever work -- if you see compatible = 85xx,
what is it? PCI or PCIe? Or something else perhaps, maybe
a CPU or an
Does it make more sense to call this ppc64/power5+rev3?
This is a change to support new counter setup for oprofile. It may be the
same if there is a revision 4 or 5 etc. So since the internal name was ++
I followed that convention.
I'm not too fussed, but if rev 4 comes out, the
[ added Kou back to cc: ]
On Tuesday 10 July 2007, Sergei Shtylyov wrote:
Hello.
Kumar Gala wrote:
Move to using inline function variant of eieio instead of inline assmebly.
Signed-off-by: Kumar Gala [EMAIL PROTECTED]
applied
Please use host driver name (scc_pata in this case)
This series creates a 32 bit zImage wrapper for a 32 or 64 bit PowerPC
Linux kernel. This allows you to kexec a zImage with its compressed
vmlinux instead of the uncompressed vmlinux elf. The elf is also
packaged as a 64 bit elf for use by kexec-tools for 64 bit kernels.
This series also adds
Record the number of header bytes skipped in the total bytes read field.
This is needed for the initramfs parsing code to find the end of the zip file.
Signed-off-by: Milton Miller [EMAIL PROTECTED]
---
Index: work.git/arch/powerpc/boot/gunzip_util.c
Call gunzip_partial to calculate the remaining length and copy the
data to the user buffer. This makes it shorter and reduces
duplication.
Signed-off-by: Milton Miller [EMAIL PROTECTED]
---
Index: work.git/arch/powerpc/boot/gunzip_util.c
Support code to move cpus around, both a spin loop and c code to
move the cpus before uncompressing and copying the kernel to 0.
The low level code is designed to be included in a crt0 or other
assembly file because it may need to be at a fixed location or there
may be other entry point
Add a set of library routines to manage gross memory allocations.
This code uses an array in bss to store upto 32 entrys with merging
representing a range of memory below rmo_end (aka end of real mode
memory at 0).
To use this code, a platform would set rmo_end, call occupy_memory,
then then
Add code to check if the processor is in 64 or 32 bit mode using
only instructions from the 32 bit subset. If the processor is in
64 bit mode, switch to 32 bit mode by clearing MSR[SF].
Also add a 64 bit procedure descriptor to use as a elf64 entry
point.
Signed-off-by: Milton Miller [EMAIL
An example using the marshalling code that can be entered by sreset.
By linking the marshalling code is at 0 and differentiating a cpu
id from a device tree, it also works for kexec.
Signed-off-by: Milton Miller [EMAIL PROTECTED]
---
For reference only, not intended to be merged.
Index:
+ /* Check if the processor is running in 32 bit mode, using
+ * only 32 bit instructions which should be safe on 32 and
+ * 64 bit processors.
+ *
+ * Subtract the bottom 32 bits of MSR from the full value
+ * recording the result. Since MSR[SF] is in the high
In older versions of glibc (through 2.3), the dynamic linker
executes a
small amount of code from the data segment, which is not marked as
executable. A recent change (commit
9ba4ace39fdfe22268daca9f28c5df384ae462cf)
stops this from working; there should be a deprecation period before
On Jul 10, 2007, at 3:25 PM, Segher Boessenkool wrote:
pci1: [EMAIL PROTECTED] {
interrupt-map-mask = 1f800 0 0 7;
Set the mask to 1800 0 0 7, and you need only 16
entries to encode the swizzle. Except...
+/* bus 1 , idsel 0x2
Hi All,
When support for the PPC44x arch/powerpc port was posted back in May, David
included two serial patches along with it. The short story is that the
powerpc patches were merged in via Paul, but the two serial patches were never
merged. This makes the 44x arch/powerpc port dead on arival
Mikael Pettersson wrote:
2.6.22 + this prints the following on my G3:
pata_pdc2027x :00:0e.0: version 0.9
usec_elapsed for mdelay(37) [35431]
start time: [1184112028]s [775333]us
end time: [1184112028]s [810764]us
pata_pdc2027x :00:0e.0: PLL input clock 1691741 kHz
On Wed, 2007-07-11 at 04:25, Segher Boessenkool wrote:
pci1: [EMAIL PROTECTED] {
interrupt-map-mask = 1f800 0 0 7;
Set the mask to 1800 0 0 7, and you need only 16
entries to encode the swizzle. Except...
+ /* bus 1 ,
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