On Sun, Dec 14 2008, FUJITA Tomonori wrote:
> This is a resend of:
>
> http://marc.info/?l=linux-kernel&m=122482703616607&w=2
>
> =
> From: FUJITA Tomonori
> Subject: [PATCH] powerpc: remove dead BIO_VMERGE_BOUNDARY definition
>
> The block layer dropped the virtual merge feature
> (b8b3e16cfe6
On Mon, 2008-12-15 at 17:59 +1100, Stephen Rothwell wrote:
> Hi Ben,
>
> On Mon, 15 Dec 2008 16:44:21 +1100 Benjamin Herrenschmidt
> wrote:
> >
> > From: Kumar Gala
> >
> > An example calling sequence which we did see:
>
> This one is already in Linus' tree as of today.
Ah indeed, it wasn't
Hi Ben,
On Mon, 15 Dec 2008 16:44:21 +1100 Benjamin Herrenschmidt
wrote:
>
> From: Kumar Gala
>
> An example calling sequence which we did see:
This one is already in Linus' tree as of today.
--
Cheers,
Stephen Rothwells...@canb.auug.org.au
http://www.canb.auug.org.au/~sf
After discussing with chip designers, it appears that it's not
necessary to set G everywhere on 440 cores. The various core
errata related to prefetch should be sorted out by firmware by
disabling icache prefetching in CCR0. We add the workaround to
the kernel however just in case ld firmwares
Currently, we never set _PAGE_COHERENT in the PTEs, we just OR it in
in the hash code based on some CPU feature bit. We also manipulate
_PAGE_NO_CACHE and _PAGE_GUARDED by hand in all sorts of places.
This changes the logic so that instead, the PTE now contains
_PAGE_COHERENT for all normal RAM pa
This makes the MMU context code used for CPUs with no hash table
(except 603) dynamically allocate the various maps used to track
the state of contexts.
Only the main free map and CPU 0 stale map are allocated at boot
time. Other CPU maps are allocated when those CPUs are brought up
and freed if t
The handlers for Critical, Machine Check or Debug interrupts
will save and restore MMUCR nowadays, thus we only need to
disable normal interrupts when invalidating TLB entries.
Signed-off-by: Benjamin Herrenschmidt
---
arch/powerpc/mm/tlb_nohash_low.S | 19 ++-
1 file changed,
Currently, the various forms of low level TLB invalidations are all
implemented in misc_32.S for 32-bit processors, in a fairly scary
mess of #ifdef's and with interesting duplication such as a whole
bunch of code for FSL _tlbie and _tlbia which are no longer used.
This moves things around such th
This patch moves the whole no-hash TLB handling out of line into a
new tlb_nohash.c file, and implements some basic SMP support using
IPIs and/or broadcast tlbivax instructions.
Note that I'm using local invalidations for D->I cache coherency.
At worst, if another processor is trying to execute t
The function flush_HPTE() is used in only one place, the implementation
of DEBUG_PAGEALLOC on ppc32.
It's actually a dup of flush_tlb_page() though it's -slightly- more
efficient on hash based processors. We remove it and replace it by
a direct call to the hash flush code on those processors and t
This renames the files to clarify the fact that they are used by
the hash based family of CPUs (the 603 being an exception in that
family but is still handled by that code).
This paves the way for the new tlb_nohash.c coming via a subsequent
patch.
Signed-off-by: Benjamin Herrenschmidt
---
arc
This reworks the context management code used by 4xx,8xx and
freescale BookE. It adds support for SMP by implementing a
concept of stale context map to lazily flush the TLB on
processors where a context may have been invalidated. This
also contains the ground work for generalizing such lazy TLB
flu
This splits the mmu_context handling between 32-bit hash based processors,
64-bit hash based processors and everybody else. This is preliminary work
for adding SMP support for BookE processors.
Signed-off-by: Benjamin Herrenschmidt
---
v2. address various comments for Josh and Stephen
v3. properl
This adds a local_flush_tlb_mm() call as a pre-requisite for some
SMP work for BookE processors
Signed-off-by: Benjamin Herrenschmidt
---
arch/powerpc/include/asm/tlbflush.h |5 +
1 file changed, 5 insertions(+)
--- linux-work.orig/arch/powerpc/include/asm/tlbflush.h 2008-12-03
14:33:
From: Kumar Gala
An example calling sequence which we did see:
copy_user_highpage -> kmap_atomic -> flush_tlb_page -> _tlbil_va
We got interrupted after setting up the MAS registers before the
tlbwe and the interrupt handler that caused the interrupt also did
a kmap_atomic (ide code) and thus o
This adds supports to the "extended" DCR addressing via
the indirect mfdcrx/mtdcrx instructions supported by some
4xx cores (440H6 and later)
I enabled the feature for now only on AMCC 460 chips
Signed-off-by: Benjamin Herrenschmidt
---
This variant uses "440x6" instead of "440H6". I made no ot
Instead of not defining it at all, this defines the macro as
being empty, thus avoiding ifdef's in call sites when CONFIG_BUG
is not set.
Also removes an extra whitespace in the existing definition
Signed-off-by: Benjamin Herrenschmidt
---
arch/powerpc/include/asm/bug.h | 11 ++-
1 f
We were missing the CPU_FTR_NOEXECUTE bit in our cputable for all
these processors. The result is that update_mmu_cache() would flush
the cache for all pages mapped to userspace which is totally
unnecessary on those processors since we already handle flushing
on execute in the page fault path.
Thi
This series of patches is aimed at supporting SMP on non-hash
based processors. It consists of a rework of the MMU context
management and TLB management, clearly splitting hash32, hash64
and nohash in both cases, adding SMP safe context handling and
some basic SMP TLB management.
There is room for
On Fri, 2008-12-12 at 20:19 +0100, Arnd Bergmann wrote:
> Commit d015fe995 'powerpc/cell/axon-msi: Retry on missing interrupt'
> has turned a rare failure to kexec on QS22 into a reproducible
> error, which we have now analysed.
>
> The problem is that after a kexec, the MSIC hardware still points
On Mon, 15 Dec 2008 08:21:05 +1100
Paul Mackerras wrote:
> Guillaume Knispel writes:
>
> > On Tue, 09 Dec 2008 09:16:50 -0600
> > Timur Tabi wrote:
> >
> > > Guillaume Knispel wrote:
> > >
> > > > blk = NULL; at the end of the loop is what is done in the more used
> > > > rh_alloc_align(), so
On Fri, Dec 12, 2008 at 09:22:02AM -0500, Steven A. Falco wrote:
> This patch adds a dummy GPIO driver, which is useful for SPI devices
> that do not have a physical chip select.
>
> Signed-off-by: Steven A. Falco
> ---
> The SPI subsystem requires a chip-select for each connected slave
> device.
Benjamin Herrenschmidt wrote:
> On Wed, 2008-12-10 at 18:46 -0600, Nathan Lynch wrote:
> > + /* OF on pmac has nodes instead of properties named "l2-cache"
> > +* beneath CPU nodes.
> > +*/
> > + if (!strcmp(np->type, "cpu"))
> > + for_each_child_of_node(np
On Wed, 2008-12-10 at 18:46 -0600, Nathan Lynch wrote:
> + /* OF on pmac has nodes instead of properties named "l2-cache"
> +* beneath CPU nodes.
> +*/
> + if (!strcmp(np->type, "cpu"))
> + for_each_child_of_node(np, child)
> + if (!st
Guillaume Knispel writes:
> On Tue, 09 Dec 2008 09:16:50 -0600
> Timur Tabi wrote:
>
> > Guillaume Knispel wrote:
> >
> > > blk = NULL; at the end of the loop is what is done in the more used
> > > rh_alloc_align(), so for consistency either we change both or we use
> > > the same construction
On Tue, 09 Dec 2008 09:16:50 -0600
Timur Tabi wrote:
> Guillaume Knispel wrote:
>
> > blk = NULL; at the end of the loop is what is done in the more used
> > rh_alloc_align(), so for consistency either we change both or we use
> > the same construction here.
> > I also think that testing for &in
On Mon, 1 Dec 2008 14:53:20 +0300
Anton Vorontsov wrote:
>
> Though, the $subject patch could be merged anytime as it doesn't
> depend on anything else. So, if you'll merge it earlier, that will
> make things a bit easier: -1 patch to resend. ;-)
>
Queued up. Will be sent once the merge window
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